Ben A. Abderazek

26 papers C 6Journal 13Unranked 7
YearRankTypeTitle / Venue / Authors
2010 J jnl
Compiling for Reduced Bit-Width Queue Processors.
J. Signal Process. Syst.
Arquimedes Canedo, Ben A. Abderazek, Masahiro Sowa
2009 J jnl
Compiler Support for Code Size Reduction Using a Queue-Based Processor.
Trans. High Perform. Embed. Archit. Compil.
Arquimedes Canedo, Ben A. Abderazek, Masahiro Sowa
2009 J jnl
Design and implementation of a queue compiler.
Microprocess. Microsystems
Arquimedes Canedo, Ben A. Abderazek, Masahiro Sowa
2009 J jnl
Efficient compilation for queue size constrained queue processors.
Parallel Comput.
Arquimedes Canedo, Ben A. Abderazek, Masahiro Sowa
2008 J jnl
A new code generation algorithm for 2-offset producer order queue computation model.
Comput. Lang. Syst. Struct.
Arquimedes Canedo, Ben A. Abderazek, Masahiro Sowa
2008 — conf
Advanced Optimization and Design Issues of a 32-Bit Embedded Processor Based on Produced Order Queue Computation Model.
EUC (1)
Hiroki Hoshino, Ben A. Abderazek, Kenichi Kuroda
2008 J jnl
Dual-execution mode processor architecture.
J. Supercomput.
Md. Musfiquzzaman Akanda, Ben A. Abderazek, Masahiro Sowa
2008 — conf
Quantitative Evaluation of Common Subexpression Elimination on Queue Machines.
ISPAN
Arquimedes Canedo, Masahiro Sowa, Ben A. Abderazek
2008 — conf
Single Instruction Dual-Execution Model Processor Architecture.
EUC (1)
Taichi Maekawa, Ben A. Abderazek, Kenichi Kuroda
2008 J jnl
The QC-2 parallel Queue processor architecture.
J. Parallel Distributed Comput.
Ben A. Abderazek, Arquimedes Canedo, Tsutomu Yoshinaga, Masahiro Sowa
2007 C conf
An Efficient Code Generation Algorithm for Code Size Reduction Using 1-Offset P-Code Queue Computation Model.
EUC
Arquimedes Canedo, Ben A. Abderazek, Masahiro Sowa
2007 J jnl
Dual-Execution Mode Processor Architecture For Embedded Applications.
J. Mobile Multimedia
Md. Musfiquzzaman Akanda, Ben A. Abderazek, Masahiro Sowa
2007 — conf
Mathematical Model for Multiobjective Synthesis of NoC Architectures.
ICPP Workshops
Ben A. Abderazek, Mushfiquzzaman Akanda, Tsutomu Yoshinaga, Masahiro Sowa
2007 C conf
New Code Generation Algorithm for QueueCore - An Embedded Processor with High ILP.
PDCAT
Arquimedes Canedo, Ben A. Abderazek, Masahiro Sowa
2007 J jnl
Optimizing Reaching Definitions Overhead in Queue Processors.
J. Convergence Inf. Technol.
Yuki Nakanishi, Arquimedes Canedo, Ben A. Abderazek, Masahiro Sowa
2007 C conf
Queue Register File Optimization Algorithm for QueueCore Processor.
SBAC-PAD
Arquimedes Canedo, Ben A. Abderazek, Masahiro Sowa
2006 J jnl
Construction of Hybrid MPI-OpenMP Solutions for SMP Clusters.
Inf. Media Technol.
Ta Quoc Viet, Tsutomu Yoshinaga, Ben A. Abderazek, Masahiro Sowa
2006 J jnl
Design and architecture for an embedded 32-bit QueueCore.
J. Embed. Comput.
Ben A. Abderazek, Sotaro Kawata, Masahiro Sowa
2006 J jnl
High-Level Modeling and FPGA Prototyping of Produced Order Parallel Queue Processor Core.
J. Supercomput.
Ben A. Abderazek, Tsutomu Yoshinaga, Masahiro Sowa
2006 — conf
On the Design of a Dual-Execution Modes Processor: Architecture and Preliminary Evaluation.
ISPA Workshops
Md. Musfiquzzaman Akanda, Ben A. Abderazek, Masahiro Sowa
2006 — conf
Scalable Core-Based Methodology and Synthesizable Core for Systematic Design.
ICPP Workshops
Ben A. Abderazek, Tsutomu Yoshinaga, Masahiro Sowa
2005 C conf
An Efficient Dynamic Switching Mechanism (DSM) for Hybrid Processor Architecture.
EUC
Md. Musfiquzzaman Akanda, Ben A. Abderazek, Sotaro Kawata, Masahiro Sowa
2005 C conf
Modular Design Structure and High-Level Prototyping for Novel Embedded Processor Core.
EUC
Ben A. Abderazek, Sotaro Kawata, Tsutomu Yoshinaga, Masahiro Sowa
2005 J jnl
Parallel Queue Processor Architecture Based on Produced Order Computation Model.
J. Supercomput.
Masahiro Sowa, Ben A. Abderazek, Tsutomu Yoshinaga
2003 C conf
On the Design of a Register Queue Based Processor Architecture (FaRM-rq).
ISPA
Ben A. Abderazek, Soichi Shigeta, Tsutomu Yoshinaga, Masahiro Sowa
2002 — conf
Proposal and Design of a Parallel Queue Processor Architecture (PQP).
IASTED PDCS
Masahiro Sowa, Ben A. Abderazek, Soichi Shigeta, Kirilka Nikolova, Tsutomu Yoshinaga