Belgacem Ben Hedia

20 papers A 1B 2C 9Misc 1Journal 3Unranked 4
YearRankTypeTitle / Venue / Authors
2025 C ed.
Verification and Evaluation of Computer and Communication Systems - 17th International Conference, VECoS 2024, Djerba, Tunisia, October 16-18, 2024, Proceedings
VECoS
Belgacem Ben Hedia, Mohamed Ghazel, Bruno Monsuez
2024 J jnl
Preface to the VECoS 2020 & 2021 special issue of ISSE.
Innov. Syst. Softw. Eng.
Kamel Barkaoui, Belgacem Ben Hedia
2024 C ed.
Verification and Evaluation of Computer and Communication Systems - 16th International Conference, VECoS 2023, Marrakech, Morocco, October 18-20, 2023, Proceedings
VECoS
Belgacem Ben Hedia, Yassine Maleh, Moez Krichen
2022 J jnl
Formal modeling and verification for amplification timing anomalies in the superscalar TriCore architecture.
Int. J. Softw. Tools Technol. Transf.
Benjamin Binder, Mihail Asavoae, Florian Brandner, Belgacem Ben Hedia, Mathieu Jan
2022 B conf
The Role of Causality in a Formal Definition of Timing Anomalies.
RTCSA
Benjamin Binder, Mihail Asavoae, Florian Brandner, Belgacem Ben Hedia, Mathieu Jan
2021 B conf
Is This Still Normal? Putting Definitions of Timing Anomalies to the Test.
RTCSA
Benjamin Binder, Mihail Asavoae, Belgacem Ben Hedia, Florian Brandner, Mathieu Jan
2020 C conf
Scalable Detection of Amplification Timing Anomalies for the Superscalar TriCore Architecture.
FMICS
Benjamin Binder, Mihail Asavoae, Florian Brandner, Belgacem Ben Hedia, Mathieu Jan
2020 C ed.
Verification and Evaluation of Computer and Communication Systems - 14th International Conference, VECoS 2020, Xi'an, China, October 26-27, 2020, Proceedings
VECoS
Belgacem Ben Hedia, Yu-Fang Chen, Gaiyun Liu, Zhenhua Yu
2019 — conf
Towards Formal Co-validation of Hardware and Software Timing Models of CPSs.
CyPhy/WESE
Mihail Asavoae, Imane Haur, Mathieu Jan, Belgacem Ben Hedia, Martin Schoeberl
2018 — conf
Formal Executable Models for Automatic Detection of Timing Anomalies.
WCET
Mihail Asavoae, Belgacem Ben Hedia, Mathieu Jan
2018 C conf
QuaRTOS-DSE: A Tool for Design Space Exploration of Embedded Real-Time System.
ISORC
Briag Le Nabec, Belgacem Ben Hedia, Jean-Philippe Babau
2018 J jnl
TT-BIP: using correct-by-design BIP approach for modelling real-time system with time-triggered paradigm.
Innov. Syst. Softw. Eng.
Hela Guesmi, Belgacem Ben Hedia, Simon Bliudze, Saddek Bensalem, Briag Le Nabec
2017 C conf
TT-BIP: Using Correct-by-Design BIP Approach for Modelling Real-Time System with Time-Triggered Paradigm.
VECoS
Hela Guesmi, Belgacem Ben Hedia, Simon Bliudze, Saddek Bensalem, Briag Le Nabec
2016 C conf
Modeling legacy code with BIP: how to reduce the gap between formal description and real-time implementation.
FDL
Briag Le Nabec, Belgacem Ben Hedia, Jean-Philippe Babau, Mathieu Jan, Hela Guesmi
2016 A conf
Poster Abstract: Towards Correct Transformation: From High-Level Models to Time-Triggered Implementations.
RTAS
Hela Guesmi, Belgacem Ben Hedia, Mathieu Jan, Simon Bliudze, Saddek Bensalem
2016 — conf
Towards an Ultra-lightweight Cryptosystem for IoT.
SoCPaR
Tasnime Omrani, Layth Sliman, Rabei Becheikh, Safya Belghith, Belgacem Ben Hedia
2015 C ed.
Proceedings of the 9th Workshop on Verification and Evaluation of Computer and Communication Systems, VECoS 2015, Bucharest, Romania, September 10-11, 2015.
VECoS
Belgacem Ben Hedia, Florin Popentiu Vladicescu
2015 C conf
State Space Reduction Strategie for Model Checking Concurrent C Programs.
VECoS
Amira Methni, Matthieu Lemerre, Belgacem Ben Hedia, Serge Haddad, Kamel Barkaoui
2014 Misc ed.
22nd International Conference on Real-Time Networks and Systems, RTNS '14, Versaille, France, October 8-10, 2014
RTNS
Mathieu Jan, Belgacem Ben Hedia, Joël Goossens, Claire Maiza
2014 — conf
Specifying and Verifying Concurrent C Programs with TLA+.
FTSCS
Amira Methni, Matthieu Lemerre, Belgacem Ben Hedia, Serge Haddad, Kamel Barkaoui