Bei Yu

567 papers A* 94A 87B 8C 4Misc 1Journal 289Unranked 83
YearRankTypeTitle / Venue / Authors
2026 J jnl
Attention-Based EDA Tool Parameter Explorer: From Hybrid Parameters to Multi-QoR Metrics.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Donger Luo, Qi Sun, Peng Xu, Su Zheng, Qi Xu, Tinghuan Chen, Bei Yu, Hao Geng
2026 — conf
BEAM: Bidirectional MEEF-Driven Mask Optimization for Curvilinear Photonic Design.
ASP-DAC
Xiaoxiao Liang, Yang Luo, Bei Yu, Yuzhe Ma
2026 — conf
CHASE: A CHiplet Architecture Simulation and Exploration Framework with Decoupled Multi-Fidelity Optimization.
ISPD
Shixin Chen, Hengyuan Zhang, Jianwang Zhai, Bei Yu
2026 — conf
CausalTuner: Will Causality Help High-Dimensional EDA Tool Parameter Tuning.
ASP-DAC
Ziyang Yu, Peng Xu, Su Zheng, Siyuan Xu, Hao Geng, Bei Yu, Martin D. F. Wong
2026 — conf
CombRewriter: Enabling Combinational Logic Simplification in MLIR-Based Hardware Compiler.
ASP-DAC
Haisheng Zheng, Zhuolun He, Shuo Yin, Yuzhe Ma, Bei Yu
2026 — conf
DCLOG: Don't Cares-based Logic Optimization using Pre-training Graph Neural Networks.
ASP-DAC
Rongliang Fu, Libo Shen, Ziyi Wang, Zhengxing Lei, Zixiao Wang, JunYing Huang, Bei Yu, Tsung-Yi Ho
2026 — conf
DPO-3D: Differentiable Power Delivery Network Optimization via Flexible Modeling for Routability and IR-Drop Tradeoff in Face-to-Face 3D ICs.
ASP-DAC
Zhen Zhuang, Zheng Yang, Yuxuan Zhao, Jiawei Hu, Bei Yu, Sung Kyu Lim, Tsung-Yi Ho
2026 J jnl
DeepVerifier: Learning to Update Test Sequences for Coverage-Guided Verification.
ACM Trans. Design Autom. Electr. Syst.
Yuntao Lu, Chen Bai, Yuxuan Zhao, Ziyue Zheng, Yangdi Lyu, Mingyu Liu, Bei Yu
2026 — conf
DiLA: Enhancing LLM Tool Learning with Differential Logic Layer.
KDD (1)
Yu Zhang, Hui-Ling Zhen, Zehua Pei, Yingzhao Lian, Lihao Yin, Mingxuan Yuan, Bei Yu
2026 J jnl
G-kway: Multilevel GPU-Accelerated k-way Graph Partitioner using Task Graph Parallelism.
ACM Trans. Design Autom. Electr. Syst.
Wan-Luan Lee, Dian-Lun Lin, Shui Jiang, Cheng-Hsiang Chiu, Yibo Lin, Bei Yu, Tsung-Yi Ho, Tsung-Wei Huang
2026 J jnl
GoSteiner: Constructing Rectilinear Steiner Minimum Tree on Directed Graph.
ACM Trans. Design Autom. Electr. Syst.
Rong Sun, Qi Xu, Song Chen, Yi Kang, Bei Yu
2026 J jnl
HiePlace: Efficient Hierarchical PCB Placement.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Shanyi Li, Zhen Zhuang, Mingyu Liu, Weihua Sheng, Bei Yu, Tsung-Yi Ho
2026 J jnl
HyDAS: Hybrid Domain Deformed Attention for Selective Hotspot Detection.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yuyang Chen, Qi Sun, Su Zheng, Xinyun Zhang, Bei Yu, Hao Geng
2026 — conf
Invited: Infusing EDA Knowledge into LLM Systems: An Information-Source Perspective.
ISPD
Yuhan Qin, Yuan Pu, Tairu Qiu, Zhuolun He, Bei Yu
2026 A* conf
KCLNet: Electrically Equivalence-Oriented Graph Representation Learning for Analog Circuits.
AAAI
Peng Xu, Yapeng Li, Tinghuan Chen, Tsung-Yi Ho, Bei Yu
2026 J jnl
KCLNet: Electrically Equivalence-Oriented Graph Representation Learning for Analog Circuits.
CoRR
Peng Xu, Yapeng Li, Tinghuan Chen, Tsung-Yi Ho, Bei Yu
2026 — conf
LLM-Assisted Circuit Verification: A Comprehensive Survey.
ASP-DAC
Hongduo Liu, Yuntao Lu, Mingjun Wang, Xufeng Yao, Bei Yu
2026 J jnl
Low-Light Video Enhancement with An Effective Spatial-Temporal Decomposition Paradigm.
CoRR
Xiaogang Xu, Kun Zhou, Tao Hu, Jiafei Wu, Ruixing Wang, Hao Peng, Bei Yu
2026 J jnl
MemDLM: Memory-Enhanced DLM Training.
CoRR
Zehua Pei, Hui-Ling Zhen, Weizhe Lin, Sinno Jialin Pan, Yunhe Wang, Mingxuan Yuan, Bei Yu
2026 J jnl
Multilayer Package Power/Ground Planes Synthesis With Balanced DC IR Drops: A Game-Theoretic Optimization Approach.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Siyuan Liang, Zhen Zhuang, Kai-Yuan Chao, Bei Yu, Tsung-Yi Ho
2026 J jnl
Oiso: Outlier-Isolated Data Format for Low-Bit Large Language Model Quantization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Lancheng Zou, Shuo Yin, Mingjun Li, Mingzi Wang, Chen Bai, Wenqian Zhao, Bei Yu
2026 J jnl
PPD: A Portable and Highly Parallel Dispatching System for Deep Learning.
ACM Trans. Design Autom. Electr. Syst.
Wendong Xu, Yuhao Ji, Yang Bai, Yueting Li, Yuxuan Zhao, Zhengwu Liu, Bei Yu, Ngai Wong
2026 — conf
Partitioning-free 3D-IC Floorplanning.
ASP-DAC
Shuo Ren, Zhen Zhuang, Rongliang Fu, Leilei Jin, Libo Shen, Bei Yu, Tsung-Yi Ho
2026 J jnl
Real-Time Compensation Framework for Large-Scale ReRAM-Based Sparse LU Factorization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Weiran Chen, Zaitian Chen, Bei Yu, Song Chen, Yi Kang, Qi Xu
2026 J jnl
RegPlace: Regularity-Aware Placement for Full-System DNN Accelerator Designs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jiaxi Jiang, Yuan Pu, Mingjun Li, Yuxuan Zhao, Peiyu Liao, Zuodong Zhang, Yibo Lin, Bei Yu
2026 J jnl
Routing-aware Legal Hybrid Bonding Terminal Assignment for 3D Face-to-Face Stacked ICs.
ACM Trans. Design Autom. Electr. Syst.
Siting Liu, Jieya Zhou, Jiaxi Jiang, Zhuolun He, Ziyi Wang, Yibo Lin, Bei Yu, Martin D. F. Wong
2026 J jnl
Selecting Nets to Rip Up and Reroute via SAT.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hongduo Liu, Siting Liu, Zhongdong Qi, Tsung-Yi Ho, Bei Yu
2025 A* conf
3D-Flow: Flow-based Standard Cell Legalization for 3D ICs.
DAC
Yuxuan Zhao, Peiyu Liao, Bei Yu
2025 J jnl
A Learned Performance Model With Transfer Learning Across GPUs on Tensorized Instructions.
IEEE Trans. Parallel Distributed Syst.
Yang Bai, Mingjun Li, Wendong Xu, Bei Yu
2025 A* conf
A Systematic Approach for Multi-objective Double-side Clock Tree Synthesis.
DAC
Xun Jiang, Haoran Lu, Yuxuan Zhao, Jiarui Wang, Zizheng Guo, Heng Wu, Bei Yu, Sung Kyu Lim, Runsheng Wang, Ru Huang, Yibo Lin
2025 J jnl
A Systematic Approach for Multi-objective Double-side Clock Tree Synthesis.
CoRR
Xun Jiang, Haoran Lu, Yuxuan Zhao, Jiarui Wang, Zizheng Guo, Heng Wu, Bei Yu, Sung Kyu Lim, Runsheng Wang, Ru Huang, Yibo Lin
2025 J jnl
Adaptive ILT via Multi-Level Lithography Simulation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Shuyuan Sun, Fan Yang, Bei Yu, Li Shang, Xuan Zeng
2025 J jnl
AnalogCoder-Pro: Unifying Analog Circuit Generation and Optimization via Multi-modal LLMs.
CoRR
Yao Lai, Souradip Poddar, Sungyoung Lee, Guojin Chen, Mengkang Hu, Bei Yu, Ping Luo, David Z. Pan
2025 J jnl
Analytical Heterogeneous Die-to-Die 3-D Placement With Macros.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yuxuan Zhao, Peiyu Liao, Siting Liu, Jiaxi Jiang, Yibo Lin, Bei Yu
2025 J jnl
AnchorTP: Resilient LLM Inference with State-Preserving Elastic Tensor Parallelism.
CoRR
Wendong Xu, Chujie Chen, He Xiao, Kuan Li, Jing Xiong, Chen Zhang, Wenyong Zhou, Chaofan Tao, Yang Bai, Bei Yu, Ngai Wong
2025 J jnl
Architect of the Bits World: Masked Autoregressive Modeling for Circuit Generation Guided by Truth Table.
CoRR
Haoyuan Wu, Haisheng Zheng, Shoubo Hu, Zhuolun He, Bei Yu
2025 J jnl
BAQE: Backend-Adaptive DNN Deployment via Synchronous Bayesian Quantization and Hardware Configuration Exploration.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Wenqian Zhao, Shuo Yin, Chen Bai, Zixiao Wang, Bei Yu
2025 J jnl
Behavioral Fingerprinting of Large Language Models.
CoRR
Zehua Pei, Hui-Ling Zhen, Yingchun Zhang, Zhiyuan Yang, Xing Li, Xianzhi Yu, Mingxuan Yuan, Bei Yu
2025 J jnl
Boosting Fidelity for Pre-Trained-Diffusion-Based Low-Light Image Enhancement via Condition Refinement.
CoRR
Xiaogang Xu, Jian Wang, Yunfan Lu, Ruihang Chu, Ruixing Wang, Jiafei Wu, Bei Yu, Liang Lin
2025 J jnl
Bounded Dynamic Level Maintenance for Efficient Logic Optimization.
CoRR
Junfeng Liu, Qinghua Zhao, Liwei Ni, Jingren Wang, Biwei Xie, Xingquan Li, Bei Yu, Shuai Ma
2025 J jnl
Bridging Hotspot Detection and Mask Optimization via Domain-Crossing Masked Layout Modeling.
ACM Trans. Design Autom. Electr. Syst.
Binwu Zhu, Su Zheng, Yuzhe Ma, Bei Yu, Martin D. F. Wong
2025 A* conf
Bridging Layout and RTL: Knowledge Distillation based Timing Prediction.
ICML
Mingjun Wang, Yihan Wen, Bin Sun, Jianan Mu, Juan Li, Xiaoyi Wang, Jing Justin Ye, Bei Yu, Huawei Li
2025 J jnl
Buffer and Splitter Insertion for Adiabatic Quantum-Flux-Parametron Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Rongliang Fu, Mengmeng Wang, Yirong Kan, Olivia Chen, Nobuyuki Yoshikawa, Bei Yu, Tsung-Yi Ho
2025 J jnl
CMoE: Fast Carving of Mixture-of-Experts for Efficient LLM Inference.
CoRR
Zehua Pei, Lancheng Zou, Hui-Ling Zhen, Xianzhi Yu, Wulong Liu, Sinno Jialin Pan, Mingxuan Yuan, Bei Yu
2025 A conf
ChronoTE: Crosstalk-Aware Timing Estimation for Routing Optimization via Edge-Enhanced GNNs.
ICCAD
Leilei Jin, Rongliang Fu, Zhen Zhuang, Liang Xiao, Fangzhou Liu, Bei Yu, Tsung-Yi Ho
2025 A* conf
Circuit Representation Learning with Masked Gate Modeling and Verilog-AIG Alignment.
ICLR
Haoyuan Wu, Haisheng Zheng, Yuan Pu, Bei Yu
2025 J jnl
Circuit Representation Learning with Masked Gate Modeling and Verilog-AIG Alignment.
CoRR
Haoyuan Wu, Haisheng Zheng, Yuan Pu, Bei Yu
2025 A* conf
Curvilinear Optical Proximity Correction via Cardinal Spline.
DAC
Su Zheng, Xiaoxiao Liang, Ziyang Yu, Yuzhe Ma, Bei Yu, Martin D. F. Wong
2025 J jnl
Customized Retrieval Augmented Generation and Benchmarking for EDA Tool Documentation QA.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yuan Pu, Zhuolun He, Yuqi Jiang, Tairu Qiu, Haoyuan Wu, Qi Sun, Cheng Zhuo, Bei Yu
2025 A* conf
DSPlacer: DSP Placement for FPGA-based CNN Accelerator.
DAC
Baohui Xie, Xinrui Zhu, Zhiyuan Lu, Yuan Pu, Tongkai Wu, Xiaofeng Zou, Bei Yu, Tinghuan Chen
2025 J jnl
Deep-Learning-Based Pre-Layout Parasitic Capacitance Prediction on SRAM Designs.
CoRR
Shan Shen, Dingcheng Yang, Yuyang Xie, Chunyan Pei, Wenjian Yu, Bei Yu
2025 J jnl
Delay-Driven Rectilinear Steiner Tree Construction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hongxi Wu, Xingquan Li, Liang Chen, Bei Yu, Wenxing Zhu
2025 A conf
DiffCCD: Differentiable Concurrent Clock and Data Optimization.
ICCAD
Yuhao Ji, Yuntao Lu, Zuodong Zhang, Zizheng Guo, Yibo Lin, Bei Yu
2025 J jnl
DiffPattern-Flex: Efficient Layout Pattern Generation via Discrete Diffusion.
CoRR
Zixiao Wang, Wenqian Zhao, Yunheng Shen, Yang Bai, Guojin Chen, Farzan Farnia, Bei Yu
2025 J jnl
DiffPattern-Flex: Efficient Layout Pattern Generation via Discrete Diffusion.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Zixiao Wang, Wenqian Zhao, Yunheng Shen, Yang Bai, Guojin Chen, Farzan Farnia, Bei Yu
2025 — conf
Divergent Thoughts toward One Goal: LLM-based Multi-Agent Collaboration System for Electronic Design Automation.
NAACL (Long Papers)
Haoyuan Wu, Haisheng Zheng, Zhuolun He, Bei Yu
2025 J jnl
Divergent Thoughts toward One Goal: LLM-based Multi-Agent Collaboration System for Electronic Design Automation.
CoRR
Haoyuan Wu, Haisheng Zheng, Zhuolun He, Bei Yu
2025 J jnl
Does Your Vision-Language Model Get Lost in the Long Video Sampling Dilemma?
CoRR
Tianyuan Qu, Longxiang Tang, Bohao Peng, Senqiao Yang, Bei Yu, Jiaya Jia
2025 J jnl
DreamOmni2: Multimodal Instruction-based Editing and Generation.
CoRR
Bin Xia, Bohao Peng, Yuechen Zhang, Junjia Huang, Jiyang Liu, Jingyao Li, Haoru Tan, Sitong Wu, Chengyao Wang, Yitong Wang, Xinglong Wu, Bei Yu, Jiaya Jia
2025 J jnl
DreamOmni3: Scribble-based Editing and Generation.
CoRR
Bin Xia, Bohao Peng, Jiyang Liu, Sitong Wu, Jingyao Li, Junjia Huang, Xu Zhao, Yitong Wang, Ruihang Chu, Bei Yu, Jiaya Jia
2025 A* conf
DreamOmni: Unified Image Generation and Editing.
CVPR
Bin Xia, Yuechen Zhang, Jingyao Li, Chengyao Wang, Yitong Wang, Xinglong Wu, Bei Yu, Jiaya Jia
2025 J jnl
DreamVE: Unified Instruction-based Image and Video Editing.
CoRR
Bin Xia, Jiyang Liu, Yuechen Zhang, Bohao Peng, Ruihang Chu, Yitong Wang, Xinglong Wu, Bei Yu, Jiaya Jia
2025 J jnl
EDA-Copilot: A RAG-Powered Intelligent Assistant for EDA Tools.
ACM Trans. Design Autom. Electr. Syst.
Zhe Xiao, Xu He, Haoying Wu, Bei Yu, Yang Guo
2025 J jnl
EasyMRC: Efficient Mask Rule Checking via Representative Edge Sampling.
ACM Trans. Design Autom. Electr. Syst.
Jiahao Xu, Zhuolun He, Shuo Yin, Yuan Pu, Wenjian Yu, Bei Yu
2025 J jnl
Effective LLM Knowledge Learning via Model Generalization.
CoRR
Mingkang Zhu, Xi Chen, Zhongdao Wang, Bei Yu, Hengshuang Zhao, Jiaya Jia
2025 J jnl
Efficient Design Space Exploration for the BOOM Using SAC-Based Reinforcement Learning.
IEEE Trans. Very Large Scale Integr. Syst.
Mingjun Cheng, Shihan Zhang, Xin Zheng, Xian Lin, Huaien Gao, Shuting Cai, Xiaoming Xiong, Bei Yu
2025 — conf
Efficient OpAmp Adaptation for Zoom Attention to Golden Contexts.
ACL (1)
Haoyuan Wu, Rui Ming, Haisheng Zheng, Zhuolun He, Bei Yu
2025 J jnl
Efficient OpAmp Adaptation for Zoom Attention to Golden Contexts.
CoRR
Haoyuan Wu, Rui Ming, Haisheng Zheng, Zhuolun He, Bei Yu
2025 — conf
Enhancing LLM Knowledge Learning through Generalization.
EMNLP (Findings)
Mingkang Zhu, Xi Chen, Zhongdao Wang, Bei Yu, Hengshuang Zhao, Jiaya Jia
2025 J jnl
Evolution of Optimization Algorithms for Global Placement via Large Language Models.
CoRR
Xufeng Yao, Jiaxi Jiang, Yuxuan Zhao, Peiyu Liao, Yibo Lin, Bei Yu
2025 J jnl
FGNN2: A Powerful Pretraining Framework for Learning the Logic Functionality of Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Ziyi Wang, Chen Bai, Zhuolun He, Guangliang Zhang, Qiang Xu, Tsung-Yi Ho, Yu Huang, Bei Yu
2025 — conf
FTAFP: A Feedthrough-Aware Floorplanner for Hierarchical Design of Large-Scale SoCs.
ASP-DAC
Zirui Li, Kanglin Tian, Jianwang Zhai, Zixuan Li, Shixiong Kai, Siyuan Xu, Bei Yu, Kang Zhao
2025 A* conf
FlexPose: Pose Distribution Adaptation with Limited Guidance.
AAAI
Zixiao Wang, Junwu Weng, Mengyuan Liu, Bei Yu
2025 A* conf
From Flatland to Forest: Exploring Pareto-optimal Design through RTL Hierarchy Trees.
DAC
Donger Luo, Qi Sun, Xingheng Li, Cheng Zhuo, Bei Yu, Hao Geng
2025 J jnl
From Noisy Traces to Stable Gradients: Bias-Variance Optimized Preference Optimization for Aligning Large Reasoning Models.
CoRR
Mingkang Zhu, Xi Chen, Bei Yu, Hengshuang Zhao, Jiaya Jia
2025 A conf
G-Contour: GPU Accelerated Contour Tracing For Large-Scale Layouts.
ICCAD
Shuo Yin, Jiahao Xu, Jiaxi Jiang, Mingjun Li, Yuzhe Ma, Tsung-Yi Ho, Bei Yu
2025 A conf
GPU Acceleration for Versatile Buffer Insertion.
ICCAD
Yuan Pu, Yuhao Ji, Siying Yu, Zuodong Zhang, Zizheng Guo, Zhuolun He, Yibo Lin, David Z. Pan, Bei Yu
2025 J jnl
Generalized Kullback-Leibler Divergence Loss.
CoRR
Jiequan Cui, Beier Zhu, Qingshan Xu, Zhuotao Tian, Xiaojuan Qi, Bei Yu, Hanwang Zhang, Richang Hong
2025 J jnl
Generative Distribution Distillation.
CoRR
Jiequan Cui, Beier Zhu, Qingshan Xu, Xiaogang Xu, Pengguang Chen, Xiaojuan Qi, Bei Yu, Hanwang Zhang, Richang Hong
2025 A* conf
Generative Video Propagation.
CVPR
Shaoteng Liu, Tianyu Wang, Jui-Hsien Wang, Qing Liu, Zhifei Zhang, Joon-Young Lee, Yijun Li, Bei Yu, Zhe Lin, Soo Ye Kim, Jiaya Jia
2025 — conf
GraphCAD: Leveraging Graph Neural Networks for Accuracy Prediction Handling Crosstalk-affected Delays.
ISPD
Fangzhou Liu, Guannan Guo, Yuyang Ye, Ziyi Wang, Wenjie Fu, Weihua Sheng, Bei Yu
2025 A conf
H3D: Heterogeneous Resources Aware Global Router for Face-to-Face Bonded 3D ICs.
ICCAD
Yuxuan Zhao, Feng Gu, Siting Liu, Peiyu Liao, Bei Yu
2025 J jnl
HAPE: Hardware-Aware LLM Pruning For Efficient On-Device Inference Optimization.
ACM Trans. Design Autom. Electr. Syst.
Wenqian Zhao, Lancheng Zou, Zixiao Wang, Xufeng Yao, Bei Yu
2025 J jnl
HDLdebugger: Streamlining HDL debugging with Large Language Models.
ACM Trans. Design Autom. Electr. Syst.
Xufeng Yao, Haoyang Li, Tsz Ho Chan, Wenyi Xiao, Mingxuan Yuan, Yu Huang, Lei Chen, Bei Yu
2025 — conf
HeLO: A Heterogeneous Logic Optimization Framework by Hierarchical Clustering and Graph Learning.
ISPD
Yuan Pu, Fangzhou Liu, Zhuolun He, Keren Zhu, Rongliang Fu, Ziyi Wang, Tsung-Yi Ho, Bei Yu
2025 J jnl
Hierarchical Partitioning-Based Interchip Redistribution Layer Routing for Fan-Out Wafer-Level Packaging.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Haoyang Xu, Xing Huang, Zhen Zhuang, Zhiwen Yu, Bin Guo, Kai-Yuan Chao, Bei Yu, Tsung-Yi Ho, Martin D. F. Wong
2025 J jnl
High-level Synthesis Directives Design Optimization via Large Language Model.
ACM Trans. Design Autom. Electr. Syst.
Xufeng Yao, Wenqian Zhao, Qi Sun, Cheng Zhuo, Bei Yu
2025 A conf
IR-Fusion: A Fusion Framework for Static IR Drop Analysis Combining Numerical Solution and Machine Learning.
DATE
Feng Guo, Jianwang Zhai, Jingyu Jia, Jiawei Liu, Kang Zhao, Bei Yu, Chuan Shi
2025 J jnl
IncreMacro: Incremental Macro Placement Refinement.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yuan Pu, Tinghuan Chen, Zhuolun He, Jiajun Qin, Chen Bai, Haisheng Zheng, Yibo Lin, Bei Yu
2025 A* conf
Intelligent OPC Engineer Assistant for Semiconductor Manufacturing.
AAAI
Guojin Chen, Haoyu Yang, Bei Yu, Haoxing Ren
2025 — conf
Invited: Physical Design for Advanced 3D ICs: Challenges and Solutions.
ISPD
Yuxuan Zhao, Lancheng Zou, Bei Yu
2025 J jnl
Klotski v2: Improved DNN Model Orchestration Framework for Dataflow Architecture Accelerators.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chen Bai, Xuechao Wei, Youwei Zhuo, Yi Cai, Hongzhong Zheng, Bei Yu, Yuan Xie
2025 A conf
LLM-Augmented Multi-Modal Fusion for SoC Design Space Exploration.
ICCAD
Donger Luo, Tianyi Li, Xinheng Li, Qi Sun, Cheng Zhuo, Bei Yu, Jingyi Yu, Hao Geng
2025 A conf
LLM-SRAF: Sub-Resolution Assist Feature Generation Using Large Language Model.
DATE
Tianyi Li, Zhexin Tang, Tao Wu, Bei Yu, Jingyi Yu, Hao Geng
2025 A* conf
LLMShare: Optimizing LLM Inference Serving with Hardware Architecture Exploration.
DAC
Hongduo Liu, Chen Bai, Peng Xu, Lihao Yin, Xianzhi Yu, Hui-Ling Zhen, Mingxuan Yuan, Tsung-Yi Ho, Bei Yu
2025 A conf
LMLitho: A Large Vision Model-Driven Lithography Simulation Framework.
ICCAD
Zhen Wang, Hongquan He, Tao Wu, Xuming He, Qi Sun, Cheng Zhuo, Bei Yu, Jingyi Yu, Hao Geng
2025 J jnl
Large Language Models for EDA: From Assistants to Agents.
Found. Trends Electron. Des. Autom.
Zhuolun He, Yuan Pu, Haoyuan Wu, Yuhan Qin, Tairu Qiu, Bei Yu
2025 J jnl
Large Language Models for EDA: Future or Mirage?
ACM Trans. Design Autom. Electr. Syst.
Zhuolun He, Yuan Pu, Haoyuan Wu, Tairu Qiu, Bei Yu
2025 J jnl
Lay-Net: Grafting Netlist Knowledge on Layout-Based Congestion Prediction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Lancheng Zou, Su Zheng, Peng Xu, Siting Liu, Bei Yu, Martin D. F. Wong
2025 J jnl
Layout Decomposition via Boolean Satisfiability.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hongduo Liu, Peiyu Liao, Mengchuan Zou, Bowen Pang, Xijun Li, Mingxuan Yuan, Tsung-Yi Ho, Bei Yu
2025 J jnl
Learning-Driven Physically Aware Large-Scale Circuit Gate Sizing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yuyang Ye, Peng Xu, Lizheng Ren, Tinghuan Chen, Hao Yan, Bei Yu, Longxing Shi
2025 A* conf
Low-Light Video Enhancement via Spatial-Temporal Consistent Decomposition.
IJCAI
Xiaogang Xu, Kun Zhou, Tao Hu, Jiafei Wu, Ruixing Wang, Hao Peng, Bei Yu
2025 J jnl
MGM-Omni: Scaling Omni LLMs to Personalized Long-Horizon Speech.
CoRR
Chengyao Wang, Zhisheng Zhong, Bohao Peng, Senqiao Yang, Yuqi Liu, Haokun Gui, Bin Xia, Jingyao Li, Bei Yu, Jiaya Jia
2025 — conf
ML-Based Fine-Grained Modeling of DC Current Crowding in Power Delivery TSVs for Face-to-Face 3D ICs.
ISPD
Zheng Yang, Zhen Zhuang, Bei Yu, Tsung-Yi Ho, Martin D. F. Wong, Sung Kyu Lim
2025 A conf
MM-GRADE: A Multi-Modal EDA Tool Documentation QA Framework Leveraging Retrieval Augmented Generation.
ICCAD
Yuan Pu, Zhuolun He, Shutong Lin, Jiajun Qin, Xinyun Zhang, Hairuo Han, Haisheng Zheng, Yuqi Jiang, Cheng Zhuo, Qi Sun, David Z. Pan, Bei Yu
2025 A conf
MMPack: Multi-Mask Co-Design for Ultra-Large Wafer-Scale Package Integration.
ICCAD
Shanyi Li, Zhen Zhuang, Siyuan Liang, Bei Yu, Tsung-Yi Ho
2025 J jnl
MOSS: Efficient and Accurate FP8 LLM Training with Microscaling and Automatic Scaling.
CoRR
Yu Zhang, Hui-Ling Zhen, Mingxuan Yuan, Bei Yu
2025 A* conf
MOSS: Multi-Modal Representation Learning on Sequential Circuits.
DAC
Mingjun Wang, Bin Sun, Jianan Mu, Feng Gu, Boyu Han, Tianmeng Yang, Xinyu Zhang, Silin Liu, Yihan Wen, Hui Wang, Jun Gao, Zhiteng Chao, Husheng Han, Zizhen Liu, Shengwen Liang, Jing Ye, Bei Yu, Xiaowei Li, Huawei Li
2025 J jnl
Modular Customization of Diffusion Models via Blockwise-Parameterized Low-Rank Adaptation.
CoRR
Mingkang Zhu, Xi Chen, Zhongdao Wang, Bei Yu, Hengshuang Zhao, Jiaya Jia
2025 A conf
NUA-Timer: Pre-Synthesis Timing Prediction Under Non-Uniform Input Arrival Times.
ICCAD
Ziyi Wang, Fangzhou Liu, Tsung-Yi Ho, David Z. Pan, Bei Yu
2025 — conf
On the Distributed Evaluation of Generative Models.
ICCVW
Zixiao Wang, Farzan Farnia, Zhenghao Lin, Yunheng Shen, Bei Yu
2025 J jnl
On-Policy Optimization with Group Equivalent Preference for Multi-Programming Language Understanding.
CoRR
Haoyuan Wu, Rui Ming, Jilong Gao, Hangyu Zhao, Xueyi Chen, Yikai Yang, Haisheng Zheng, Zhuolun He, Bei Yu
2025 J jnl
One-Token Rollout: Guiding Supervised Fine-Tuning of LLMs with Policy Gradient.
CoRR
Rui Ming, Haoyuan Wu, Shoubo Hu, Zhuolun He, Bei Yu
2025 J jnl
PARoute2: Enhanced Analog Routing via Performance-Drive Guidance Generation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Peng Xu, Jindong Tu, Guojin Chen, Keren Zhu, Tinghuan Chen, Tsung-Yi Ho, Bei Yu
2025 — conf
PCBAgent: An Agent-based Framework for High-Density Printed Circuit Board Placement.
ASP-DAC
Lin Chen, Ran Chen, Shoubo Hu, Xufeng Yao, Zhentao Tang, Shixiong Kai, Siyuan Xu, Mingxuan Yuan, Jianye Hao, Bei Yu, Jiang Xu
2025 J jnl
PRO-TIME: Prerouting Optimization-Aware Timing Prediction via Multimodal Learning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Ziyi Wang, Siting Liu, Yuan Pu, Song Chen, Tsung-Yi Ho, Bei Yu
2025 J jnl
ParSGCN: Bridging the Gap Between Emulation Partitioning and Scheduling.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Ziyi Wang, Wenqian Zhao, Yuan Pu, Lei Chen, Wilson W. K. Thong, Weihua Sheng, Tsung-Yi Ho, Bei Yu
2025 J jnl
PermLLM: Learnable Channel Permutation for N:M Sparse Large Language Models.
CoRR
Lancheng Zou, Shuo Yin, Zehua Pei, Tsung-Yi Ho, Farzan Farnia, Bei Yu
2025 J jnl
PreMoe: Lightening MoEs on Constrained Memory by Expert Pruning and Retrieval.
CoRR
Zehua Pei, Yingchun Zhang, Hui-Ling Zhen, Xianzhi Yu, Wulong Liu, Sinno Jialin Pan, Mingxuan Yuan, Bei Yu
2025 J jnl
Prerouting Timing Prediction Across Different Technology Nodes.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Xinyun Zhang, Binwu Zhu, Fangzhou Liu, Jiaxi Jiang, Ziyi Wang, Peng Xu, Hong Xu, Bei Yu
2025 A conf
RSizing: Robust Bayesian Optimization for Analog Circuit Sizing Under Process Variations.
ICCAD
Jindong Tu, Yapeng Li, Peng Xu, Tuo Li, Guoqing Li, Zushuai Xie, Bei Yu, Tinghuan Chen
2025 J jnl
RTime-QA: A Benchmark for Atomic Temporal Event Understanding in Large Multi-modal Models.
CoRR
Yuqi Liu, Qin Jin, Tianyuan Qu, Xuan Liu, Yang Du, Bei Yu, Jiaya Jia
2025 J jnl
Rank-DSE: Neural Pareto Comparator of Microarchitecture Design Space Exploration.
ACM Trans. Design Autom. Electr. Syst.
Peng Xu, Su Zheng, Mingzi Wang, Ziyang Yu, Shixin Chen, Tinghuan Chen, Keren Zhu, Tsung-Yi Ho, Bei Yu
2025 A* conf
Rank-based Multi-objective Approximate Logic Synthesis via Monte Carlo Tree Search.
DAC
Yuyang Ye, Xiangfei Hu, Yuchen Liu, Peng Xu, Yu Gong, Tinghuan Chen, Hao Yan, Bei Yu, Longxing Shi
2025 J jnl
RePlan: Reasoning-guided Region Planning for Complex Instruction-based Image Editing.
CoRR
Tianyuan Qu, Lei Ke, Xiaohang Zhan, Longxiang Tang, Yuqi Liu, Bohao Peng, Bei Yu, Dong Yu, Jiaya Jia
2025 J jnl
RuleLearner: OPC Rule Extraction From Inverse Lithography Technique Engine.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Ziyang Yu, Su Zheng, Wenqian Zhao, Shuo Yin, Xiaoxiao Liang, Guojin Chen, Yuzhe Ma, Bei Yu, Martin D. F. Wong
2025 J jnl
SCOPE: Prompt Evolution for Enhancing Agent Effectiveness.
CoRR
Zehua Pei, Hui-Ling Zhen, Shixiong Kai, Sinno Jialin Pan, Yunhe Wang, Mingxuan Yuan, Bei Yu
2025 A* conf
SDM-PEB: Spatial-Depthwise Mamba for Enhanced Post-Exposure Bake Simulation.
DAC
Ziyang Yu, Peng Xu, Zixiao Wang, Binwu Zhu, Qipan Wang, Yibo Lin, Runsheng Wang, Bei Yu, Martin D. F. Wong
2025 J jnl
SMART: Graph Learning-Boosted Subcircuit Matching for Large-Scale Analog Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jindong Tu, Yapeng Li, Pengjia Li, Peng Xu, Qianru Zhang, Sanping Wan, Yongsheng Sun, Bei Yu, Tinghuan Chen
2025 J jnl
Seg-Zero: Reasoning-Chain Guided Segmentation via Cognitive Reinforcement.
CoRR
Yuqi Liu, Bohao Peng, Zhisheng Zhong, Zihao Yue, Fanbin Lu, Bei Yu, Jiaya Jia
2025 J jnl
Sign-Off Timing Considerations via Concurrent Routing Topology Optimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Siting Liu, Ziyi Wang, Fangzhou Liu, Yibo Lin, Bei Yu, Martin D. F. Wong
2025 J jnl
Stratified GRPO: Handling Structural Heterogeneity in Reinforcement Learning of LLM Search Agents.
CoRR
Mingkang Zhu, Xi Chen, Bei Yu, Hengshuang Zhao, Jiaya Jia
2025 J jnl
Streamlining Computational Lithography With Efficient Pattern Database.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Su Zheng, Wenqian Zhao, Shuyuan Sun, Fan Yang, Bei Yu, Martin D. F. Wong
2025 J jnl
SwingArena: Competitive Programming Arena for Long-context GitHub Issue Solving.
CoRR
Wendong Xu, Jing Xiong, Chenyang Zhao, Qiujiang Chen, Haoran Wang, Hui Shen, Zhongwei Wan, Jianbo Dai, Taiqiang Wu, He Xiao, Chaofan Tao, Z. Morley Mao, Ying Sheng, Zhijiang Guo, Hongxia Yang, Bei Yu, Lingpeng Kong, Quanquan Gu, Ngai Wong
2025 A* conf
TGDPO: Harnessing Token-Level Reward Guidance for Enhancing Direct Preference Optimization.
ICML
Mingkang Zhu, Xi Chen, Zhongdao Wang, Bei Yu, Hengshuang Zhao, Jiaya Jia
2025 J jnl
TGDPO: Harnessing Token-Level Reward Guidance for Enhancing Direct Preference Optimization.
CoRR
Mingkang Zhu, Xi Chen, Zhongdao Wang, Bei Yu, Hengshuang Zhao, Jiaya Jia
2025 J jnl
TeMACLE: A Technology Mapping-Aware Area-Efficient Standard Cell Library Extension Framework.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Rongliang Fu, Chao Wang, Bei Yu, Tsung-Yi Ho
2025 — conf
The Survey of 2.5D Integrated Architecture: An EDA perspective.
ASP-DAC
Shixin Chen, Hengyuan Zhang, Zichao Ling, Jianwang Zhai, Bei Yu
2025 — conf
ThePlace: Thermal-Aware Placement With Operator Learning-Based Ultra-Fast Simulator.
ASP-DAC
Xinfei Liu, Siting Liu, Bei Yu, Song Chen, Qi Xu
2025 J jnl
Think with Self-Decoupling and Self-Verification: Automated RTL Design with Backtrack-ToT.
CoRR
Zhiteng Chao, Yonghao Wang, Xinyu Zhang, Jiaxin Zhou, Tenghui Hua, Husheng Han, Tianmeng Yang, Jianan Mu, Bei Yu, Rui Zhang, Jing Ye, Huawei Li
2025 A conf
Timing-Driven Approximate Logic Synthesis Based on Double-Chase Grey Wolf Optimizer.
DATE
Xiangfei Hu, Yuyang Ye, Tinghuan Chen, Hao Yan, Bei Yu
2025 J jnl
ToTRL: Unlock LLM Tree-of-Thoughts Reasoning Potential through Puzzles Solving.
CoRR
Haoyuan Wu, Xueyi Chen, Rui Ming, Jilong Gao, Shoubo Hu, Zhuolun He, Bei Yu
2025 J jnl
TorchResist: Open-Source Differentiable Resist Simulator.
CoRR
Zixiao Wang, Jieya Zhou, Su Zheng, Shuo Yin, Kaichao Liang, Shoubo Hu, Xiao Chen, Bei Yu
2025 A conf
Ultrafast Density Gradient Accumulation in 3D Analytical Placement with Divergence Theorem.
ICCAD
Peiyu Liao, Yuxuan Zhao, Siting Liu, Bei Yu
2025 J jnl
UniMoCo: Unified Modality Completion for Robust Multi-Modal Embeddings.
CoRR
Jiajun Qin, Yuan Pu, Zhuolun He, Seunggeun Kim, David Z. Pan, Bei Yu
2025 A conf
VIRTUAL: Vector-based Dynamic Power Estimation via Decoupled Multi-Modality Learning.
ICCAD
Yuntao Lu, Mingjun Wang, Yihan Wen, Boyu Han, Jianan Mu, Huawei Li, Bei Yu
2025 J jnl
ViSurf: Visual Supervised-and-Reinforcement Fine-Tuning for Large Vision-and-Language Models.
CoRR
Yuqi Liu, Liangyu Chen, Jiazhen Liu, Mingkang Zhu, Zhisheng Zhong, Bei Yu, Jiaya Jia
2025 J jnl
VisionReasoner: Unified Visual Perception and Reasoning via Reinforcement Learning.
CoRR
Yuqi Liu, Tianyuan Qu, Zhisheng Zhong, Bohao Peng, Shu Liu, Bei Yu, Jiaya Jia
2025 J jnl
VisionThink: Smart and Efficient Vision Language Model via Reinforcement Learning.
CoRR
Senqiao Yang, Junyi Li, Xin Lai, Bei Yu, Hengshuang Zhao, Jiaya Jia
2025 A* conf
VisionZip: Longer is Better but Not Necessary in Vision Language Models.
CVPR
Senqiao Yang, Yukang Chen, Zhuotao Tian, Chengyao Wang, Jingyao Li, Bei Yu, Jiaya Jia
2025 A conf
WideGate: Beyond Directed Acyclic Graph Learning in Subcircuit Boundary Prediction.
DATE
Jiawei Liu, Zhiyan Liu, Xun He, Jianwang Zhai, Zhengyuan Shi, Qiang Xu, Bei Yu, Chuan Shi
2025 J jnl
iCTS: Iterative and Hierarchical Clock Tree Synthesis With Skew-Latency-Load Tree.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Weiguo Li, Zhipeng Huang, Bei Yu, Wenxing Zhu, Jian Chen, Zhixue He, Xingquan Li
2025 A conf
iRw: An Intelligent Rewriting.
DATE
Haisheng Zheng, Haoyuan Wu, Zhuolun He, Yuzhe Ma, Bei Yu
2024 J jnl
A High-Performance Accelerator for Real-Time Super-Resolution on Edge FPGAs.
ACM Trans. Design Autom. Electr. Syst.
Hongduo Liu, Yijian Qian, Youqiang Liang, Bin Zhang, Zhaohan Liu, Tao He, Wenqian Zhao, Jiangbo Lu, Bei Yu
2024 J jnl
AdaOPC 2.0: Enhanced Adaptive Mask Optimization Framework for via Layers.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Wenqian Zhao, Xufeng Yao, Shuo Yin, Yang Bai, Ziyang Yu, Yuzhe Ma, Bei Yu, Martin D. F. Wong
2024 A conf
An Agile Framework for Efficient LLM Accelerator Development and Model Inference.
ICCAD
Lvcheng Chen, Ying Wu, Chenyi Wen, Shizhang Wang, Li Zhang, Bei Yu, Qi Sun, Cheng Zhuo
2024 J jnl
Analytical Die-to-Die 3-D Placement With Bistratal Wirelength Model and GPU Acceleration.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Peiyu Liao, Yuxuan Zhao, Dawei Guo, Yibo Lin, Bei Yu
2024 J jnl
Analytical Heterogeneous Die-to-Die 3D Placement with Macros.
CoRR
Yuxuan Zhao, Peiyu Liao, Siting Liu, Jiaxi Jiang, Yibo Lin, Bei Yu
2024 J jnl
BOOM-Explorer: RISC-V BOOM Microarchitecture Design Space Exploration.
ACM Trans. Design Autom. Electr. Syst.
Chen Bai, Qi Sun, Jianwang Zhai, Yuzhe Ma, Bei Yu, Martin D. F. Wong
2024 A* conf
BetterV: Controlled Verilog Generation with Discriminative Guidance.
ICML
Zehua Pei, Hui-Ling Zhen, Mingxuan Yuan, Yu Huang, Bei Yu
2024 J jnl
BetterV: Controlled Verilog Generation with Discriminative Guidance.
CoRR
Zehua Pei, Hui-Ling Zhen, Mingxuan Yuan, Yu Huang, Bei Yu
2024 A* conf
BiE: Bi-Exponent Block Floating-Point for Large Language Models Quantization.
ICML
Lancheng Zou, Wenqian Zhao, Shuo Yin, Chen Bai, Qi Sun, Bei Yu
2024 A* conf
CAMO: Correlation-Aware Mask Optimization with Modulated Reinforcement Learning.
DAC
Xiaoxiao Liang, Haoyu Yang, Kang Liu, Bei Yu, Yuzhe Ma
2024 J jnl
CAMO: Correlation-Aware Mask Optimization with Modulated Reinforcement Learning.
CoRR
Xiaoxiao Liang, Haoyu Yang, Kang Liu, Bei Yu, Yuzhe Ma
2024 A conf
CBTune: Contextual Bandit Tuning for Logic Synthesis.
DATE
Fangzhou Liu, Zehua Pei, Ziyang Yu, Haisheng Zheng, Zhuolun He, Tinghuan Chen, Bei Yu
2024 J jnl
ChatEDA: A Large Language Model Powered Autonomous Agent for EDA.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Haoyuan Wu, Zhuolun He, Xinyun Zhang, Xufeng Yao, Su Zheng, Haisheng Zheng, Bei Yu
2024 A* conf
ChatPattern: Layout Pattern Customization via Natural Language.
DAC
Zixiao Wang, Yunheng Shen, Xufeng Yao, Wenqian Zhao, Yang Bai, Farzan Farnia, Bei Yu
2024 J jnl
ChatPattern: Layout Pattern Customization via Natural Language.
CoRR
Zixiao Wang, Yunheng Shen, Xufeng Yao, Wenqian Zhao, Yang Bai, Farzan Farnia, Bei Yu
2024 A* conf
Classes Are Not Equal: An Empirical Study on Image Recognition Fairness.
CVPR
Jiequan Cui, Beier Zhu, Xin Wen, Xiaojuan Qi, Bei Yu, Hanwang Zhang
2024 J jnl
Classes Are Not Equal: An Empirical Study on Image Recognition Fairness.
CoRR
Jiequan Cui, Beier Zhu, Xin Wen, Xiaojuan Qi, Bei Yu, Hanwang Zhang
2024 A conf
Customized Retrieval Augmented Generation and Benchmarking for EDA Tool Documentation QA.
ICCAD
Yuan Pu, Zhuolun He, Tairu Qiu, Haoyuan Wu, Bei Yu
2024 J jnl
Customized Retrieval Augmented Generation and Benchmarking for EDA Tool Documentation QA.
CoRR
Yuan Pu, Zhuolun He, Tairu Qiu, Haoyuan Wu, Bei Yu
2024 A* conf
Decoupled Kullback-Leibler Divergence Loss.
NeurIPS
Jiequan Cui, Zhuotao Tian, Zhisheng Zhong, Xiaojuan Qi, Bei Yu, Hanwang Zhang
2024 — conf
Deep-Learning-Based Pre-Layout Parasitic Capacitance Prediction on SRAM Designs.
ACM Great Lakes Symposium on VLSI
Shan Shen, Dingcheng Yang, Yuyang Xie, Chunyan Pei, Bei Yu, Wenjian Yu
2024 J jnl
DeepOTF: Learning Equations-constrained Prediction for Electromagnetic Behavior.
ACM Trans. Design Autom. Electr. Syst.
Peng Xu, Siyuan Xu, Tinghuan Chen, Guojin Chen, Tsung-Yi Ho, Bei Yu
2024 A conf
DiffSAT: Differential MaxSAT Layer for SAT Solving.
ICCAD
Yu Zhang, Hui-Ling Zhen, Mingxuan Yuan, Bei Yu
2024 A conf
Differentiable Edge-based OPC.
ICCAD
Guojin Chen, Haoyu Yang, Haoxing Mark Ren, Bei Yu, David Z. Pan
2024 J jnl
Differentiable Edge-based OPC.
CoRR
Guojin Chen, Haoyu Yang, Haoxing Ren, Bei Yu, David Z. Pan
2024 A* conf
Disentangle, Align and Generalize: Learning A Timing Predictor from Different Technology Nodes.
DAC
Xinyun Zhang, Binwu Zhu, Fangzhou Liu, Ziyi Wang, Peng Xu, Hong Xu, Bei Yu
2024 J jnl
DreamOmni: Unified Image Generation and Editing.
CoRR
Bin Xia, Yuechen Zhang, Jingyao Li, Chengyao Wang, Yitong Wang, Xinglong Wu, Bei Yu, Jiaya Jia
2024 A* conf
EMOGen: Enhancing Mask Optimization via Pattern Generation.
DAC
Su Zheng, Yuzhe Ma, Bei Yu, Martin D. F. Wong
2024 A* conf
Efficient Bilevel Source Mask Optimization.
DAC
Guojin Chen, Hongquan He, Peng Xu, Hao Geng, Bei Yu
2024 A* conf
Efficient ILT via Multigrid-Schwartz Method.
DAC
Shuyuan Sun, Fan Yang, Bei Yu, Li Shang, Dian Zhou, Xuan Zeng
2024 J jnl
Erratum to: Large circuit models: opportunities and challenges.
Sci. China Inf. Sci.
Lei Chen, Yiqi Chen, Zhufei Chu, Wenji Fang, Tsung-Yi Ho, Ru Huang, Yu Huang, Sadaf Khan, Min Li, Xingquan Li, Yu Li, Yun Liang, Jinwei Liu, Yi Liu, Yibo Lin, Guojie Luo, Hongyang Pan, Zhengyuan Shi, Guangyu Sun, Dimitrios Tsaras, Runsheng Wang, Ziyi Wang, Xinming Wei, Zhiyao Xie, Qiang Xu, Chenhao Xue, Junchi Yan, Jun Yang, Bei Yu, Mingxuan Yuan, Evangeline F. Y. Young, Xuan Zeng, Haoyi Zhang, Zuodong Zhang, Yuxiang Zhao, Hui-Ling Zhen, Ziyang Zheng, Binwu Zhu, Keren Zhu, Sunan Zou
2024 J jnl
Fast and Accurate Aging-Aware Cell Timing Model via Graph Learning.
IEEE Trans. Circuits Syst. II Express Briefs
Yuyang Ye, Tinghuan Chen, Zicheng Wang, Hao Yan, Bei Yu, Longxing Shi
2024 Misc conf
Fed2Com: Towards Efficient Compression in Federated Learning.
ICNC
Yu Zhang, Wei Lin, Sisi Chen, Qingyu Song, Jiaxun Lu, Yunfeng Shao, Bei Yu, Hong Xu
2024 J jnl
Floorplanning with Edge-aware Graph Attention Network and Hindsight Experience Replay.
ACM Trans. Design Autom. Electr. Syst.
Bo Yang, Qi Xu, Hao Geng, Song Chen, Bei Yu, Yi Kang
2024 J jnl
Floorplet: Performance-Aware Floorplan Framework for Chiplet Integration.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Shixin Chen, Shanyi Li, Zhen Zhuang, Su Zheng, Zheng Liang, Tsung-Yi Ho, Bei Yu, Alberto L. Sangiovanni-Vincentelli
2024 A* conf
Fracturing-aware Curvilinear ILT via Circular E-beam Mask Writer.
DAC
Xinyun Zhang, Su Zheng, Guojin Chen, Binwu Zhu, Hong Xu, Bei Yu
2024 — conf
FuILT: Full Chip ILT System With Boundary Healing.
ISPD
Shuo Yin, Wenqian Zhao, Li Xie, Hong Chen, Yuzhe Ma, Tsung-Yi Ho, Bei Yu
2024 J jnl
FuseGPT: Learnable Layers Fusion of Generative Pre-trained Transformers.
CoRR
Zehua Pei, Hui-Ling Zhen, Xianzhi Yu, Sinno Jialin Pan, Mingxuan Yuan, Bei Yu
2024 A* conf
G-kway: Multilevel GPU-Accelerated k-way Graph Partitioner.
DAC
Wan-Luan Lee, Dian-Lun Lin, Tsung-Wei Huang, Shui Jiang, Tsung-Yi Ho, Yibo Lin, Bei Yu
2024 A* conf
GNNavigator: Towards Adaptive Training of Graph Neural Networks via Automatic Guideline Exploration.
DAC
Tong Qiao, Jianlei Yang, Yingjie Qi, Ao Zhou, Chen Bai, Bei Yu, Weisheng Zhao, Chunming Hu
2024 J jnl
GNNavigator: Towards Adaptive Training of Graph Neural Networks via Automatic Guideline Exploration.
CoRR
Tong Qiao, Jianlei Yang, Yingjie Qi, Ao Zhou, Chen Bai, Bei Yu, Weisheng Zhao, Chunming Hu
2024 J jnl
GTCO: Graph and Tensor Co-Design for Transformer-Based Image Recognition on Tensor Cores.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yang Bai, Xufeng Yao, Qi Sun, Wenqian Zhao, Shixin Chen, Zixiao Wang, Bei Yu
2024 J jnl
Generalized Parametric Contrastive Learning.
IEEE Trans. Pattern Anal. Mach. Intell.
Jiequan Cui, Zhisheng Zhong, Zhuotao Tian, Shu Liu, Bei Yu, Jiaya Jia
2024 J jnl
Generative Video Propagation.
CoRR
Shaoteng Liu, Tianyu Wang, Jui-Hsien Wang, Qing Liu, Zhifei Zhang, Joon-Young Lee, Yijun Li, Bei Yu, Zhe Lin, Soo Ye Kim, Jiaya Jia
2024 J jnl
HDLdebugger: Streamlining HDL debugging with Large Language Models.
CoRR
Xufeng Yao, Haoyang Li, Tsz Ho Chan, Wenyi Xiao, Mingxuan Yuan, Yu Huang, Lei Chen, Bei Yu
2024 A* conf
Improving Neural ODE Training with Temporal Adaptive Batch Normalization.
NeurIPS
Su Zheng, Zhengqi Gao, Fan-Keng Sun, Duane S. Boning, Bei Yu, Martin D. F. Wong
2024 — conf
IncreMacro: Incremental Macro Placement Refinement.
ISPD
Yuan Pu, Tinghuan Chen, Zhuolun He, Chen Bai, Haisheng Zheng, Yibo Lin, Bei Yu
2024 J jnl
Intelligent OPC Engineer Assistant for Semiconductor Manufacturing.
CoRR
Guojin Chen, Haoyu Yang, Bei Yu, Haoxing Ren
2024 A conf
Is Vanilla Bayesian Optimization Enough for High-Dimensional Architecture Design Optimization?
ICCAD
Yuanhang Gao, Donger Luo, Chen Bai, Bei Yu, Hao Geng, Qi Sun, Cheng Zhuo
2024 A* conf
Knowing The Spec to Explore The Design via Transformed Bayesian Optimization.
DAC
Donger Luo, Qi Sun, Xinheng Li, Chen Bai, Bei Yu, Hao Geng
2024 J jnl
L2O-ILT: Learning to Optimize Inverse Lithography Techniques.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Binwu Zhu, Su Zheng, Ziyang Yu, Guojin Chen, Yuzhe Ma, Fan Yang, Bei Yu, Martin D. F. Wong
2024 J jnl
LLM-Enhanced Bayesian Optimization for Efficient Analog Layout Constraint Generation.
CoRR
Guojin Chen, Keren Zhu, Seunggeun Kim, Hanqing Zhu, Yao Lai, Bei Yu, David Z. Pan
2024 B conf
LSTP: A Logic Synthesis Timing Predictor.
ASPDAC
Haisheng Zheng, Zhuolun He, Fangzhou Liu, Zehua Pei, Bei Yu
2024 — conf
Large Language Models for EDA: Future or Mirage?
ISPD
Zhuolun He, Bei Yu
2024 J jnl
Large circuit models: opportunities and challenges.
Sci. China Inf. Sci.
Lei Chen, Yiqi Chen, Zhufei Chu, Wenji Fang, Tsung-Yi Ho, Ru Huang, Yu Huang, Sadaf Khan, Min Li, Xingquan Li, Yu Li, Yun Liang, Jinwei Liu, Yi Liu, Yibo Lin, Guojie Luo, Hongyang Pan, Zhengyuan Shi, Guangyu Sun, Dimitrios Tsaras, Runsheng Wang, Ziyi Wang, Xinming Wei, Zhiyao Xie, Qiang Xu, Chenhao Xue, Junchi Yan, Jun Yang, Bei Yu, Mingxuan Yuan, Evangeline F. Y. Young, Xuan Zeng, Haoyi Zhang, Zuodong Zhang, Yuxiang Zhao, Hui-Ling Zhen, Ziyang Zheng, Binwu Zhu, Keren Zhu, Sunan Zou
2024 J jnl
Learning-driven Physically-aware Large-scale Circuit Gate Sizing.
CoRR
Yuyang Ye, Peng Xu, Lizheng Ren, Tinghuan Chen, Hao Yan, Bei Yu, Longxing Shi
2024 A* conf
Lesyn: Placement-aware Logic Resynthesis for Non-Integer Multiple-Cell-Height Designs.
DAC
Yuan Pu, Fangzhou Liu, Yu Zhang, Zhuolun He, Yibo Lin, Kai-Yuan Chao, Bei Yu
2024 J jnl
MixPE: Quantization and Hardware Co-design for Efficient LLM Inference.
CoRR
Yu Zhang, Mingzi Wang, Lancheng Zou, Wulong Liu, Hui-Ling Zhen, Mingxuan Yuan, Bei Yu
2024 J jnl
MoreauPruner: Robust Pruning of Large Language Models against Weight Perturbations.
CoRR
Zixiao Wang, Jingwei Zhang, Wenqian Zhao, Farzan Farnia, Bei Yu
2024 — conf
Multi-Electrostatics Based Placement for Non-Integer Multiple-Height Cells.
ISPD
Yu Zhang, Yuan Pu, Fangzhou Liu, Peiyu Liao, Kai-Yuan Chao, Keren Zhu, Yibo Lin, Bei Yu
2024 A* conf
NeuroSelect: Learning to Select Clauses in SAT Solvers.
DAC
Hongduo Liu, Peng Xu, Yuan Pu, Lihao Yin, Hui-Ling Zhen, Mingxuan Yuan, Tsung-Yi Ho, Bei Yu
2024 J jnl
Open-Source Differentiable Lithography Imaging Framework.
CoRR
Guojin Chen, Hao Geng, Bei Yu, David Z. Pan
2024 A* conf
PDRC: Package Design Rule Checking via GPU-Accelerated Geometric Intersection Algorithms for Non-Manhattan Geometry.
DAC
Jiaxi Jiang, Lancheng Zou, Wenqian Zhao, Zhuolun He, Tinghuan Chen, Bei Yu
2024 J jnl
PFENet++: Boosting Few-Shot Semantic Segmentation With the Noise-Filtered Context-Aware Prior Mask.
IEEE Trans. Pattern Anal. Mach. Intell.
Xiaoliu Luo, Zhuotao Tian, Taiping Zhang, Bei Yu, Yuan Yan Tang, Jiaya Jia
2024 A conf
Parallel Gröbner Basis Rewriting and Memory Optimization for Efficient Multiplier Verification.
DATE
Hongduo Liu, Peiyu Liao, Junhua Huang, Hui-Ling Zhen, Mingxuan Yuan, Tsung-Yi Ho, Bei Yu
2024 A* conf
Parameter-Efficient Sparsity Crafting from Dense to Mixture-of-Experts for Instruction Tuning on General Tasks.
EMNLP
Haoyuan Wu, Haisheng Zheng, Zhuolun He, Bei Yu
2024 J jnl
Parameter-Efficient Sparsity Crafting from Dense to Mixture-of-Experts for Instruction Tuning on General Tasks.
CoRR
Haoyuan Wu, Haisheng Zheng, Bei Yu
2024 A conf
Peak Power and Dynamic IR-drop Assessment via Waveform Augmenting.
ICCAD
Yihan Wen, Juan Li, Bei Yu, Xiaoyi Wang
2024 B conf
Performance-Driven Analog Layout Automation: Current Status and Future Directions (Invited Paper).
ASPDAC
Peng Xu, Jintao Li, Tsung-Yi Ho, Bei Yu, Keren Zhu
2024 A* conf
Performance-driven Analog Routing via Heterogeneous 3DGNN and Potential Relaxation.
DAC
Peng Xu, Guojin Chen, Keren Zhu, Tinghuan Chen, Tsung-Yi Ho, Bei Yu
2024 A conf
PolarGate: Breaking the Functionality Representation Bottleneck of And-Inverter Graph Neural Network.
ICCAD
Jiawei Liu, Jianwang Zhai, Mingyu Zhao, Zhe Lin, Bei Yu, Chuan Shi
2024 A* conf
Progressively Knowledge Distillation via Re-parameterizing Diffusion Reverse Process.
AAAI
Xufeng Yao, Fanbin Lu, Yuechen Zhang, Xinyun Zhang, Wenqian Zhao, Bei Yu
2024 J jnl
Quantization via Distillation and Contrastive Learning.
IEEE Trans. Neural Networks Learn. Syst.
Zehua Pei, Xufeng Yao, Wenqian Zhao, Bei Yu
2024 A conf
RISCSparse: Point Cloud Inference Engine on RISC-V Processor.
ICCAD
Shangran Lin, Xinrui Zhu, Baohui Xie, Tinghuan Chen, Cheng Zhuo, Qi Sun, Bei Yu
2024 J jnl
RL-OPC: Mask Optimization With Deep Reinforcement Learning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Xiaoxiao Liang, Yikang Ouyang, Haoyu Yang, Bei Yu, Yuzhe Ma
2024 A conf
RTLRewriter: Methodologies for Large Models aided RTL Code Optimization.
ICCAD
Xufeng Yao, Yiwen Wang, Xing Li, Yingzhao Lian, Ran Chen, Lei Chen, Mingxuan Yuan, Hong Xu, Bei Yu
2024 J jnl
RTLRewriter: Methodologies for Large Models aided RTL Code Optimization.
CoRR
Xufeng Yao, Yiwen Wang, Xing Li, Yingzhao Lian, Ran Chen, Lei Chen, Mingxuan Yuan, Hong Xu, Bei Yu
2024 A conf
RankTuner: When Design Tool Parameter Tuning Meets Preference Bayesian Optimization.
ICCAD
Peng Xu, Su Zheng, Yuyang Ye, Chen Bai, Siyuan Xu, Hao Geng, Tsung-Yi Ho, Bei Yu
2024 — conf
Routing-aware Legal Hybrid Bonding Terminal Assignment for 3D Face-to-Face Stacked ICs.
ISPD
Siting Liu, Jiaxi Jiang, Zhuolun He, Ziyi Wang, Yibo Lin, Bei Yu, Martin D. F. Wong
2024 J jnl
Small is Beautiful: Compressing Deep Neural Networks for Partial Domain Adaptation.
IEEE Trans. Neural Networks Learn. Syst.
Yuzhe Ma, Xufeng Yao, Ran Chen, Ruiyu Li, Xiaoyong Shen, Bei Yu
2024 B conf
SoC-Tuner: An Importance-guided Exploration Framework for DNN-targeting SoC Design.
ASPDAC
Shixin Chen, Su Zheng, Chen Bai, Wenqian Zhao, Shuo Yin, Yang Bai, Bei Yu
2024 J jnl
SoLA: Solver-Layer Adaption of LLM for Better Logic Reasoning.
CoRR
Yu Zhang, Hui-Ling Zhen, Zehua Pei, Yingzhao Lian, Lihao Yin, Mingxuan Yuan, Bei Yu
2024 J jnl
The Dawn of AI-Native EDA: Promises and Challenges of Large Circuit Models.
CoRR
Lei Chen, Yiqi Chen, Zhufei Chu, Wenji Fang, Tsung-Yi Ho, Yu Huang, Sadaf Khan, Min Li, Xingquan Li, Yun Liang, Yibo Lin, Jinwei Liu, Yi Liu, Guojie Luo, Zhengyuan Shi, Guangyu Sun, Dimitrios Tsaras, Runsheng Wang, Ziyi Wang, Xinming Wei, Zhiyao Xie, Qiang Xu, Chenhao Xue, Evangeline F. Y. Young, Bei Yu, Mingxuan Yuan, Haoyi Zhang, Zuodong Zhang, Yuxiang Zhao, Hui-Ling Zhen, Ziyang Zheng, Binwu Zhu, Keren Zhu, Sunan Zou
2024 J jnl
The Survey of Chiplet-based Integrated Architecture: An EDA perspective.
CoRR
Shixin Chen, Hengyuan Zhang, Zichao Ling, Jianwang Zhai, Bei Yu
2024 J jnl
Timing-Driven Technology Mapping Approximation Based on Reinforcement Learning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yuyang Ye, Tinghuan Chen, Yifei Gao, Hao Yan, Bei Yu, Longxing Shi
2024 J jnl
Timing-driven Approximate Logic Synthesis Based on Double-chase Grey Wolf Optimizer.
CoRR
Xiangfei Hu, Yuyang Ye, Tinghuan Chen, Hao Yan, Bei Yu
2024 A* conf
Toward Controllable Hierarchical Clock Tree Synthesis with Skew-Latency-Load Tree.
DAC
Weiguo Li, Zhipeng Huang, Bei Yu, Wenxing Zhu, Xingquan Li
2024 A* conf
Towards Automated RISC-V Microarchitecture Design with Reinforcement Learning.
AAAI
Chen Bai, Jianwang Zhai, Yuzhe Ma, Bei Yu, Martin D. F. Wong
2024 J jnl
Ultrafast Source Mask Optimization via Conditional Discrete Diffusion.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Guojin Chen, Zixiao Wang, Bei Yu, David Z. Pan, Martin D. F. Wong
2024 A* conf
Unleashing the Potential of AQFP Logic Placement via Entanglement Entropy and Projection.
DAC
Yinuo Bai, Enxin Yi, Wei W. Xing, Bei Yu, Zhou Jin
2024 B conf
V-GR: 3D Global Routing with Via Minimization and Multi-Strategy Rip-up and Rerouting.
ASPDAC
Ping Zhang, Pengju Yao, Xingquan Li, Bei Yu, Wenxing Zhu
2024 J jnl
VisionZip: Longer is Better but Not Necessary in Vision Language Models.
CoRR
Senqiao Yang, Yukang Chen, Zhuotao Tian, Chengyao Wang, Jingyao Li, Bei Yu, Jiaya Jia
2024 J jnl
Wages: The Worst Transistor Aging Analysis for Large-scale Analog Integrated Circuits via Domain Generalization.
ACM Trans. Design Autom. Electr. Syst.
Tinghuan Chen, Hao Geng, Qi Sun, Sanping Wan, Yongsheng Sun, Huatao Yu, Bei Yu
2024 A* conf
WinoGen: A Highly Configurable Winograd Convolution IP Generator for Efficient CNN Acceleration on FPGA.
DAC
Mingjun Li, Pengjia Li, Shuo Yin, Shixin Chen, Beichen Li, Chong Tong, Jianlei Yang, Tinghuan Chen, Bei Yu
2024 B conf
iEDA: An Open-source infrastructure of EDA.
ASPDAC
Xingquan Li, Zengrong Huang, Simin Tao, Zhipeng Huang, Chunan Zhuang, Hao Wang, Yifan Li, Yihang Qiu, Guojie Luo, Huawei Li, Haihua Shen, Mingyu Chen, Dongbo Bu, Wenxing Zhu, Ye Cai, Xiaoming Xiong, Ying Jiang, Yi Heng, Peng Zhang, Bei Yu, Biwei Xie, Yungang Bao
2024 B conf
iPD: An Open-source intelligent Physical Design Toolchain.
ASPDAC
Xingquan Li, Simin Tao, Shijian Chen, Zhisheng Zeng, Zhipeng Huang, Hongxi Wu, Weiguo Li, Zengrong Huang, Liwei Ni, Xueyan Zhao, He Liu, Shuaiying Long, Ruizhi Liu, Xiaoze Lin, Bo Yang, Fuxing Huang, Zonglin Yang, Yihang Qiu, Zheqing Shao, Jikang Liu, Yuyao Liang, Biwei Xie, Yungang Bao, Bei Yu
2024 A* conf
p-Laplacian Adaptation for Generative Pre-trained Vision-Language Models.
AAAI
Haoyuan Wu, Xinyun Zhang, Peng Xu, Peiyu Liao, Xufeng Yao, Bei Yu
2024 J jnl
pNeurFill: Enhanced Neural Network Model-Based Dummy Filling Synthesis With Perimeter Adjustment.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Zhaoting Chen, Junzhe Cai, Changhao Yan, Zhaori Bi, Yuzhe Ma, Bei Yu, Wenchuang Walter Hu, Dian Zhou, Xuan Zeng
2023 J jnl
A GPU-Enabled Level-Set Method for Mask Optimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Ziyang Yu, Guojin Chen, Yuzhe Ma, Bei Yu
2023 J jnl
A High-Performance Accelerator for Super-Resolution Processing on Embedded GPU.
CoRR
Wenqian Zhao, Qi Sun, Yang Bai, Wenbo Li, Haisheng Zheng, Bei Yu, Martin D. F. Wong
2023 J jnl
A High-Performance Accelerator for Super-Resolution Processing on Embedded GPU.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Wenqian Zhao, Yang Bai, Qi Sun, Wenbo Li, Haisheng Zheng, Nianjuan Jiang, Jiangbo Lu, Bei Yu, Martin D. F. Wong
2023 J jnl
A Unified Framework for Layout Pattern Analysis With Deep Causal Estimation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Ran Chen, Shoubo Hu, Zhitang Chen, Shengyu Zhu, Bei Yu, Pengyun Li, Cheng Chen, Yu Huang, Jianye Hao
2023 — conf
ALCOP: Automatic Load-Compute Pipelining in Deep Learning Compiler for AI-GPUs.
MLSys
Guyue Huang, Yang Bai, Liu Liu, Yuke Wang, Bei Yu, Yufei Ding, Yuan Xie
2023 A* conf
ATFormer: A Learned Performance Model with Transfer Learning Across Devices for Deep Learning Tensor Programs.
EMNLP
Yang Bai, Wenqian Zhao, Shuo Yin, Zixiao Wang, Bei Yu
2023 J jnl
AdaOPC: A Self-Adaptive Mask Optimization Framework For Real Design Patterns.
CoRR
Wenqian Zhao, Xufeng Yao, Ziyang Yu, Guojin Chen, Yuzhe Ma, Bei Yu, Martin D. F. Wong
2023 J jnl
Adaptive Perspective Distillation for Semantic Segmentation.
IEEE Trans. Pattern Anal. Mach. Intell.
Zhuotao Tian, Pengguang Chen, Xin Lai, Li Jiang, Shu Liu, Hengshuang Zhao, Bei Yu, Ming-Chang Yang, Jiaya Jia
2023 J jnl
Aging-Aware Critical Path Selection via Graph Attention Networks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yuyang Ye, Tinghuan Chen, Yifei Gao, Hao Yan, Bei Yu, Longxing Shi
2023 A conf
AlphaSyn: Logic Synthesis Optimization with Efficient Monte Carlo Tree Search.
ICCAD
Zehua Pei, Fangzhou Liu, Zhuolun He, Guojin Chen, Haisheng Zheng, Keren Zhu, Bei Yu
2023 J jnl
Analytical Die-to-Die 3D Placement with Bistratal Wirelength Model and GPU Acceleration.
CoRR
Peiyu Liao, Yuxuan Zhao, Dawei Guo, Yibo Lin, Bei Yu
2023 A* conf
ArchExplorer: Microarchitecture Exploration Via Bottleneck Analysis.
MICRO
Chen Bai, Jiayi Huang, Xuechao Wei, Yuzhe Ma, Sicheng Li, Hongzhong Zheng, Bei Yu, Yuan Xie
2023 A* conf
AutoGraph: Optimizing DNN Computation Graph for Parallel GPU Kernel Execution.
AAAI
Yuxuan Zhao, Qi Sun, Zhuolun He, Yang Bai, Bei Yu
2023 A conf
BOMIG: A Majority Logic Synthesis Framework for AQFP Logic.
DATE
Rongliang Fu, JunYing Huang, Mengmeng Wang, Nobuyuki Yoshikawa, Bei Yu, Tsung-Yi Ho, Olivia Chen
2023 J jnl
Boosting VLSI Design Flow Parameter Tuning with Random Embedding and Multi-objective Trust-region Bayesian Optimization.
ACM Trans. Design Autom. Electr. Syst.
Su Zheng, Hao Geng, Chen Bai, Bei Yu, Martin D. F. Wong
2023 J jnl
CTM-SRAF: Continuous Transmission Mask-Based Constraint-Aware Subresolution Assist Feature Generation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Ziyang Yu, Peiyu Liao, Yuzhe Ma, Bei Yu, Martin D. F. Wong
2023 — conf
ChatEDA: A Large Language Model Powered Autonomous Agent for EDA.
MLCAD
Zhuolun He, Haoyuan Wu, Xinyun Zhang, Xufeng Yao, Su Zheng, Haisheng Zheng, Bei Yu
2023 J jnl
ChatEDA: A Large Language Model Powered Autonomous Agent for EDA.
CoRR
Zhuolun He, Haoyuan Wu, Xinyun Zhang, Xufeng Yao, Su Zheng, Haisheng Zheng, Bei Yu
2023 A* conf
Concurrent Sign-off Timing Optimization via Deep Steiner Points Refinement.
DAC
Siting Liu, Ziyi Wang, Fangzhou Liu, Yibo Lin, Bei Yu, Martin D. F. Wong
2023 J jnl
Conditional Temporal Variational AutoEncoder for Action Video Prediction.
Int. J. Comput. Vis.
Xiaogang Xu, Yi Wang, Liwei Wang, Bei Yu, Jiaya Jia
2023 A conf
DLPlace: A Delay-Line Clocking-Based Placement Framework for AQFP Circuits.
ICCAD
Rongliang Fu, Olivia Chen, Bei Yu, Nobuyuki Yoshikawa, Tsung-Yi Ho
2023 J jnl
DRC-SG 2.0: Efficient Design Rule Checking Script Generation via Key Information Extraction.
ACM Trans. Design Autom. Electr. Syst.
Binwu Zhu, Xinyun Zhang, Yibo Lin, Bei Yu, Martin D. F. Wong
2023 J jnl
DREAMPlace 4.0: Timing-Driven Placement With Momentum-Based Net Weighting and Lagrangian-Based Refinement.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Peiyu Liao, Dawei Guo, Zizheng Guo, Siting Liu, Yibo Lin, Bei Yu
2023 J jnl
DSGN++: Exploiting Visual-Spatial Relation for Stereo-Based 3D Detectors.
IEEE Trans. Pattern Anal. Mach. Intell.
Yilun Chen, Shijia Huang, Shu Liu, Bei Yu, Jiaya Jia
2023 J jnl
Decoupled Kullback-Leibler Divergence Loss.
CoRR
Jiequan Cui, Zhuotao Tian, Zhisheng Zhong, Xiaojuan Qi, Bei Yu, Hanwang Zhang
2023 J jnl
DevelSet: Deep Neural Level Set for Instant Mask Optimization.
CoRR
Guojin Chen, Ziyang Yu, Hongduo Liu, Yuzhe Ma, Bei Yu
2023 J jnl
DevelSet: Deep Neural Level Set for Instant Mask Optimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Guojin Chen, Ziyang Yu, Hongduo Liu, Yuzhe Ma, Bei Yu
2023 A* conf
DiffPattern: Layout Pattern Generation via Discrete Diffusion.
DAC
Zixiao Wang, Yunheng Shen, Wenqian Zhao, Yang Bai, Guojin Chen, Farzan Farnia, Bei Yu
2023 J jnl
DiffPattern: Layout Pattern Generation via Discrete Diffusion.
CoRR
Zixiao Wang, Yunheng Shen, Wenqian Zhao, Yang Bai, Guojin Chen, Farzan Farnia, Bei Yu
2023 A* conf
Do Not Train It: A Linear Neural Architecture Search of Graph Neural Networks.
ICML
Peng Xu, Lin Zhang, Xuanzhou Liu, Jiaqi Sun, Yue Zhao, Haiqin Yang, Bei Yu
2023 J jnl
Do Not Train It: A Linear Neural Architecture Search of Graph Neural Networks.
CoRR
Peng Xu, Lin Zhang, Xuanzhou Liu, Jiaqi Sun, Yue Zhao, Haiqing Yang, Bei Yu
2023 J jnl
Efficient Arithmetic Block Identification With Graph Learning and Network-Flow.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Ziyi Wang, Zhuolun He, Chen Bai, Haoyu Yang, Bei Yu
2023 A* conf
Efficient Deep Space Filling Curve.
ICCV
Wanli Chen, Xufeng Yao, Xinyun Zhang, Bei Yu
2023 A conf
Efficient Design Rule Checking with GPU Acceleration.
DATE
Wei Zhong, Zhenhua Feng, Zhuolun He, Weimin Wang, Yuzhe Ma, Bei Yu
2023 A* conf
Efficient ILT via Multi-level Lithography Simulation.
DAC
Shuyuan Sun, Fan Yang, Bei Yu, Li Shang, Xuan Zeng
2023 A conf
Fast and Accurate Wire Timing Estimation Based on Graph Learning.
DATE
Yuyang Ye, Tinghuan Chen, Yifei Gao, Hao Yan, Bei Yu, Longxing Shi
2023 J jnl
FastGR: Global Routing on CPU-GPU With Heterogeneous Task Graph Scheduler.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Siting Liu, Yuan Pu, Peiyu Liao, Hongzhong Wu, Rui Zhang, Zhitang Chen, Wenlong Lv, Yibo Lin, Bei Yu
2023 A* conf
FastGR: Global Routing on CPU-GPU with Heterogeneous Task Graph Scheduler (Extended Abstract).
IJCAI
Siting Liu, Yuan Pu, Peiyu Liao, Hongzhong Wu, Rui Zhang, Zhitang Chen, Wenlong Lv, Yibo Lin, Bei Yu
2023 J jnl
Floorplet: Performance-aware Floorplan Framework for Chiplet Integration.
CoRR
Shixin Chen, Shanyi Li, Zhen Zhuang, Su Zheng, Zheng Liang, Tsung-Yi Ho, Bei Yu, Alberto L. Sangiovanni-Vincentelli
2023 J jnl
GPU-accelerated Matrix Cover Algorithm for Multiple Patterning Layout Decomposition.
CoRR
Guojin Chen, Haoyu Yang, Bei Yu
2023 — conf
Graph-Learning-Driven Path-Based Timing Analysis Results Predictor from Graph-Based Timing Analysis.
ASP-DAC
Yuyang Ye, Tinghuan Chen, Yifei Gao, Hao Yan, Bei Yu, Longxing Shi
2023 J jnl
Guest Editors' Introduction: Special Issue on Machine Learning for CAD/EDA.
IEEE Des. Test
Ulf Schlichtmann, Bing Li, Bei Yu, Raviv Gal
2023 A conf
Handling Orientation and Aspect Ratio of Modules in Electrostatics-Based Large Scale Fixed-Outline Floorplanning.
ICCAD
Fuxing Huang, Duanxiang Liu, Xingquan Li, Bei Yu, Wenxing Zhu
2023 A conf
IT-DSE: Invariance Risk Minimized Transfer Microarchitecture Design Space Exploration.
ICCAD
Ziyang Yu, Chen Bai, Shoubo Hu, Ran Chen, Taohai He, Mingxuan Yuan, Bei Yu, Martin D. F. Wong
2023 A conf
Invited Paper: Heterogeneous Acceleration for Design Rule Checking.
ICCAD
Zhuolun He, Bei Yu
2023 A conf
Klotski: DNN Model Orchestration Framework for Dataflow Architecture Accelerators.
ICCAD
Chen Bai, Xuechao Wei, Youwei Zhuo, Yi Cai, Hongzhong Zheng, Bei Yu, Yuan Xie
2023 A* conf
LRSDP: Low-Rank SDP for Triple Patterning Lithography Layout Decomposition.
DAC
Yu Zhang, Yifan Chen, Zhonglin Xie, Hong Xu, Zaiwen Wen, Yibo Lin, Bei Yu
2023 A conf
Lay-Net: Grafting Netlist Knowledge on Layout-Based Congestion Prediction.
ICCAD
Su Zheng, Lancheng Zou, Peng Xu, Siting Liu, Bei Yu, Martin D. F. Wong
2023 A* conf
Layout Decomposition via Boolean Satisfiability.
DAC
Hongduo Liu, Peiyu Liao, Mengchuan Zou, Bowen Pang, Xijun Li, Mingxuan Yuan, Tsung-Yi Ho, Bei Yu
2023 A* conf
LithoBench: Benchmarking AI Computational Lithography for Semiconductor Manufacturing.
NeurIPS
Su Zheng, Haoyu Yang, Binwu Zhu, Bei Yu, Martin D. F. Wong
2023 J jnl
Machine Learning in Advanced IC Design: A Methodological Survey.
IEEE Des. Test
Tinghuan Chen, Grace Li Zhang, Bei Yu, Bing Li, Ulf Schlichtmann
2023 — conf
Machine Learning in EDA: When and How.
MLCAD
Bei Yu
2023 J jnl
McPAT-Calib: A RISC-V BOOM Microarchitecture Power Modeling Framework.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jianwang Zhai, Chen Bai, Binwu Zhu, Yici Cai, Qiang Zhou, Bei Yu
2023 — conf
Microarchitecture Power Modeling via Artificial Neural Network and Transfer Learning.
ASP-DAC
Jianwang Zhai, Yici Cai, Bei Yu
2023 A* conf
Mitigating Distribution Shift for Congestion Optimization in Global Placement.
DAC
Su Zheng, Lancheng Zou, Siting Liu, Yibo Lin, Bei Yu, Martin D. F. Wong
2023 — conf
Mixed-Type Wafer Failure Pattern Recognition.
ASP-DAC
Hao Geng, Qi Sun, Tinghuan Chen, Qi Xu, Tsung-Yi Ho, Bei Yu
2023 A conf
Multi-Product Optimization for 3D Heterogeneous Integration with D2W Bonding.
ICCAD
Zhen Zhuang, Kai-Yuan Chao, Bei Yu, Tsung-Yi Ho, Martin D. F. Wong
2023 A* conf
On a Moreau Envelope Wirelength Model for Analytical Global Placement.
DAC
Peiyu Liao, Hongduo Liu, Yibo Lin, Bei Yu, Martin D. F. Wong
2023 J jnl
On the Evaluation of Generative Models in Distributed Learning Tasks.
CoRR
Zixiao Wang, Farzan Farnia, Zhenghao Lin, Yunheng Shen, Bei Yu
2023 A* conf
OpenDRC: An Efficient Open-Source Design Rule Checking Engine with Hierarchical GPU Acceleration.
DAC
Zhuolun He, Yihang Zuo, Jiaxi Jiang, Haisheng Zheng, Yuzhe Ma, Bei Yu
2023 — conf
OpenILT: An Open Source Inverse Lithography Technique Framework (Invited Paper).
ASICON
Su Zheng, Bei Yu, Martin D. F. Wong
2023 J jnl
PTPT: Physical Design Tool Parameter Tuning via Multi-Objective Bayesian Optimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hao Geng, Tinghuan Chen, Yuzhe Ma, Binwu Zhu, Bei Yu
2023 A* conf
Physics-Informed Optical Kernel Regression Using Complex-valued Neural Fields.
DAC
Guojin Chen, Zehua Pei, Haoyu Yang, Yuzhe Ma, Bei Yu, Martin D. F. Wong
2023 J jnl
Physics-Informed Optical Kernel Regression Using Complex-valued Neural Fields.
CoRR
Guojin Chen, Zehua Pei, Haoyu Yang, Yuzhe Ma, Bei Yu, Martin D. F. Wong
2023 J jnl
Reliability-Driven Memristive Crossbar Design in Neuromorphic Computing Systems.
IEEE Trans Autom. Sci. Eng.
Qi Xu, Junpeng Wang, Bo Yuan, Qi Sun, Song Chen, Bei Yu, Yi Kang, Feng Wu
2023 A* conf
Restructure-Tolerant Timing Prediction via Multimodal Fusion.
DAC
Ziyi Wang, Siting Liu, Yuan Pu, Song Chen, Tsung-Yi Ho, Bei Yu
2023 B conf
SNICIT: Accelerating Sparse Neural Network Inference via Compression at Inference Time on GPU.
ICPP
Shui Jiang, Tsung-Wei Huang, Bei Yu, Tsung-Yi Ho
2023 J jnl
SoC-Tuner: An Importance-guided Exploration Framework for DNN-targeting SoC Design.
CoRR
Shixin Chen, Su Zheng, Chen Bai, Wenqian Zhao, Shuo Yin, Yang Bai, Bei Yu
2023 J jnl
TRouter: Thermal-Driven PCB Routing via Nonlocal Crisscross Attention Networks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Tinghuan Chen, Silu Xiong, Huan He, Bei Yu
2023 J jnl
TinyFormer: Efficient Transformer Design and Deployment on Tiny Devices.
CoRR
Jianlei Yang, Jiacheng Liao, Fanding Lei, Meichen Liu, Junyi Chen, Lingkun Long, Han Wan, Bei Yu, Weisheng Zhao
2023 J jnl
Towards Versatile and Efficient Visual Knowledge Injection into Pre-trained Language Models with Cross-Modal Adapters.
CoRR
Xinyun Zhang, Haochen Tan, Han Wu, Mingjie Zhan, Ding Liang, Bei Yu
2023 J jnl
p-Laplacian Adaptation for Generative Pre-trained Vision-Language Models.
CoRR
Haoyuan Wu, Xinyun Zhang, Peng Xu, Peiyu Liao, Xufeng Yao, Bei Yu
2022 A conf
AdaOPC: A Self-Adaptive Mask Optimization Framework for Real Design Patterns.
ICCAD
Wenqian Zhao, Xufeng Yao, Ziyang Yu, Guojin Chen, Yuzhe Ma, Bei Yu, Martin D. F. Wong
2022 J jnl
Adaptive Layout Decomposition With Graph Embedding Neural Networks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Wei Li, Yuzhe Ma, Yibo Lin, Bei Yu
2022 J jnl
An Efficient Sharing Grouped Convolution via Bayesian Learning.
IEEE Trans. Neural Networks Learn. Syst.
Tinghuan Chen, Bin Duan, Qi Sun, Meng Zhang, Guoqing Li, Hao Geng, Qianru Zhang, Bei Yu
2022 J jnl
Analog Circuit Yield Optimization via Freeze-Thaw Bayesian Optimization Technique.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Xiaodong Wang, Changhao Yan, Yuzhe Ma, Bei Yu, Fan Yang, Dian Zhou, Xuan Zeng
2022 A* conf
Context-Based Contrastive Learning for Scene Text Recognition.
AAAI
Xinyun Zhang, Binwu Zhu, Xufeng Yao, Qi Sun, Ruiyu Li, Bei Yu
2022 J jnl
Correlated Multi-objective Multi-fidelity Optimization for HLS Directives Design.
ACM Trans. Design Autom. Electr. Syst.
Qi Sun, Tinghuan Chen, Siting Liu, Jianli Chen, Hao Yu, Bei Yu
2022 J jnl
Counteracting Adversarial Attacks in Autonomous Driving.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Qi Sun, Xufeng Yao, Arjun Ashok Rao, Bei Yu, Shiyan Hu
2022 J jnl
DAMO: Deep Agile Mask Optimization for Full-Chip Scale.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Guojin Chen, Wanli Chen, Qi Sun, Yuzhe Ma, Haoyu Yang, Bei Yu
2022 A conf
DREAMPlace 4.0: Timing-driven Global Placement with Momentum-based Net Weighting.
DATE
Peiyu Liao, Siting Liu, Zhitang Chen, Wenlong Lv, Yibo Lin, Bei Yu
2022 J jnl
DSGN++: Exploiting Visual-Spatial Relation for Stereo-based 3D Detectors.
CoRR
Yilun Chen, Shijia Huang, Shu Liu, Bei Yu, Jiaya Jia
2022 J jnl
Deep H-GCN: Fast Analog IC Aging-Induced Degradation Estimation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Tinghuan Chen, Qi Sun, Canhui Zhan, Changze Liu, Huatao Yu, Bei Yu
2022 J jnl
Deep Learning-Driven Simultaneous Layout Decomposition and Mask Optimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Wei Zhong, Shuxiang Hu, Yuzhe Ma, Haoyu Yang, Xiuyuan Ma, Bei Yu
2022 — conf
Efficient Design Rule Checking Script Generation via Key Information Extraction.
MLCAD
Binwu Zhu, Xinyun Zhang, Yibo Lin, Bei Yu, Martin D. F. Wong
2022 A conf
Efficient Hotspot Detection via Graph Neural Network.
DATE
Shuyuan Sun, Yiyang Jiang, Fan Yang, Bei Yu, Xuan Zeng
2022 J jnl
Efficient Layout Hotspot Detection via Neural Architecture Search.
ACM Trans. Design Autom. Electr. Syst.
Yiyang Jiang, Fan Yang, Bei Yu, Dian Zhou, Xuan Zeng
2022 — conf
Efficient Point Cloud Analysis Using Hilbert Curve.
ECCV (2)
Wanli Chen, Xinge Zhu, Guojin Chen, Bei Yu
2022 J jnl
Enabling Data Movement and Computation Pipelining in Deep Learning Compiler.
CoRR
Guyue Huang, Yang Bai, Liu Liu, Yuke Wang, Bei Yu, Yufei Ding, Yuan Xie
2022 J jnl
Eventor: An Efficient Event-Based Monocular Multi-View Stereo Accelerator on FPGA Platform.
CoRR
Mingjun Li, Jianlei Yang, Yingjie Qi, Meng Dong, Yuhao Yang, Runze Liu, Weitao Pan, Bei Yu, Weisheng Zhao
2022 A* conf
Eventor: an efficient event-based monocular multi-view stereo accelerator on FPGA platform.
DAC
Mingjun Li, Jianlei Yang, Yingjie Qi, Meng Dong, Yuhao Yang, Runze Liu, Weitao Pan, Bei Yu, Weisheng Zhao
2022 A conf
FastGR: Global Routing on CPU-GPU with Heterogeneous Task Graph Scheduler.
DATE
Siting Liu, Peiyu Liao, Rui Zhang, Zhitang Chen, Wenlong Lv, Yibo Lin, Bei Yu
2022 J jnl
Faster Region-Based Hotspot Detection.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Ran Chen, Wei Zhong, Haoyu Yang, Hao Geng, Fan Yang, Xuan Zeng, Bei Yu
2022 J jnl
Fortune: A New Fault-Tolerance TSV Configuration in Router-Based Redundancy Structure.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Qi Xu, Hao Geng, Tianming Ni, Song Chen, Bei Yu, Yi Kang, Xiaoqing Wen
2022 A* conf
Functionality matters in netlist representation learning.
DAC
Ziyi Wang, Chen Bai, Zhuolun He, Guangliang Zhang, Qiang Xu, Tsung-Yi Ho, Bei Yu, Yu Huang
2022 A* conf
GTuner: tuning DNN computations on GPU via graph attention network.
DAC
Qi Sun, Xinyun Zhang, Hao Geng, Yuxuan Zhao, Yang Bai, Haisheng Zheng, Bei Yu
2022 J jnl
Generalized Parametric Contrastive Learning.
CoRR
Jiequan Cui, Zhisheng Zhong, Zhuotao Tian, Shu Liu, Bei Yu, Jiaya Jia
2022 J jnl
High-Speed Adder Design Space Exploration via Graph Neural Processes.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hao Geng, Yuzhe Ma, Qi Xu, Jin Miao, Subhendu Roy, Bei Yu
2022 J jnl
Hotspot Detection via Attention-Based Deep Layout Metric Learning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hao Geng, Haoyu Yang, Lu Zhang, Fan Yang, Xuan Zeng, Bei Yu
2022 A conf
LayouTransformer: Generating Layout Patterns with Transformer via Sequential Pattern Modeling.
ICCAD
Liangjian Wen, Yi Zhu, Lei Ye, Guojin Chen, Bei Yu, Jianzhuang Liu, Chunjing Xu
2022 J jnl
MLCAD: A Survey of Research in Machine Learning for CAD Keynote Paper.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Martin Rapp, Hussam Amrouch, Yibo Lin, Bei Yu, David Z. Pan, Marilyn Wolf, Jörg Henkel
2022 A conf
Mixed-Cell-Height Legalization on CPU-GPU Heterogeneous Systems.
DATE
Haoyu Yang, Kit Fung, Yuxuan Zhao, Yibo Lin, Bei Yu
2022 A conf
Multi-Package Co-Design for Chiplet Integration.
ICCAD
Zhen Zhuang, Bei Yu, Kai-Yuan Chao, Tsung-Yi Ho
2022 J jnl
Neural-ILT 2.0: Migrating ILT to Domain-Specific and Multitask-Enabled Neural Network.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Bentian Jiang, Lixin Liu, Yuzhe Ma, Bei Yu, Evangeline F. Y. Young
2022 A* conf
PCL: Proxy-based Contrastive Learning for Domain Generalization.
CVPR
Xufeng Yao, Yang Bai, Xinyun Zhang, Yuechen Zhang, Qi Sun, Ran Chen, Ruiyu Li, Bei Yu
2022 A* conf
PPATuner: pareto-driven tool parameter auto-tuning in physical design via gaussian process transfer learning.
DAC
Hao Geng, Qi Xu, Tsung-Yi Ho, Bei Yu
2022 J jnl
PVDD: A Practical Video Denoising Dataset with Real-World Dynamic Scenes.
CoRR
Xiaogang Xu, Yitong Yu, Nianjuan Jiang, Jiangbo Lu, Bei Yu, Jiaya Jia
2022 J jnl
Pin-Accessible Legalization for Mixed-Cell-Height Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Haocheng Li, Wing-Kai Chow, Gengjie Chen, Bei Yu, Evangeline F. Y. Young
2022 J jnl
Rethinking Graph Neural Networks for the Graph Coloring Problem.
CoRR
Wei Li, Ruxuan Li, Yuzhe Ma, Siu On Chan, David Z. Pan, Bei Yu
2022 A conf
TRADER: A Practical Track-Assignment-Based Detailed Router.
DATE
Zhen Zhuang, Genggeng Liu, Tsung-Yi Ho, Bei Yu, Wenzhong Guo
2022 — conf
Techniques for CAD Tool Parameter Auto-tuning in Physical Synthesis: A Survey (Invited Paper).
ASP-DAC
Hao Geng, Tinghuan Chen, Qi Sun, Bei Yu
2022 A conf
X-Check: CPU-Accelerated Design Rule Checking via Parallel Sweepline Algorithms.
ICCAD
Zhuolun He, Yuzhe Ma, Bei Yu
2021 A conf
A GPU-enabled Level Set Method for Mask Optimization.
DATE
Ziyang Yu, Guojin Chen, Yuzhe Ma, Bei Yu
2021 A conf
A High-Performance Accelerator for Super-Resolution Processing on Embedded GPU.
ICCAD
Wenqian Zhao, Qi Sun, Yang Bai, Wenbo Li, Haisheng Zheng, Bei Yu, Martin D. F. Wong
2021 A conf
A Unified Framework for Layout Pattern Analysis with Deep Causal Estimation.
ICCAD
Ran Chen, Shoubo Hu, Zhitang Chen, Shengyu Zhu, Bei Yu, Pengyun Li, Cheng Chen, Yu Huang, Jianye Hao
2021 — conf
Analog IC Aging-induced Degradation Estimation via Heterogeneous Graph Convolutional Networks.
ASP-DAC
Tinghuan Chen, Qi Sun, Canhui Zhan, Changze Liu, Huatao Yu, Bei Yu
2021 — conf
Attacking a CNN-based Layout Hotspot Detector Using Group Gradient Method.
ASP-DAC
Haoyu Yang, Shifan Zhang, Kang Liu, Siting Liu, Benjamin Tan, Ramesh Karri, Siddharth Garg, Bei Yu, Evangeline F. Y. Young
2021 A conf
AutoGTCO: Graph and Tensor Co-Optimize for Image Recognition with Transformers on GPU.
ICCAD
Yang Bai, Xufeng Yao, Qi Sun, Bei Yu
2021 A conf
BOOM-Explorer: RISC-V BOOM Microarchitecture Design Space Exploration Framework.
ICCAD
Chen Bai, Qi Sun, Jianwang Zhai, Yuzhe Ma, Bei Yu, Martin D. F. Wong
2021 J jnl
Bridging the Gap Between Layout Pattern Sampling and Hotspot Detection via Batch Active Learning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Haoyu Yang, Shuhe Li, Cyrus Tabery, Bingqing Lin, Bei Yu
2021 J jnl
Conditional Temporal Variational AutoEncoder for Action Video Prediction.
CoRR
Xiaogang Xu, Yi Wang, Liwei Wang, Bei Yu, Jiaya Jia
2021 A conf
Correlated Multi-objective Multi-fidelity Optimization for HLS Directives Design.
DATE
Qi Sun, Tinghuan Chen, Siting Liu, Jin Miao, Jianli Chen, Hao Yu, Bei Yu
2021 J jnl
DAC-SDC Low Power Object Detection Challenge for UAV Applications.
IEEE Trans. Pattern Anal. Mach. Intell.
Xiaowei Xu, Xinyi Zhang, Bei Yu, Xiaobo Sharon Hu, Christopher Rowen, Jingtong Hu, Yiyu Shi
2021 J jnl
Deep Learning Analysis for Split-Manufactured Layouts With Routing Perturbation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Haocheng Li, Satwik Patnaik, Mohammed Ashraf, Haoyu Yang, Johann Knechtel, Bei Yu, Ozgur Sinanoglu, Evangeline F. Y. Young
2021 A conf
Deep Neural Network Hardware Deployment Optimization via Advanced Active Learning.
DATE
Qi Sun, Chen Bai, Hao Geng, Bei Yu
2021 A conf
DevelSet: Deep Neural Level Set for Instant Mask Optimization.
ICCAD
Guojin Chen, Ziyang Yu, Hongduo Liu, Yuzhe Ma, Bei Yu
2021 J jnl
Efficient Layout Hotspot Detection via Binarized Residual Neural Network Ensemble.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yiyang Jiang, Fan Yang, Bei Yu, Dian Zhou, Xuan Zeng
2021 A* conf
Fast and Efficient DNN Deployment via Deep Gaussian Transfer Learning.
ICCV
Qi Sun, Chen Bai, Tinghuan Chen, Hao Geng, Xinyun Zhang, Yang Bai, Bei Yu
2021 A conf
Global Placement with Deep Learning-Enabled Explicit Routability Optimization.
DATE
Siting Liu, Qi Sun, Peiyu Liao, Yibo Lin, Bei Yu
2021 A conf
Graph Learning-Based Arithmetic Block Identification.
ICCAD
Zhuolun He, Ziyi Wang, Chen Bai, Haoyu Yang, Bei Yu
2021 A conf
Hotspot Detection via Multi-task Learning and Transformer Encoder.
ICCAD
Binwu Zhu, Ran Chen, Xinyun Zhang, Fan Yang, Xuan Zeng, Bei Yu, Martin D. F. Wong
2021 — conf
Learning Point Clouds in EDA.
ISPD
Wei Li, Guojin Chen, Haoyu Yang, Ran Chen, Bei Yu
2021 J jnl
Leveraging Spatial Correlation for Sensor Drift Calibration in Smart Building.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Tinghuan Chen, Bingqing Lin, Hao Geng, Shiyan Hu, Bei Yu
2021 A* conf
Low-Cost Lithography Hotspot Detection with Active Entropy Sampling and Model Calibration.
DAC
Yifeng Xiao, Miaodi Su, Haoyu Yang, Jianli Chen, Jun Yu, Bei Yu
2021 J jnl
Machine Learning for Electronic Design Automation: A Survey.
CoRR
Guyue Huang, Jingbo Hu, Yifan He, Jialong Liu, Mingyuan Ma, Zhaoyang Shen, Juejian Wu, Yuanfan Xu, Hengrui Zhang, Kai Zhong, Xuefei Ning, Yuzhe Ma, Haoyu Yang, Bei Yu, Huazhong Yang, Yu Wang
2021 J jnl
Machine Learning for Electronic Design Automation: A Survey.
ACM Trans. Design Autom. Electr. Syst.
Guyue Huang, Jingbo Hu, Yifan He, Jialong Liu, Mingyuan Ma, Zhaoyang Shen, Juejian Wu, Yuanfan Xu, Hengrui Zhang, Kai Zhong, Xuefei Ning, Yuzhe Ma, Haoyu Yang, Bei Yu, Huazhong Yang, Yu Wang
2021 — conf
Machine Learning in Nanometer AMS Design-for-Reliability : (Invited Paper).
ASICON
Tinghuan Chen, Qi Sun, Bei Yu
2021 A conf
McPAT-Calib: A Microarchitecture Power Modeling Framework for Modern CPUs.
ICCAD
Jianwang Zhai, Chen Bai, Binwu Zhu, Yici Cai, Qiang Zhou, Bei Yu
2021 A* conf
NeurFill: Migrating Full-Chip CMP Simulators to Neural Networks for Model-Based Dummy Filling Synthesis.
DAC
Junzhe Cai, Changhao Yan, Yuzhe Ma, Bei Yu, Dian Zhou, Xuan Zeng
2021 J jnl
OpenMPL: An Open-Source Layout Decomposer.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Wei Li, Yuzhe Ma, Qi Sun, Lu Zhang, Yibo Lin, Iris Hui-Ru Jiang, Bei Yu, David Z. Pan
2021 J jnl
PFENet++: Boosting Few-shot Semantic Segmentation with the Noise-filtered Context-aware Prior Mask.
CoRR
Xiaoliu Luo, Zhuotao Tian, Taiping Zhang, Bei Yu, Yuan Yan Tang, Jiaya Jia
2021 A* conf
Parametric Contrastive Learning.
ICCV
Jiequan Cui, Zhisheng Zhong, Shu Liu, Bei Yu, Jiaya Jia
2021 J jnl
Parametric Contrastive Learning.
CoRR
Jiequan Cui, Zhisheng Zhong, Shu Liu, Bei Yu, Jiaya Jia
2021 — conf
Physical Synthesis for Advanced Neural Network Processors.
ASP-DAC
Zhuolun He, Peiyu Liao, Siting Liu, Yuzhe Ma, Yibo Lin, Bei Yu
2021 J jnl
Routing Towards Discriminative Power of Class Capsules.
CoRR
Haoyu Yang, Shuhe Li, Bei Yu
2021 A* conf
Seeing Dynamic Scene in the Dark: A High-Quality Video Dataset with Mechatronic Alignment.
ICCV
Ruixing Wang, Xiaogang Xu, Chi-Wing Fu, Jiangbo Lu, Bei Yu, Jiaya Jia
2021 A conf
Towards AQFP-Capable Physical Design Automation.
DATE
Hongjia Li, Mengshu Sun, Tianyun Zhang, Olivia Chen, Nobuyuki Yoshikawa, Bei Yu, Yanzhi Wang, Yibo Lin
2021 — conf
TreeNet: Deep Point Cloud Embedding for Routing Tree Construction.
ASP-DAC
Wei Li, Yuxiao Qu, Gengjie Chen, Yuzhe Ma, Bei Yu
2021 J jnl
VLSI mask optimization: From shallow to deep learning.
Integr.
Haoyu Yang, Wei Zhong, Yuzhe Ma, Hao Geng, Ran Chen, Wanli Chen, Bei Yu
2021 A conf
When Wafer Failure Pattern Classification Meets Few-shot Learning and Self-Supervised Learning.
ICCAD
Hao Geng, Fan Yang, Xuan Zeng, Bei Yu
2020 J jnl
A Unified Framework for Simultaneous Layout Decomposition and Mask Optimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yuzhe Ma, Wei Zhong, Shuxiang Hu, Jhih-Rong Gao, Jian Kuang, Jin Miao, Bei Yu
2020 A* conf
Adaptive Layout Decomposition with Graph Embedding Neural Networks.
DAC
Wei Li, Jialu Xia, Yuzhe Ma, Jialu Li, Yibo Lin, Bei Yu
2020 J jnl
Adversarial Perturbation Attacks on ML-based CAD: A Case Study on CNN-based Lithographic Hotspot Detection.
ACM Trans. Design Autom. Electr. Syst.
Kang Liu, Haoyu Yang, Yuzhe Ma, Benjamin Tan, Bei Yu, Evangeline F. Y. Young, Ramesh Karri, Siddharth Garg
2020 J jnl
Attacking Split Manufacturing from a Deep Learning Perspective.
CoRR
Haocheng Li, Satwik Patnaik, Abhrajit Sengupta, Haoyu Yang, Johann Knechtel, Bei Yu, Evangeline F. Y. Young, Ozgur Sinanoglu
2020 A conf
Counteracting Adversarial Attacks in Autonomous Driving.
ICCAD
Qi Sun, Arjun Ashok Rao, Xufeng Yao, Bei Yu, Shiyan Hu
2020 A conf
DAMO: Deep Agile Mask Optimization for Full Chip Scale.
ICCAD
Guojin Chen, Wanli Chen, Yuzhe Ma, Haoyu Yang, Bei Yu
2020 J jnl
DAMO: Deep Agile Mask Optimization for Full Chip Scale.
CoRR
Guojin Chen, Wanli Chen, Yuzhe Ma, Haoyu Yang, Bei Yu
2020 J jnl
DSA guiding template assignment with multiple redundant via and dummy via insertion.
Integr.
Xingquan Li, Bei Yu, Jianli Chen, Wenxing Zhu
2020 A* conf
Deep Learning-Driven Simultaneous Layout Decomposition and Mask Optimization.
DAC
Wei Zhong, Shuxiang Hu, Yuzhe Ma, Haoyu Yang, Xiuyuan Ma, Bei Yu
2020 A* conf
DeepBillboard: systematic physical-world testing of autonomous driving systems.
ICSE
Husheng Zhou, Wei Li, Zelun Kong, Junfeng Guo, Yuqun Zhang, Bei Yu, Lingming Zhang, Cong Liu
2020 J jnl
Dive Deeper Into Box for Object Detection.
CoRR
Ran Chen, Yong Liu, Mengdan Zhang, Shu Liu, Bei Yu, Yu-Wing Tai
2020 — conf
Dive Deeper into Box for Object Detection.
ECCV (22)
Ran Chen, Yong Liu, Mengdan Zhang, Shu Liu, Bei Yu, Yu-Wing Tai
2020 J jnl
Fault tolerance in memristive crossbar-based neuromorphic computing systems.
Integr.
Qi Xu, Song Chen, Hao Geng, Bo Yuan, Bei Yu, Feng Wu, Zhengfeng Huang
2020 J jnl
GAN-OPC: Mask Optimization With Lithography-Guided Generative Adversarial Nets.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Haoyu Yang, Shuhe Li, Zihao Deng, Yuzhe Ma, Bei Yu, Evangeline F. Y. Young
2020 A conf
Hotspot Detection via Attention-based Deep Layout Metric Learning.
ICCAD
Hao Geng, Haoyu Yang, Lu Zhang, Jin Miao, Fan Yang, Xuan Zeng, Bei Yu
2020 C conf
Learn to Floorplan through Acquisition of Effective Local Search Heuristics.
ICCD
Zhuolun He, Yuzhe Ma, Lu Zhang, Peiyu Liao, Ngai Wong, Bei Yu, Martin D. F. Wong
2020 J jnl
Memristive Crossbar Mapping for Neuromorphic Computing Systems on 3D IC.
ACM Trans. Design Autom. Electr. Syst.
Qi Xu, Hao Geng, Song Chen, Bei Yu, Feng Wu
2020 A conf
Neural-ILT: Migrating ILT to Neural Networks for Mask Printability and Complexity Co-optimization.
ICCAD
Bentian Jiang, Lixin Liu, Yuzhe Ma, Hang Zhang, Bei Yu, Evangeline F. Y. Young
2020 C conf
Reliability-Driven Neural Network Training for Memristive Crossbar-Based Neuromorphic Computing Systems.
ISCAS
Junpeng Wang, Qi Xu, Bo Yuan, Song Chen, Bei Yu, Feng Wu
2020 J jnl
SRAF Insertion via Supervised Dictionary Learning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hao Geng, Wei Zhong, Haoyu Yang, Yuzhe Ma, Joydeep Mitra, Bei Yu
2020 — conf
Tensor Low-Rank Reconstruction for Semantic Segmentation.
ECCV (17)
Wanli Chen, Xinge Zhu, Ruoqi Sun, Junjun He, Ruiyu Li, Xiaoyong Shen, Bei Yu
2020 J jnl
Tensor Low-Rank Reconstruction for Semantic Segmentation.
CoRR
Wanli Chen, Xinge Zhu, Ruoqi Sun, Junjun He, Ruiyu Li, Xiaoyong Shen, Bei Yu
2020 J jnl
TimingCamouflage+: Netlist Security Enhancement With Unconventional Timing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Grace Li Zhang, Bing Li, Meng Li, Bei Yu, David Z. Pan, Michaela Brunner, Georg Sigl, Ulf Schlichtmann
2020 J jnl
TimingCamouflage+: Netlist Security Enhancement with Unconventional Timing (with Appendix).
CoRR
Grace Li Zhang, Bing Li, Meng Li, Bei Yu, David Z. Pan, Michaela Brunner, Georg Sigl, Ulf Schlichtmann
2020 — conf
Understanding Graphs in EDA: From Shallow to Deep Learning.
ISPD
Yuzhe Ma, Zhuolun He, Wei Li, Lu Zhang, Bei Yu
2020 — conf
VLSI Mask Optimization: From Shallow To Deep Learning.
ASP-DAC
Haoyu Yang, Wei Zhong, Yuzhe Ma, Hao Geng, Ran Chen, Wanli Chen, Bei Yu
2019 J jnl
A Practical Split Manufacturing Framework for Trojan Prevention via Simultaneous Wire Lifting and Cell Insertion.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Meng Li, Bei Yu, Yibo Lin, Xiaoqing Xu, Wuxi Li, David Z. Pan
2019 B conf
A Unified Approximation Framework for Compressing and Accelerating Deep Neural Networks.
ICTAI
Yuzhe Ma, Ran Chen, Wei Li, Fanhua Shang, Wenjian Yu, Minsik Cho, Bei Yu
2019 — conf
A local optimal method on DSA guiding template assignment with redundant/dummy via insertion.
ASP-DAC
Xingquan Li, Bei Yu, Jianli Chen, Wenxing Zhu
2019 J jnl
Adaptive 3D-IC TSV Fault Tolerance Structure Generation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Song Chen, Qi Xu, Bei Yu
2019 J jnl
Are Adversarial Perturbations a Showstopper for ML-Based CAD? A Case Study on CNN-Based Lithographic Hotspot Detection.
CoRR
Kang Liu, Haoyu Yang, Yuzhe Ma, Benjamin Tan, Bei Yu, Evangeline F. Y. Young, Ramesh Karri, Siddharth Garg
2019 A* conf
Attacking Split Manufacturing from a Deep Learning Perspective.
DAC
Haocheng Li, Satwik Patnaik, Abhrajit Sengupta, Haoyu Yang, Johann Knechtel, Bei Yu, Evangeline F. Y. Young, Ozgur Sinanoglu
2019 J jnl
Automatic Layout Generation with Applications in Machine Learning Engine Evaluation.
CoRR
Haoyu Yang, Wen Chen, Piyush Pathak, Frank Gennari, Ya-Chieh Lai, Bei Yu
2019 J jnl
CAD Tool Design Space Exploration via Bayesian Optimization.
CoRR
Yuzhe Ma, Ziyang Yu, Bei Yu
2019 J jnl
Cross-Layer Optimization for High Speed Adders: A Pareto Driven Machine Learning Approach.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yuzhe Ma, Subhendu Roy, Jin Miao, Jiamin Chen, Bei Yu
2019 A* conf
DeePattern: Layout Pattern Generation with Transforming Convolutional Auto-Encoder.
DAC
Haoyu Yang, Piyush Pathak, Frank Gennari, Ya-Chieh Lai, Bei Yu
2019 — conf
Detecting multi-layer layout hotspots with adaptive squish patterns.
ASP-DAC
Haoyu Yang, Piyush Pathak, Frank Gennari, Ya-Chieh Lai, Bei Yu
2019 A* conf
Efficient Layout Hotspot Detection via Binarized Residual Neural Network.
DAC
Yiyang Jiang, Fan Yang, Hengliang Zhu, Bei Yu, Dian Zhou, Xuan Zeng
2019 A* conf
FIT: Fill Insertion Considering Timing.
DAC
Bentian Jiang, Xiaopeng Zhang, Ran Chen, Gengjie Chen, Peishan Tu, Wei Li, Evangeline F. Y. Young, Bei Yu
2019 A* conf
Faster Region-based Hotspot Detection.
DAC
Ran Chen, Wei Zhong, Haoyu Yang, Hao Geng, Xuan Zeng, Bei Yu
2019 — conf
Hardware-software co-design of slimmed optical neural networks.
ASP-DAC
Zheng Zhao, Derong Liu, Meng Li, Zhoufeng Ying, Lu Zhang, Biying Xu, Bei Yu, Ray T. Chen, David Z. Pan
2019 A* conf
High Performance Graph Convolutional Networks with Applications in Testability Analysis.
DAC
Yuzhe Ma, Haoxing Ren, Brucek Khailany, Harbinder Sikka, Lijuan Luo, Karthikeyan Natarajan, Bei Yu
2019 J jnl
Layout Hotspot Detection With Feature Tensor Generation and Deep Biased Learning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Haoyu Yang, Jing Su, Yi Zou, Yuzhe Ma, Bei Yu, Evangeline F. Y. Young
2019 — conf
OpenMPL: An Open Source Layout Decomposer: Invited Paper.
ASICON
Wei Li, Yuzhe Ma, Qi Sun, Yibo Lin, Iris Hui-Ru Jiang, Bei Yu, David Z. Pan
2019 A conf
Power-Driven DNN Dataflow Optimization on FPGA.
ICCAD
Qi Sun, Tinghuan Chen, Jin Miao, Bei Yu
2019 J jnl
Provably Secure Camouflaging Strategy for IC Protection.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Meng Li, Kaveh Shamsi, Travis Meade, Zheng Zhao, Bei Yu, Yier Jin, David Z. Pan
2019 J jnl
Recent advances in convolutional neural network acceleration.
Neurocomputing
Qianru Zhang, Meng Zhang, Tinghuan Chen, Zhifei Sun, Yuzhe Ma, Bei Yu
2019 — conf
SRAF insertion via supervised dictionary learning.
ASP-DAC
Hao Geng, Haoyu Yang, Yuzhe Ma, Joydeep Mitra, Bei Yu
2019 A* conf
Sensor Drift Calibration via Spatial Correlation Model in Smart Building.
DAC
Tinghuan Chen, Bingqing Lin, Hao Geng, Bei Yu
2019 J jnl
Synergistic Topology Generation and Route Synthesis for On-Chip Performance-Critical Signal Groups.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Derong Liu, Bei Yu, Vinicius S. Livramento, Salim Chowdhury, Duo Ding, Huy Vo, Akshay Sharma, David Z. Pan
2019 J jnl
VLSI Mask Optimization: From Shallow To Deep Learning.
CoRR
Haoyu Yang, Wei Zhong, Yuzhe Ma, Hao Geng, Ran Chen, Wanli Chen, Bei Yu
2018 J jnl
A Multicommodity Flow-Based Detailed Router With Efficient Acceleration Techniques.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Xiaotao Jia, Yici Cai, Qiang Zhou, Bei Yu
2018 J jnl
A Unified Approximation Framework for Deep Neural Networks.
CoRR
Yuzhe Ma, Ran Chen, Wei Li, Fanhua Shang, Wenjian Yu, Minsik Cho, Bei Yu
2018 — conf
A practical split manufacturing framework for Trojan prevention via simultaneous wire lifting and cell insertion.
ASP-DAC
Meng Li, Bei Yu, Yibo Lin, Xiaoqing Xu, Wuxi Li, David Z. Pan
2018 J jnl
Adaptive 3D-IC TSV Fault Tolerance Structure Generation.
CoRR
Song Chen, Qi Xu, Bei Yu
2018 J jnl
Bridging the Gap Between Layout Pattern Sampling and Hotspot Detection via Batch Active Learning.
CoRR
Haoyu Yang, Shuhe Li, Cyrus Tabery, Bingqing Lin, Bei Yu
2018 J jnl
CRMA: Incorporating Cut Redistribution With Mask Assignment to Enable the Fabrication of 1-D Gridded Design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jian Kuang, Evangeline F. Y. Young, Bei Yu
2018 J jnl
Cross-layer Optimization for High Speed Adders: A Pareto Driven Machine Learning Approach.
CoRR
Yuzhe Ma, Subhendu Roy, Jin Miao, Jiamin Chen, Bei Yu
2018 J jnl
DAC-SDC Low Power Object Detection Challenge for UAV Applications.
CoRR
Xiaowei Xu, Xinyi Zhang, Bei Yu, Xiaobo Sharon Hu, Christopher Rowen, Jingtong Hu, Yiyu Shi
2018 J jnl
DeepBillboard: Systematic Physical-World Testing of Autonomous Driving Systems.
CoRR
Husheng Zhou, Wei Li, Yuankun Zhu, Yuqun Zhang, Bei Yu, Lingming Zhang, Cong Liu
2018 A* conf
GAN-OPC: mask optimization with lithography-guided generative adversarial nets.
DAC
Haoyu Yang, Shuhe Li, Yuzhe Ma, Bei Yu, Evangeline F. Y. Young
2018 J jnl
Graph-Based Redundant Via Insertion and Guiding Template Assignment for DSA-MP.
IEEE Trans. Very Large Scale Integr. Syst.
Xingquan Li, Bei Yu, Jiaojiao Ou, Jianli Chen, David Z. Pan, Wenxing Zhu
2018 J jnl
IEEE Transactions on Sustainable Computing: Guest Editorial on Special Issue on Sustainable Cyber-Physical Systems.
IEEE Trans. Sustain. Comput.
Shiyan Hu, Bei Yu, Huafeng Yu
2018 J jnl
Layout Synthesis for Topological Quantum Circuits With 1-D and 2-D Architectures.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yibo Lin, Bei Yu, Meng Li, David Z. Pan
2018 — conf
Memristive Crossbar Mapping for Neuromorphic Computing Systems on 3D IC.
ACM Great Lakes Symposium on VLSI
Qi Xu, Song Chen, Bei Yu, Feng Wu
2018 J jnl
MrDP: Multiple-Row Detailed Placement of Heterogeneous-Sized Cells for Advanced Nodes.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yibo Lin, Bei Yu, Xiaoqing Xu, Jhih-Rong Gao, Natarajan Viswanathan, Wen-Hao Liu, Zhuo Li, Charles J. Alpert, David Z. Pan
2018 J jnl
OpenMPL: An Open Source Layout Decomposer.
CoRR
Qi Sun, Yibo Lin, Iris Hui-Ru Jiang, Bei Yu, David Z. Pan
2018 — conf
Power Grid Reduction by Sparse Convex Optimization.
ISPD
Wei Ye, Meng Li, Kai Zhong, Bei Yu, David Z. Pan
2018 J jnl
Recent Advances in Convolutional Neural Network Acceleration.
CoRR
Qianru Zhang, Meng Zhang, Tinghuan Chen, Zhifei Sun, Yuzhe Ma, Bei Yu
2018 J jnl
RippleFPGA: Routability-Driven Simultaneous Packing and Placement for Modern FPGAs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Gengjie Chen, Chak-Wa Pui, Wing-Kai Chow, Ka-Chun Lam, Jian Kuang, Evangeline F. Y. Young, Bei Yu
2018 A* conf
Routability-driven and fence-aware legalization for mixed-cell-height circuits.
DAC
Haocheng Li, Wing-Kai Chow, Gengjie Chen, Evangeline F. Y. Young, Bei Yu
2018 J jnl
SD-PUF: Spliced Digital Physical Unclonable Function.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jin Miao, Meng Li, Subhendu Roy, Yuzhe Ma, Bei Yu
2018 — conf
Sparse VLSI Layout Feature Extraction: A Dictionary Learning Approach.
ISVLSI
Hao Geng, Haoyu Yang, Bei Yu, Xingquan Li, Xuan Zeng
2018 J jnl
TILA-S: Timing-Driven Incremental Layer Assignment Avoiding Slew Violations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Derong Liu, Bei Yu, Salim Chowdhury, David Z. Pan
2018 C conf
Thermal-Aware Placement and Routing for 3D Optical Networks-on-Chips.
ISCAS
Fengxian Jiao, Sheqin Dong, Bei Yu, Bing Li, Ulf Schlichtmann
2018 A conf
TimingCamouflage: Improving circuit security against counterfeiting by unconventional timing.
DATE
Grace Li Zhang, Bing Li, Bei Yu, David Z. Pan, Ulf Schlichtmann
2017 A conf
A learning bridge from architectural synthesis to physical design for exploring power efficient high-performance adders.
ISLPED
Subhendu Roy, Yuzhe Ma, Jin Miao, Bei Yu
2017 A conf
A unified framework for simultaneous layout decomposition and mask optimization.
ICCAD
Yuzhe Ma, Jhih-Rong Gao, Jian Kuang, Jin Miao, Bei Yu
2017 A conf
A utility-driven data transmission optimization strategy in large scale cyber-physical systems.
DATE
Soumi Chattopadhyay, Ansuman Banerjee, Bei Yu
2017 — conf
Accelerating chip design with machine learning: From pre-silicon to post-silicon.
SoCC
Cheng Zhuo, Bei Yu, Di Gao
2017 — conf
Bilinear Lithography Hotspot Detection.
ISPD
Hang Zhang, Fengyuan Zhu, Haocheng Li, Evangeline F. Y. Young, Bei Yu
2017 A conf
Clock-aware ultrascale FPGA placement with machine learning routability prediction: (Invited paper).
ICCAD
Chak-Wa Pui, Gengjie Chen, Yuzhe Ma, Evangeline F. Y. Young, Bei Yu
2017 J jnl
Clustered Fault Tolerance TSV Planning for 3-D Integrated Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Qi Xu, Song Chen, Xiaodong Xu, Bei Yu
2017 — conf
DSAR: DSA aware Routing with Simultaneous DSA Guiding Pattern and Double Patterning Assignment.
ISPD
Jiaojiao Ou, Bei Yu, Xiaoqing Xu, Joydeep Mitra, Yibo Lin, David Z. Pan
2017 — conf
F1B: Algorithms, models and simulation for systems.
SoCC
Bei Yu
2017 J jnl
High Performance Dummy Fill Insertion With Coupling and Uniformity Constraints.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yibo Lin, Bei Yu, David Z. Pan
2017 J jnl
Incremental Layer Assignment Driven by an External Signoff Timing Engine.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Vinicius S. Livramento, Derong Liu, Salim Chowdhury, Bei Yu, Xiaoqing Xu, David Z. Pan, José Luís Almada Güntzel, Luiz C. V. dos Santos
2017 J jnl
Incremental Layer Assignment for Timing Optimization.
ACM Trans. Design Autom. Electr. Syst.
Derong Liu, Bei Yu, Salim Chowdhury, David Z. Pan
2017 A* conf
Layout Hotspot Detection with Feature Tensor Generation and Deep Biased Learning.
DAC
Haoyu Yang, Jing Su, Yi Zou, Bei Yu, Evangeline F. Y. Young
2017 — conf
Lithography hotspot detection: From shallow to deep learning.
SoCC
Haoyu Yang, Yajun Lin, Bei Yu, Evangeline F. Y. Young
2017 C conf
Methodologies for layout decomposition and mask optimization: A systematic review.
VLSI-SoC
Yuzhe Ma, Xuan Zeng, Bei Yu
2017 A* conf
Minimizing Thermal Gradient and Pumping Power in 3D IC Liquid Cooling Network Design.
DAC
Gengjie Chen, Jian Kuang, Zhiliang Zeng, Hang Zhang, Evangeline F. Y. Young, Bei Yu
2017 J jnl
Smart building uncertainty analysis via adaptive Lasso.
IET Cyper-Phys. Syst.: Theory & Appl.
Bingqing Lin, Bei Yu
2017 J jnl
Special Issue on Scalable Cyber-Physical Systems.
J. Parallel Distributed Comput.
Meikang Qiu, Saurabh Kumar Garg, Rajkumar Buyya, Bei Yu, Shiyan Hu
2017 J jnl
Stitch aware detailed placement for multiple E-beam lithography.
Integr.
Yibo Lin, Bei Yu, Yi Zou, Zhuo Li, Charles J. Alpert, David Z. Pan
2017 J jnl
Triple Patterning Aware Detailed Placement Toward Zero Cross-Row Middle-of-Line Conflict.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yibo Lin, Bei Yu, Biying Xu, David Z. Pan
2016 — conf
Concurrent Guiding Template Assignment and Redundant via Insertion for DSA-MP Hybrid Lithography.
ISPD
Jiaojiao Ou, Bei Yu, David Z. Pan
2016 J jnl
Design for manufacturability and reliability in extreme-scaling VLSI.
Sci. China Inf. Sci.
Bei Yu, Xiaoqing Xu, Subhendu Roy, Yibo Lin, Jiaojiao Ou, David Z. Pan
2016 J jnl
EBL Overlapping Aware Stencil Planning for MCC System.
ACM Trans. Design Autom. Electr. Syst.
Bei Yu, Kun Yuan, Jhih-Rong Gao, Shiyan Hu, David Z. Pan
2016 A conf
Enabling online learning in lithography hotspot detection with information-theoretic feature optimization.
ICCAD
Hang Zhang, Bei Yu, Evangeline F. Y. Young
2016 A conf
Incorporating cut redistribution with mask assignment to enable 1D gridded design.
ICCAD
Jian Kuang, Evangeline F. Y. Young, Bei Yu
2016 A* conf
Incremental layer assignment for critical path timing.
DAC
Derong Liu, Bei Yu, Salim Chowdhury, David Z. Pan
2016 A conf
LRR-DPUF: learning resilient and reliable digital physical unclonable function.
ICCAD
Jin Miao, Meng Li, Subhendu Roy, Bei Yu
2016 — conf
Laplacian eigenmaps and bayesian clustering based layout pattern sampling and its applications to hotspot detection and OPC.
ASP-DAC
Tetsuaki Matsunawa, Bei Yu, David Z. Pan
2016 — ch.
Layout Decomposition for Triple Patterning.
Encyclopedia of Algorithms
Bei Yu, David Z. Pan
2016 — conf
MCFRoute 2.0: A Redundant Via Insertion Enhanced Concurrent Detailed Router.
ACM Great Lakes Symposium on VLSI
Xiaotao Jia, Yici Cai, Qiang Zhou, Bei Yu
2016 A conf
MrDP: multiple-row detailed placement of heterogeneous-sized cells for advanced nodes.
ICCAD
Yibo Lin, Bei Yu, Xiaoqing Xu, Jhih-Rong Gao, Natarajan Viswanathan, Wen-Hao Liu, Zhuo Li, Charles J. Alpert, David Z. Pan
2016 J jnl
PARR: Pin-Access Planning and Regular Routing for Self-Aligned Double Patterning.
ACM Trans. Design Autom. Electr. Syst.
Xiaoqing Xu, Bei Yu, Jhih-Rong Gao, Che-Lun Hsu, David Z. Pan
2016 A conf
Provably secure camouflaging strategy for IC protection.
ICCAD
Meng Li, Kaveh Shamsi, Travis Meade, Zheng Zhao, Bei Yu, Yier Jin, David Z. Pan
2016 A conf
RippleFPGA: a routability-driven placement for large-scale heterogeneous FPGAs.
ICCAD
Chak-Wa Pui, Gengjie Chen, Wing-Kai Chow, Ka-Chun Lam, Jian Kuang, Peishan Tu, Hang Zhang, Evangeline F. Y. Young, Bei Yu
2016 — conf
Stitch aware detailed placement for multiple e-beam lithography.
ASP-DAC
Yibo Lin, Bei Yu, Yi Zou, Zhuo Li, Charles J. Alpert, David Z. Pan
2016 — conf
VLSI layout hotspot detection based on discriminative feature extraction.
APCCAS
Hang Zhang, Haoyu Yang, Bei Yu, Evangeline F. Y. Young
2015 — conf
Directed Self-Assembly Based Cut Mask Optimization for Unidirectional Design.
ACM Great Lakes Symposium on VLSI
Jiaojiao Ou, Bei Yu, Jhih-Rong Gao, David Z. Pan, Moshe Preil, Azat Latypov
2015 J jnl
E-BLOW: E-Beam Lithography Overlapping aware Stencil Planning for MCC System.
CoRR
Bei Yu, Kun Yuan, Jhih-Rong Gao, David Z. Pan
2015 — conf
Electromigration-aware redundant via insertion.
ASP-DAC
Jiwoo Pak, Bei Yu, David Z. Pan
2015 A* conf
High performance dummy fill insertion with coupling and uniformity constraints.
DAC
Yibo Lin, Bei Yu, David Z. Pan
2015 J jnl
Layout Decomposition for Triple Patterning Lithography.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Bei Yu, Kun Yuan, Duo Ding, David Z. Pan
2015 — conf
Machine learning and pattern matching in physical design.
ASP-DAC
Bei Yu, David Z. Pan, Tetsuaki Matsunawa, Xuan Zeng
2015 J jnl
Methodology for Standard Cell Compliance and Detailed Placement for Triple Patterning Lithography.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Bei Yu, Xiaoqing Xu, Jhih-Rong Gao, Yibo Lin, Zhuo Li, Charles J. Alpert, David Z. Pan
2015 A* conf
PARR: pin access planning and regular routing for self-aligned double patterning.
DAC
Xiaoqing Xu, Bei Yu, Jhih-Rong Gao, Che-Lun Hsu, David Z. Pan
2015 A* conf
Pushing multiple patterning in sub-10nm: are we ready?
DAC
David Z. Pan, Lars Liebmann, Bei Yu, Xiaoqing Xu, Yibo Lin
2015 J jnl
Self-Aligned Double Patterning Aware Pin Access and Standard Cell Layout Co-Optimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Xiaoqing Xu, Brian Cline, Greg Yeric, Bei Yu, David Z. Pan
2015 — conf
Standard Cell Layout Regularity and Pin Access Optimization Considering Middle-of-Line.
ACM Great Lakes Symposium on VLSI
Wei Ye, Bei Yu, David Z. Pan, Yongchan Ban, Lars Liebmann
2015 A conf
TILA: Timing-Driven Incremental Layer Assignment.
ICCAD
Bei Yu, Derong Liu, Salim Chowdhury, David Z. Pan
2015 A conf
Triple Patterning Aware Detailed Placement Toward Zero Cross-Row Middle-of-Line Conflict.
ICCAD
Yibo Lin, Bei Yu, Biying Xu, David Z. Pan
2014 J jnl
A High-Performance Triple Patterning Layout Decomposer with Balanced Density.
CoRR
Bei Yu, Yen-Hung Lin, Gerard Luk-Pat, Duo Ding, Kevin Lucas, David Z. Pan
2014 J jnl
E-BLOW: E-Beam Lithography Overlapping aware Stencil Planning for MCC System.
CoRR
Bei Yu, Kun Yuan, Jhih-Rong Gao, David Z. Pan
2014 J jnl
EPIC: Efficient prediction of IC manufacturing hotspots with a unified meta-classification formulation.
CoRR
Duo Ding, Bei Yu, Joydeep Ghosh, David Z. Pan
2014 J jnl
Floorplanning and Topology Generation for Application-Specific Network-on-Chip.
CoRR
Bei Yu, Sheqin Dong, Song Chen, Satoshi Goto
2014 J jnl
GLOW: A global router for low-power thermal-reliable interconnect synthesis using photonic wavelength multiplexing.
CoRR
Duo Ding, Bei Yu, David Z. Pan
2014 J jnl
L-Shape based Layout Fracturing for E-Beam Lithography.
CoRR
Bei Yu, Jhih-Rong Gao, David Z. Pan
2014 A* conf
Layout Decomposition for Quadruple Patterning Lithography and Beyond.
DAC
Bei Yu, David Z. Pan
2014 J jnl
Layout Decomposition for Quadruple Patterning Lithography and Beyond.
CoRR
Bei Yu, David Z. Pan
2014 J jnl
Layout decomposition for triple patterning lithography.
CoRR
Bei Yu, Kun Yuan, Boyang Zhang, Duo Ding, David Z. Pan
2014 J jnl
Lithography Hotspot Detection and Mitigation in Nanometer VLSI.
CoRR
Jhih-Rong Gao, Bei Yu, David Z. Pan
2014 A* conf
MOSAIC: Mask Optimizing Solution With Process Window Aware Inverse Correction.
DAC
Jhih-Rong Gao, Xiaoqing Xu, Bei Yu, David Z. Pan
2014 J jnl
Methodology for standard cell compliance and detailed placement for triple patterning lithography.
CoRR
Bei Yu, Xiaoqing Xu, Jhih-Rong Gao, David Z. Pan
2014 J jnl
Multi-Voltage and Level-Shifter Assignment Driven Floorplanning.
CoRR
Bei Yu, Sheqin Dong, Satoshi Goto
2014 J jnl
Network flow-based simultaneous retiming and slack budgeting for low power design.
CoRR
Bei Yu, Sheqin Dong, Yuchun Ma, Tao Lin, Yu Wang, Song Chen, Satoshi Goto
2014 J jnl
Self-Aligned Double Patterning Friendly Configuration for Standard Cell Library Considering Placement.
CoRR
Jhih-Rong Gao, Bei Yu, Ru Huang, David Z. Pan
2014 — conf
Self-aligned double patterning aware pin access and standard cell layout co-optimization.
ISPD
Xiaoqing Xu, Brian Cline, Greg Yeric, Bei Yu, David Z. Pan
2014 — conf
Self-aligned double patterning layout decomposition with complementary e-beam lithography.
ASP-DAC
Jhih-Rong Gao, Bei Yu, David Z. Pan
2014 J jnl
TRIAD: a triple patterning lithography aware detailed router.
CoRR
Yen-Hung Lin, Bei Yu, David Z. Pan, Yih-Lang Li
2014 J jnl
Triple Patterning Lithography (TPL) Layout Decomposition using End-Cutting (JM3 Special Session).
CoRR
Bei Yu, Subhendu Roy, Jhih-Rong Gao, David Z. Pan
2014 J jnl
Triple Patterning Lithography (TPL) Layout Decomposition using End-Cutting.
CoRR
Bei Yu, Jhih-Rong Gao, David Z. Pan
2014 J jnl
Voltage and Level-Shifter Assignment Driven Floorplanning.
CoRR
Bei Yu, Sheqin Dong, Song Chen, Satoshi Goto
2013 A conf
A high-performance triple patterning layout decomposer with balanced density.
ICCAD
Bei Yu, Yen-Hung Lin, Gerard Luk-Pat, Duo Ding, Kevin Lucas, David Z. Pan
2013 J jnl
Design for Manufacturing With Emerging Nanolithography.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
David Z. Pan, Bei Yu, Jhih-Rong Gao
2013 A* conf
E-BLOW: e-beam lithography overlapping aware stencil planning for MCC system.
DAC
Bei Yu, Kun Yuan, Jhih-Rong Gao, David Z. Pan
2013 — conf
L-shape based layout fracturing for e-beam lithography.
ASP-DAC
Bei Yu, Jhih-Rong Gao, David Z. Pan
2013 — conf
Lithography hotspot detection and mitigation in nanometer VLSI.
ASICON
Jhih-Rong Gao, Bei Yu, Duo Ding, David Z. Pan
2013 A conf
Methodology for standard cell compliance and detailed placement for triple patterning lithography.
ICCAD
Bei Yu, Xiaoqing Xu, Jhih-Rong Gao, David Z. Pan
2012 J jnl
Cluster Generation and Network Component Insertion for Topology Synthesis of Application-Specific Network-on-Chips.
IEICE Trans. Electron.
Wei Zhong, Takeshi Yoshimura, Bei Yu, Song Chen, Sheqin Dong, Satoshi Goto
2012 A conf
Dealing with IC manufacturability in extreme scaling (Embedded tutorial paper).
ICCAD
Bei Yu, Jhih-Rong Gao, Duo Ding, Yongchan Ban, Jae-Seok Yang, Kun Yuan, Minsik Cho, David Z. Pan
2012 J jnl
E-Beam Lithography Stencil Planning and Optimization With Overlapped Characters.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Kun Yuan, Bei Yu, David Z. Pan
2012 — conf
EPIC: Efficient prediction of IC manufacturing hotspots with a unified meta-classification formulation.
ASP-DAC
Duo Ding, Bei Yu, Joydeep Ghosh, David Z. Pan
2012 — conf
GLOW: A global router for low-power thermal-reliable interconnect synthesis using photonic wavelength multiplexing.
ASP-DAC
Duo Ding, Bei Yu, David Z. Pan
2012 A conf
TRIAD: A triple patterning lithography aware detailed router.
ICCAD
Yen-Hung Lin, Bei Yu, David Z. Pan, Yih-Lang Li
2012 — conf
VLSI CAD for emerging nanolithography.
VLSI-DAT
David Z. Pan, Jhih-Rong Gao, Bei Yu
2011 — conf
Application-specific Network-on-Chip synthesis: Cluster generation and network component insertion.
ISQED
Wei Zhong, Bei Yu, Song Chen, Takeshi Yoshimura, Sheqin Dong, Satoshi Goto
2011 A conf
Layout decomposition for triple patterning lithography.
ICCAD
Bei Yu, Kun Yuan, Boyang Zhang, Duo Ding, David Z. Pan
2011 — conf
Network flow-based simultaneous retiming and slack budgeting for low power design.
ASP-DAC
Bei Yu, Sheqin Dong, Yuchun Ma, Tao Lin, Yu Wang, Song Chen, Satoshi Goto
2010 — conf
A revisit to voltage partitioning problem.
ACM Great Lakes Symposium on VLSI
Tao Lin, Sheqin Dong, Bei Yu, Song Chen, Satoshi Goto
2010 — conf
Floorplanning and topology generation for application-specific network-on-chip.
ASP-DAC
Bei Yu, Sheqin Dong, Song Chen, Satoshi Goto
2009 J jnl
Voltage and Level-Shifter Assignment Driven Floorplanning.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Bei Yu, Sheqin Dong, Song Chen, Satoshi Goto
2009 — conf
Voltage-island driven floorplanning considering level-shifter positions.
ACM Great Lakes Symposium on VLSI
Bei Yu, Sheqin Dong, Satoshi Goto, Song Chen