Behzad Razavi - RankMe

175 papers A* 2C 8Journal 94Unranked 71

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	A Predictive SAR ADC Architecture. IEEE Trans. Circuits Syst. I Regul. Pap. Matias Jara, Behzad Razavi
2024	—	`conf`	A 56-Gb/s 17-mW NRZ Receiver in 0.018 mm VLSI Technology and Circuits Kshitiz Tyagi, Behzad Razavi
2023	—	`conf`	A 112-Gb/s 58-mW PAM4 Transmitter in 28-nm CMOS Technology. VLSI Technology and Circuits Mahdi Forghani, Yu Zhao, Pawan K. Khanna, Behzad Razavi
2023	J	`jnl`	A 20-GHz PLL With 20.9-fs Random Jitter. IEEE J. Solid State Circuits Yu Zhao, Mahdi Forghani, Behzad Razavi
2023	J	`jnl`	A 300-GHz 52-mW CMOS Receiver With On-Chip LO Generation. IEEE J. Solid State Circuits Onur Memioglu, Yu Zhao, Behzad Razavi
2023	J	`jnl`	A 56-GHz Fractional-N PLL With 110-fs Jitter. IEEE J. Solid State Circuits Yu Zhao, Onur Memioglu, Long Kong, Behzad Razavi
2023	—	`conf`	A 6-bit 10-GS/s 17.6-mW CMOS ADC with 0.8-V supply. CICC Matias Jara, Behzad Razavi
2023	—	`conf`	A Low-Power 28-GHz Beamforming Receiver with On-Chip LO Synthesis. ESSCIRC Pawan K. Khanna, Yu Zhao, Mahdi Forghani, Behzad Razavi
2023	J	`jnl`	A Study of Injection Locking in Oscillators and Frequency Dividers. IEEE J. Solid State Circuits Hossein Razavi, Behzad Razavi
2023	J	`jnl`	Performance Bounds of ADC-Based Receivers Due to Clock Jitter. IEEE Trans. Circuits Syst. II Express Briefs Kshitiz Tyagi, Behzad Razavi
2022	J	`jnl`	A 0.4-6 GHz Receiver for Cellular and WiFi Applications. IEEE J. Solid State Circuits Hossein Razavi, Behzad Razavi
2022	—	`conf`	A 300GHz 52mW CMOS Receiver with On-Chip LO Generation. ISSCC Onur Memioglu, Yu Zhao, Behzad Razavi
2022	J	`jnl`	A 56-Gb/s 50-mW NRZ Receiver in 28-nm CMOS. IEEE J. Solid State Circuits Atharav Atharav, Behzad Razavi
2022	J	`jnl`	A 56-Gb/s 8-mW PAM4 CDR/DMUX With High Jitter Tolerance. IEEE J. Solid State Circuits Guanrong Hou, Behzad Razavi
2022	—	`conf`	A 56GHz 23mW Fractional-N PLL with 110fs Jitter. ISSCC Yu Zhao, Onur Memioglu, Behzad Razavi
2022	C	`conf`	Circuit Bandwidth Requirements for NRZ and PAM4 Signals. ISCAS Mahdi Forghani, Behzad Razavi
2022	C	`conf`	Optimal Distribution of High-Speed Clocks on Transceiver Chips. ISCAS Makar Chand Snai, Behzad Razavi
2022	C	`conf`	Phase Noise Integration Limits for Jitter Calculation. ISCAS Yu Zhao, Behzad Razavi
2022	J	`jnl`	Relation Between INL and ACPR of RF DACs. IEEE Trans. Circuits Syst. I Regul. Pap. Seyed Mehrdad Babamir, Behzad Razavi
2021	—	`conf`	11.7 A 56Gb/s 50mW NRZ Receiver in 28nm CMOS. ISSCC Atharav Atharav, Behzad Razavi
2021	—	`conf`	A 0.4-6 GHz Receiver for LTE and WiFi. VLSI Circuits Hossein Razavi, Behzad Razavi
2021	—	`conf`	A 19-GHz PLL with 20.3-fs Jitter. VLSI Circuits Yu Zhao, Behzad Razavi
2021	—	`conf`	A 27-73 GHz Injection-Locked Frequency Divider. VLSI Circuits Hossein Razavi, Behzad Razavi
2021	—	`conf`	A 56-Gb/s 8-mW PAM4 CDR/DMUX with High Jitter Tolerance. VLSI Circuits Guanrong Hou, Behzad Razavi
2021	J	`jnl`	Jitter-Power Trade-Offs in PLLs. IEEE Trans. Circuits Syst. I Regul. Pap. Behzad Razavi
2021	—	`conf`	Low-Power Techniques for Wireline Systems. ESSCIRC Behzad Razavi
2020	J	`jnl`	A Digital RF Transmitter With Background Nonlinearity Correction. IEEE J. Solid State Circuits Seyed Mehrdad Babamir, Behzad Razavi
2020	C	`conf`	Lower Bounds on Power Consumption of Clock Generators for ADCs. ISCAS Behzad Razavi
2019	—	`conf`	A Fractional-N Synthesizer with 110fsrms Jitter and a Reference Quadrupler for Wideband 802.11ax. ISSCC Fei Song, Yu Zhao, Bart Wu, Litian Tang, Leon Lin, Behzad Razavi
2019	J	`jnl`	An Inductorless 20-Gb/s CDR With High Jitter Tolerance. IEEE J. Solid State Circuits Long Kong, Yikun Chang, Behzad Razavi
2019	J	`jnl`	Instrument Design and Performance of the High-Frequency Airborne Microwave and Millimeter-Wave Radiometer. IEEE J. Sel. Top. Appl. Earth Obs. Remote. Sens. Xavier Bosch-Lluis, Victoria D. Hadel, Thaddeus P. Johnson, Mehmet Ogut, James Ranson, Steven C. Reising, Pekka Kangaslahti, Alan B. Tanner, Shannon T. Brown, Sharmila Padmanabhan, Chaitali Parashare, Oliver Montes, Behzad Razavi
2018	—	`conf`	A 14 µM × 26 µM 20-GB/S 3-MW CDR Circuit with High Jitter Tolerance. VLSI Circuits Long Kong, Yikun Chang, Behzad Razavi
2018	J	`jnl`	A 2.4-GHz RF Fractional-N Synthesizer With BW = 0.25f IEEE J. Solid State Circuits Long Kong, Behzad Razavi
2018	—	`conf`	A 32-mW 40-Gb/s CMOS NRZ transmitter. CICC Yikun Chang, Abishek Manian, Long Kong, Behzad Razavi
2018	J	`jnl`	An 80-Gb/s 44-mW Wireline PAM4 Transmitter. IEEE J. Solid State Circuits Yikun Chang, Abishek Manian, Long Kong, Behzad Razavi
2018	C	`conf`	An Alternative Analysis of Noise Folding in Fractional-N Synthesizers. ISCAS Behzad Razavi
2017	—	`conf`	19.5 A 2.4GHz RF fractional-N synthesizer with 0.25fREF BW. ISSCC Long Kong, Behzad Razavi
2017	J	`jnl`	A 2.4-GHz 6.4-mW Fractional-N Inductorless RF Synthesizer. IEEE J. Solid State Circuits Long Kong, Behzad Razavi
2017	J	`jnl`	A 40-Gb/s 14-mW CMOS Wireline Receiver. IEEE J. Solid State Circuits Abishek Manian, Behzad Razavi
2017	J	`jnl`	Analysis of Second-Order Intermodulation in Miller Bandpass Filters. IEEE Trans. Circuits Syst. II Express Briefs Joung Won Park, Behzad Razavi
2017	J	`jnl`	Introducing Our Sister Publication: IEEE Solid-State Circuits Letters. IEEE J. Solid State Circuits John R. Long, Jan Craninckx, Behzad Razavi
2016	—	`conf`	23.8 A 40Gb/s 14mW CMOS wireline receiver. ISSCC Abishek Manian, Behzad Razavi
2016	J	`jnl`	A 2.4 GHz 4 mW Integer-N Inductorless RF Synthesizer. IEEE J. Solid State Circuits Long Kong, Behzad Razavi
2016	—	`conf`	A 2.4-GHz 6.4-mW fractional-N inductorless RF synthesizer. VLSI Circuits Long Kong, Behzad Razavi
2016	J	`jnl`	On the Stability of Charge-Pump Phase-Locked Loops. IEEE Trans. Circuits Syst. I Regul. Pap. Aliakbar Homayoun, Behzad Razavi
2015	—	`conf`	25.7 A 2.4GHz 4mW inductorless RF synthesizer. ISSCC Long Kong, Behzad Razavi
2015	—	`conf`	A 12-bit 200-MS/s 3.4-mW CMOS ADC with 0.85-V supply. VLSIC Joseph Palackal Mathew, Long Kong, Behzad Razavi
2015	J	`jnl`	A 25 Gb/s 5.8 mW CMOS Equalizer. IEEE J. Solid State Circuits Jun Won Jung, Behzad Razavi
2015	—	`conf`	A 40-Gb/s 9.2-mW CMOS equalizer. VLSIC Abishek Manian, Behzad Razavi
2015	J	`jnl`	A Low-Power CMOS Receiver for 5 GHz WLAN. IEEE J. Solid State Circuits Aliakbar Homayoun, Behzad Razavi
2015	J	`jnl`	An RF Receiver for Intra-Band Carrier Aggregation. IEEE J. Solid State Circuits Sy-Chyuan Hwu, Behzad Razavi
2015	C	`conf`	The future of radios. ISCAS Behzad Razavi
2014	—	`conf`	2.4 A 25Gb/s 5.8mW CMOS equalizer. ISSCC Jun Won Jung, Behzad Razavi
2014	—	`conf`	20.8 A 20mW GSM/WCDMA receiver with RF channel selection. ISSCC Joung Won Park, Behzad Razavi
2014	J	`jnl`	A 10-Bit 800-MHz 19-mW CMOS ADC. IEEE J. Solid State Circuits Shiuh-Hua Wood Chiang, Hyuk Sun, Behzad Razavi
2014	—	`conf`	A 32-Gb/s 9.3-mW CMOS equalizer with 0.73-V supply. CICC Abishek Manian, Behzad Razavi
2014	J	`jnl`	A 7.1 mW 1 GS/s ADC With 48 dB SNDR at Nyquist Rate. IEEE J. Solid State Circuits Sedigheh Hashemi, Behzad Razavi
2014	—	`conf`	A receiver architecture for intra-band carrier aggregation. VLSIC Sy-Chyuan Hwu, Behzad Razavi
2014	J	`jnl`	An 8 Bit 4 GS/s 120 mW CMOS ADC. IEEE J. Solid State Circuits Hegong Wei, Peng Zhang, Bibhudatta Sahoo, Behzad Razavi
2014	J	`jnl`	Analysis of Metastability in Pipelined ADCs. IEEE J. Solid State Circuits Sedigheh Hashemi, Behzad Razavi
2014	J	`jnl`	Channel Selection at RF Using Miller Bandpass Filters. IEEE J. Solid State Circuits Joung Won Park, Behzad Razavi
2014	—	`conf`	Recent developments in RF receivers. CICC Behzad Razavi
2014	J	`jnl`	Relation Between Delay Line Phase Noise and Ring Oscillator Phase Noise. IEEE J. Solid State Circuits Aliakbar Homayoun, Behzad Razavi
2014	—	`conf`	The role of translational circuits in RF receiver design. CICC Behzad Razavi
2013	J	`jnl`	A 10-b 1-GHz 33-mW CMOS ADC. IEEE J. Solid State Circuits Bibhudatta Sahoo, Behzad Razavi
2013	J	`jnl`	A 25-Gb/s 5-mW CMOS CDR/Deserializer. IEEE J. Solid State Circuits Jun Won Jung, Behzad Razavi
2013	—	`conf`	A 5-GHz 11.6-mW CMOS receiver for IEEE 802.11a applications. CICC Aliakbar Homayoun, Behzad Razavi
2013	—	`conf`	A 7.1-mW 1-GS/s ADC with 48-dB SNDR at Nyquist rate. CICC Sedigheh Hashemi, Behzad Razavi
2013	J	`jnl`	A Harmonic-Rejecting CMOS LNA for Broadband Radios. IEEE J. Solid State Circuits Joung Won Park, Behzad Razavi
2013	—	`conf`	An 8-Bit 4-GS/s 120-mW CMOS ADC. CICC Hegong Wei, Peng Zhang, Bibhudatta Sahoo, Behzad Razavi
2013	J	`jnl`	Analysis of Phase Noise in Phase/Frequency Detectors. IEEE Trans. Circuits Syst. I Regul. Pap. Aliakbar Homayoun, Behzad Razavi
2013	—	`conf`	Charge steering: A low-power design paradigm. CICC Behzad Razavi
2013	J	`jnl`	Design Considerations for Interleaved ADCs. IEEE J. Solid State Circuits Behzad Razavi
2012	—	`conf`	A 10-bit 1-GHz 33-mW CMOS ADC. VLSIC Bibhudatta Sahoo, Behzad Razavi
2012	—	`conf`	A 10-bit 1-GS/s CMOS ADC with FOM = 70 fJ/conversion. CICC Sedigheh Hashemi, Behzad Razavi
2012	—	`conf`	A 25-Gb/s 5-mWCMOS CDR/deserializer. VLSIC Jun Won Jung, Behzad Razavi
2012	—	`conf`	A harmonic-rejecting CMOS LNA for broadband radios. VLSIC Joung Won Park, Behzad Razavi
2012	—	`conf`	Problem of timing mismatch in interleaved ADCs. CICC Behzad Razavi
2011	J	`jnl`	A 300-GHz Fundamental Oscillator in 65-nm CMOS Technology. IEEE J. Solid State Circuits Behzad Razavi
2011	—	`conf`	Cellular and wireless LAN transceivers: From systems to circuit design. ISSCC John R. Long, Hooman Darabi, Frank Op't Eynde, Behzad Razavi, Robert Bogdan Staszewski
2011	J	`jnl`	Low-Power CMOS Equalizer Design for 20-Gb/s Systems. IEEE J. Solid State Circuits Sameh A. Ibrahim, Behzad Razavi
2011	J	`jnl`	Transmitter Linearization by Beamforming. IEEE J. Solid State Circuits ChuanKang Liang, Behzad Razavi
2010	—	`conf`	A 20Gb/s 40mW equalizer in 90nm CMOS technology. ISSCC Sameh A. Ibrahim, Behzad Razavi
2010	J	`jnl`	A New DAC Mismatch Shaping Technique for Sigma-Delta Modulators. IEEE Trans. Circuits Syst. II Express Briefs Mohamed Aboudina, Behzad Razavi
2010	—	`conf`	CMOS phase-locked loops for frequency synthesis. ISSCC Ian Galton, Behzad Razavi, John Cowles, Peter R. Kinget
2010	J	`jnl`	Cognitive Radio Design Challenges and Techniques. IEEE J. Solid State Circuits Behzad Razavi
2009	J	`jnl`	A 10-Bit 500-MS/s 55-mW CMOS ADC. IEEE J. Solid State Circuits Ashutosh Verma, Behzad Razavi
2009	—	`conf`	A 10b 500MHz 55mW CMOS ADC. ISSCC Ashutosh Verma, Behzad Razavi
2009	J	`jnl`	A 12-Bit 200-MHz CMOS ADC. IEEE J. Solid State Circuits Bibhudatta Sahoo, Behzad Razavi
2009	J	`jnl`	A New Transceiver Architecture for the 60-GHz Band. IEEE J. Solid State Circuits Ali Parsa, Behzad Razavi
2009	—	`conf`	Challenges in the design of cognitive radios CICC Behzad Razavi
2009	J	`jnl`	Design of Millimeter-Wave CMOS Radios: A Tutorial. IEEE Trans. Circuits Syst. I Regul. Pap. Behzad Razavi
2009	J	`jnl`	Systematic Transistor and Inductor Modeling for Millimeter-Wave Design. IEEE J. Solid State Circuits ChuanKang Liang, Behzad Razavi
2009	J	`jnl`	The Role of PLLs in Future Wireline Transmitters. IEEE Trans. Circuits Syst. I Regul. Pap. Behzad Razavi
2009	—	`conf`	U-PAS: A user-friendly ADC simulator for courses on analog design. MSE Bibhudatta Sahoo, Behzad Razavi
2008	—	`conf`	A 60GHz CMOS Receiver Using a 30GHz LO. ISSCC Ali Parsa, Behzad Razavi
2008	J	`jnl`	A Millimeter-Wave CMOS Heterodyne Receiver With On-Chip LO and Divider. IEEE J. Solid State Circuits Behzad Razavi
2008	J	`jnl`	A Millimeter-Wave Circuit Technique. IEEE J. Solid State Circuits Behzad Razavi
2008	—	`conf`	Phase-locking in wireline systems: Present and future. CICC Behzad Razavi
2007	J	`jnl`	A Receiver Architecture for Dual-Antenna Systems. IEEE J. Solid State Circuits Hamid Rafati, Behzad Razavi
2007	—	`conf`	A mm-Wave CMOS Heterodyne Receiver with On-Chip LO and Divider. ISSCC Behzad Razavi
2007	—	`conf`	An 11b 800MS/s Time-Interleaved ADC with Digital Background Calibration. ISSCC Cheng-Chung Hsu, Fong-Ching Huang, Chih-Yung Shih, Chen-Chih Huang, Ying-Hsi Lin, Chao-Cheng Lee, Behzad Razavi
2007	C	`conf`	CMOS Transceivers at 60 GHz and Beyond1. ISCAS Behzad Razavi
2007	C	`conf`	Design Considerations for Future RF Circuits. ISCAS Behzad Razavi
2007	J	`jnl`	Equalization and Clock and Data Recovery Techniques for 10-Gb/s CMOS Serial-Link Receivers. IEEE J. Solid State Circuits Srikanth Gondi, Behzad Razavi
2007	—	`conf`	Heterodyne Phase Locking: A Technique for High-Frequency Division. ISSCC Behzad Razavi
2007	J	`jnl`	Heterodyne Phase Locking: A Technique for High-Speed Frequency Division. IEEE J. Solid State Circuits Behzad Razavi
2006	J	`jnl`	A 60-GHz CMOS receiver front-end. IEEE J. Solid State Circuits Behzad Razavi
2006	—	`conf`	A Fully Integrated UWB PHY in 0.13µm CMOS. ISSCC Turgut Aytur, Han-Chang Kang, Ravishankar H. Mahadevappa, Mustafa Altintas, Stephan ten Brink, Thanh Diep, Cheng-Chung Hsu, Feng Shi, Fei-Ran Yang, Chao-Cheng Lee, Ran-Hong Yan, Behzad Razavi
2006	—	`conf`	Frequency-Based Measurement of Mismatches Between Small Capacitors. CICC Ashutosh Verma, Behzad Razavi
2006	—	`conf`	Modeling Op Amp Nonlinearity in Switched-Capacitor Sigma-Delta Modulators. CICC Khaled Abdelfattah, Behzad Razavi
2006	—	`conf`	Mutual Injection Pulling Between Oscillators. CICC Behzad Razavi
2005	J	`jnl`	A UWB CMOS transceiver. IEEE J. Solid State Circuits Behzad Razavi, Turgut Aytur, Christopher Lam, Fei-Ran Yang, Kuang-Yu (Jason) Li, Ran-Hong (Ran) Yan, Han-Chang Kang, Cheng-Chung Hsu, Chao-Cheng Lee
2005	—	`conf`	A comparison of electrical and optical clock networks in nanometer technologies. CICC Bryan D. Ackland, Behzad Razavi, Larry West
2005	—	`conf`	A new receiver architecture for multiple-antenna systems. CICC Hamid Rafati, Behzad Razavi
2005	J	`jnl`	A single-chip dual-band direct-conversion IEEE 802.11a/b/g WLAN transceiver in 0.18-μm CMOS. IEEE J. Solid State Circuits Pengfei Zhang, Lawrence Der, Dawei Guo, Isaac Sever, Taoufik Bourdi, Christopher Lam, Alireza Zolfaghari, Jess Chen, Douglas Gambetta, Baohong Cheng, Sujatha Gowder, Siegfried Hart, Lam Huynh, Thai Nguyen, Behzad Razavi
2005	J	`jnl`	Correction to "A 40-Gb/s Clock and Data Recovery Circuit in 0.18μm CMOS Technology". IEEE J. Solid State Circuits Jri Lee, Behzad Razavi
2005	—	`conf`	Multiband UWB transceivers. CICC Behzad Razavi, Turgut Aytur, Christopher Lam, Fei-Ran Yang, Ran-Hong Yan, Han-Chang Kang, Cheng-Chung Hsu, Chao-Cheng Lee
2005	—	`conf`	Will continued process-node shrinks kill high-performance analog design? CICC Jafar Savoj, David Rich, Brett Forejt, Peter R. Kinget, Un-Ku Moon, Modest M. Oprysko, Behzad Razavi, Hisashi (Sam) Shichijo, Albert Z. Wang
2004	J	`jnl`	40-Gb/s amplifier and ESD protection circuit in 0.18-μm CMOS technology. IEEE J. Solid State Circuits Sherif Galal, Behzad Razavi
2004	J	`jnl`	A 40-GHz frequency divider in 0.18-μm CMOS technology. IEEE J. Solid State Circuits Jri Lee, Behzad Razavi
2004	—	`conf`	A CMOS direct-conversion transceiver for IEEE 802.11a/b/g WLANs. CICC Pengfei Zhang, Lawrence Der, Dawei Guo, Isaac Sever, Taoufik Bourdi, Chris Lam, Alireza Zolfaghari, Jess Chen, Douglas Gambetta, Baohong Cheng, Sujatha Gower, Siegfi Hart, Lam Huynh, Thai Nguyen, Behzad Razavi
2004	J	`jnl`	A study of injection locking and pulling in oscillators. IEEE J. Solid State Circuits Behzad Razavi
2004	J	`jnl`	Analysis and modeling of bang-bang clock and data recovery circuits. IEEE J. Solid State Circuits Jri Lee, Kenneth S. Kundert, Behzad Razavi
2003	J	`jnl`	10-Gb/s limiting amplifier and laser/modulator driver in 0.18-μm CMOS technology. IEEE J. Solid State Circuits Sherif Galal, Behzad Razavi
2003	J	`jnl`	A 10-Gb/s CMOS clock and data recovery circuit with a half-rate binary phase/frequency detector. IEEE J. Solid State Circuits Jafar Savoj, Behzad Razavi
2003	J	`jnl`	A 2-GHz CMOS image-reject receiver with LMS calibration. IEEE J. Solid State Circuits Lawrence Der, Behzad Razavi
2003	J	`jnl`	A 40-Gb/s clock and data recovery circuit in 0.18-μm CMOS technology. IEEE J. Solid State Circuits Jri Lee, Behzad Razavi
2003	J	`jnl`	A 5-GHz direct-conversion CMOS transceiver. IEEE J. Solid State Circuits Pengfei Zhang, Thai Nguyen, Christopher Lam, Douglas Gambetta, Theerachet Soorapanth, Baohong Cheng, Siegfried Hart, Isaac Sever, Taoufik Bourdi, Andrew (KhongMeng) Tham, Behzad Razavi
2003	J	`jnl`	A low-power 2.4-GHz transmitter/receiver CMOS IC. IEEE J. Solid State Circuits Alireza Zolfaghari, Behzad Razavi
2003	J	`jnl`	A stabilization technique for phase-locked frequency synthesizers. IEEE J. Solid State Circuits Tai-Cheng Lee, Behzad Razavi
2003	—	`conf`	A study of injection pulling and locking in oscillators. CICC Behzad Razavi
2003	J	`jnl`	Broadband ESD protection circuits in CMOS technology. IEEE J. Solid State Circuits Sherif Galal, Behzad Razavi
2003	—	`conf`	Modeling of jitter in bang-bang clock and data recovery circuits. CICC Jri Lee, Kenneth S. Kundert, Behzad Razavi
2003	J	`jnl`	RF CMOS transceivers for cellular telephony. IEEE Commun. Mag. Behzad Razavi
2002	—	`conf`	A noninvasive channel-select filter for a CMOS Bluetooth receiver. CICC Alireza Zolfaghari, Behzad Razavi
2002	J	`jnl`	Challenges in the design of high-speed clock and data recovery circuits. IEEE Commun. Mag. Behzad Razavi
2002	J	`jnl`	Prospects of CMOS technology for high-speed optical communication circuits. IEEE J. Solid State Circuits Behzad Razavi
2002	—	`conf`	The role of monolithic transmission lines in high-speed integrated circuits. CICC Behzad Razavi
2001	J	`jnl`	A 10-Gb/s CMOS clock and data recovery circuit with a half-rate linear phase detector. IEEE J. Solid State Circuits Jafar Savoj, Behzad Razavi
2001	—	`conf`	A 125-MHz CMOS mixed-signal equalizer for Gigabit Ethernet on copper wire. CICC Tai-Cheng Lee, Behzad Razavi
2001	J	`jnl`	A 125-MHz mixed-signal echo canceller for Gigabit Ethernet on copper wire. IEEE J. Solid State Circuits Tai-Cheng Lee, Behzad Razavi
2001	J	`jnl`	A 5.2-GHz CMOS receiver with 62-dB image rejection. IEEE J. Solid State Circuits Behzad Razavi
2001	J	`jnl`	A CMOS clock recovery circuit for 2.5-Gb/s NRZ data. IEEE J. Solid State Circuits Seema Butala Anand, Behzad Razavi
2001	A*	`conf`	Design of Half-Rate Clock and Data Recovery Circuits for Optical Communication Systems. DAC Jafar Savoj, Behzad Razavi
2001	—	`conf`	Design of high-speed circuits for optical communication systems. CICC Behzad Razavi
2001	J	`jnl`	Stacked inductors and transformers in CMOS technology. IEEE J. Solid State Circuits Alireza Zolfaghari, Andrew Chan, Behzad Razavi
2000	—	`conf`	A 2.5-Gb/s clock recovery circuit for NRZ data in 0.4-μm CMOS technology. CICC Seema Butala Anand, Behzad Razavi
2000	J	`jnl`	A 2.6-GHz/5.2-GHz frequency synthesizer in 0.4-μm CMOS technology. IEEE J. Solid State Circuits Christopher Lam, Behzad Razavi
2000	—	`conf`	A 4-tap 125-MHz mixed-signal echo canceller for Gigabit Ethernet on copper wire. CICC Tai-Cheng Lee, Behzad Razavi
2000	J	`jnl`	An 8-bit 150-MHz CMOS A/D converter. IEEE J. Solid State Circuits Yun-Ti Wang, Behzad Razavi
2000	—	`conf`	Stacked inductors and 1-to-2 transformers in CMOS technology. CICC Alireza Zolfaghari, Andrew Chan, Behzad Razavi
1999	J	`jnl`	A 2.4-GHz CMOS receiver for IEEE 802.11 wireless LANs. IEEE J. Solid State Circuits Behzad Razavi
1999	J	`jnl`	A 900-MHz/1.8-GHz CMOS transmitter for dual-band applications. IEEE J. Solid State Circuits Behzad Razavi
1999	—	`conf`	An 8-bit 150-MHz CMOS A/D converter. CICC Yun-Ti Wang, Behzad Razavi
1999	J	`jnl`	CMOS technology characterization for analog and RF design. IEEE J. Solid State Circuits Behzad Razavi
1999	—	`conf`	RF transmitter architectures and circuits. CICC Behzad Razavi
1998	J	`jnl`	A 900-MHz/1.8-GHz CMOS receiver for dual-band applications. IEEE J. Solid State Circuits Stephen Wu, Behzad Razavi
1998	—	`conf`	Architectures and circuits for RF CMOS receivers. CICC Behzad Razavi
1998	—	`conf`	CMOS technology characterization for analog and RF design. CICC Behzad Razavi
1998	—	`conf`	Oscillator jitter due to supply and substrate noise. CICC Frank Herzel, Behzad Razavi
1998	A*	`conf`	RF IC Design Challenges. DAC Behzad Razavi
1997	J	`jnl`	A 2-GHz 1.6-mW phase-locked loop. IEEE J. Solid State Circuits Behzad Razavi
1997	—	`conf`	Next-Generation RF Circuits and Systems. ARVLSI Behzad Razavi
1997	J	`jnl`	Recent advances in RF integrated circuits. IEEE Commun. Mag. Behzad Razavi
1996	J	`jnl`	A 2.5-Gb/s 15-mW clock recovery circuit. IEEE J. Solid State Circuits Behzad Razavi
1996	J	`jnl`	A study of phase noise in CMOS oscillators. IEEE J. Solid State Circuits Behzad Razavi
1995	J	`jnl`	A 2-GHz, 6-mW BiCMOS frequency synthesizer. IEEE J. Solid State Circuits Turgut Aytur, Behzad Razavi
1995	J	`jnl`	A 200-MHz 15-mW BiCMOS sample-and-hold amplifier with 3 V supply. IEEE J. Solid State Circuits Behzad Razavi
1995	J	`jnl`	Design of a 100-MHz 10-mW 3-V sample-and-hold amplifier in digital bipolar technology. IEEE J. Solid State Circuits Behzad Razavi
1995	J	`jnl`	Design of high-speed, low-power frequency dividers and phase-locked loops in deep submicron CMOS. IEEE J. Solid State Circuits Behzad Razavi, Kwing F. Lee, Ran H. Yan
1994	J	`jnl`	A 6 GHz 68 mW BiCMOS phase-locked loop. IEEE J. Solid State Circuits Behzad Razavi, JanMye James Sung
1994	J	`jnl`	Design techniques for low-voltage high-speed digital bipolar circuits. IEEE J. Solid State Circuits Behzad Razavi, Yusuke Ota, Robert G. Swartz
1992	J	`jnl`	A 12-b 5-Msample/s two-step CMOS A/D converter. IEEE J. Solid State Circuits Behzad Razavi, Bruce A. Wooley
1992	J	`jnl`	Design techniques for high-speed, high-resolution comparators. IEEE J. Solid State Circuits Behzad Razavi, Bruce A. Wooley