Behzad Mesgarzadeh

25 papers B 1C 5Journal 6Unranked 12

Year	Rank	Type	Title / Venue / Authors
2015	J	`jnl`	Monte Carlo-Free Prediction of Spurious Performance for ECDLL-Based Synthesizers. IEEE Trans. Circuits Syst. I Regul. Pap. Amin Ojani, Behzad Mesgarzadeh, Atila Alvandpour
2014	—	`conf`	A low-power direct IQ upconversion technique based on duty-cycled multi-phase sub-harmonic passive mixers for UWB transmitters. ISIC Amin Ojani, Behzad Mesgarzadeh, Atila Alvandpour
2014	—	`conf`	A self-calibration technique for fast-switching frequency-hopped UWB synthesis. MIXDES Amin Ojani, Behzad Mesgarzadeh, Atila Alvandpour
2014	J	`jnl`	Modeling and Analysis of Harmonic Spurs in DLL-Based Frequency Synthesizers. IEEE Trans. Circuits Syst. I Regul. Pap. Amin Ojani, Behzad Mesgarzadeh, Atila Alvandpour
2014	J	`jnl`	Simultaneous switching noise reduction by resonant clock distribution networks. Integr. Behzad Mesgarzadeh
2013	C	`conf`	A quadrature UWB frequency synthesizer with dynamic settling-time calibration. ISCAS Amin Ojani, Behzad Mesgarzadeh, Atila Alvandpour
2013	J	`jnl`	An 8-GS/s 200-MHz Bandwidth 68-mW ΔΣ DAC in 65-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs Ameya Bhide, Omid Esmailzadeh Najari, Behzad Mesgarzadeh, Atila Alvandpour
2012	—	`conf`	A Class-D stage with harmonic suppression and DLL-based phase generation. MWSCAS Jonas Fritzin, Behzad Mesgarzadeh, Atila Alvandpour
2012	C	`conf`	A DLL-based injection-locked frequency synthesizer for WiMedia UWB. ISCAS Amin Ojani, Behzad Mesgarzadeh, Atila Alvandpour
2012	—	`conf`	A process variation tolerant DLL-based UWB frequency synthesizer. MWSCAS Amin Ojani, Behzad Mesgarzadeh, Atila Alvandpour
2012	C	`conf`	Reliability challenges in avionics due to silicon aging. DDECS Behzad Mesgarzadeh, Ingemar Söderquist, Atila Alvandpour
2011	—	`conf`	A multi-segment clocking scheme to reduce on-chip EMI. SoCC Behzad Mesgarzadeh, Iman Esmaeil Zadeh, Atila Alvandpour
2010	C	`conf`	EMI reduction by resonant clock distribution networks. ISCAS Behzad Mesgarzadeh, Atila Alvandpour
2009	J	`jnl`	A Low-Power Digital DLL-Based Clock Generator in Open-Loop Mode. IEEE J. Solid State Circuits Behzad Mesgarzadeh, Atila Alvandpour
2008	—	`conf`	A 2-GHz 7-mW digital DLL-based frequency multiplier in 90-nm CMOS. ESSCIRC Behzad Mesgarzadeh, Atila Alvandpour
2008	—	`—`	Low-Power Low-Jitter Clock Generation and Distribution. Behzad Mesgarzadeh
2007	J	`jnl`	Jitter Characteristic in Charge Recovery Resonant Clock Distribution. IEEE J. Solid State Circuits Behzad Mesgarzadeh, Martin Hansson, Atila Alvandpour
2006	—	`conf`	1.56 GHz On-chip Resonant Clocking in 130nm CMOS. CICC Martin Hansson, Behzad Mesgarzadeh, Atila Alvandpour
2006	—	`conf`	A 24-mW 0.02-mm2 1.5-GHz DLL-Based Frequency Multiplier in 130-nm CMOS. SoCC Behzad Mesgarzadeh, Atila Alvandpour
2006	C	`conf`	A wide-tuning range 1.8 GHz quadrature VCO utilizing coupled ring oscillators. ISCAS Behzad Mesgarzadeh, Atila Alvandpour
2006	—	`conf`	First-Harmonic Injection-Locked Ring Oscillators. CICC Behzad Mesgarzadeh, Atila Alvandpour
2005	—	`conf`	A study of injection locking in ring oscillators. ISCAS (6) Behzad Mesgarzadeh, Atila Alvandpour
2005	—	`conf`	Synchronous latency-insensitive design for multiple clock domain. SoCC Anders Edman, Christer Svensson, Behzad Mesgarzadeh
2004	B	`conf`	A CMOS implementation of current-mode min-max circuits and a sample fuzzy application. FUZZ-IEEE Behzad Mesgarzadeh
2004	—	`conf`	A new mesochronous clocking scheme for synchronization in SoC. ISCAS (2) Behzad Mesgarzadeh, Christer Svensson, Atila Alvandpour