Bastien Giraud

55 papers A 7C 12Journal 11Unranked 25

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	A Dataset Generation Toolbox for Dynamic Security Assessment: On the Role of the Security Boundary. CoRR Bastien Giraud, Lola Charles, Agnes Marjorie Nakiganda, Johanna Vorwerk, Spyros Chatzivasileiadis
2025	C	`conf`	Improving Error Correction with Weak-Bit Information in Resistive Memories. IOLTS Valentin Gherman, Giuseppe Piccolboni, Zeev Freidin, Matan Guttman, Amir Regev, Gabriel Molas, Ishai Naveh, Bastien Giraud, Antoine Hebert, Ilan Sever
2025	J	`jnl`	Neural Networks for AC Optimal Power Flow: Improving Worst-Case Guarantees during Training. CoRR Bastien Giraud, Rahul Nellikath, Johanna Vorwerk, Maad Alowaifeer, Spyros Chatzivasileiadis
2025	—	`conf`	Relaxation-Aware Programming in RRAM: Evaluating and Optimizing Write Termination. IMW M. Correa Cueto, Bastien Giraud, M. Drouard, Giuseppe Piccolboni, Gabriel Molas, Gaël Pillonnet
2024	C	`conf`	A Novel Design Technique for Enhanced Security and New Applications of Ferroelectric-Based Non-Volatile SRAM. VLSI-SoC Lucas Rhetat, Jean-Philippe Noel, Bastien Giraud, Laurent Grenouillet, Julie Laguerre, Cédric Marchand, Ian O'Connor
2024	—	`conf`	Scalable Design Techniques for Expanding Ferroelectric-Based Non-volatile SRAMs Applications. VLSI-SoC (Selected Papers) Lucas Rhetat, Jean-Philippe Noel, Bastien Giraud, Laurent Grenouillet, Julie Laguerre, Cédric Marchand, Ian O'Connor
2024	J	`jnl`	Smart Write Algorithm to Enhance Performances and Reliability of an RRAM Macro. IEEE J. Solid State Circuits Bastien Giraud, Sebastien Ricavy, Cyrille Laffond, Ilan Sever, Valentin Gherman, Florent Lepin, Mariam Diallo, Khadija Zenati, Sylvain Dumas, Olivier Guille, Maxim Vershkov, Alessandro Bricalli, Giuseppe Piccolboni, Jean-Philippe Noel, Anass Samir, Gaël Pillonnet, Yvain Thonnart, Gabriel Molas
2023	—	`conf`	Benefits of Design Assist Techniques on Performances and Reliability of a RRAM Macro. IMW Bastien Giraud, Sebastien Ricavy, Yasser Moursy, Cyrille Laffond, Ilan Sever, Valentin Gherman, Manuel Pezzin, Florent Lepin, Mariam Diallo, Khadija Zenati, Sylvain Dumas, Maxim Vershkov, Alessandro Bricalli, Giuseppe Piccolboni, Jean-Philippe Noël, Anass Samir, Gaël Pillonnet, Yvain Thonnart, Gabriel Molas
2023	A	`conf`	Binary ReRAM-based BNN first-layer implementation. DATE Mona Ezzadeen, Atreya Majumdar, Sigrid Thomas, Jean-Philippe Noël, Bastien Giraud, Marc Bocquet, François Andrieu, Damien Querlioz, Jean-Michel Portal
2023	C	`conf`	Compute-In-Place Serial FeRAM: Enhancing Performance, Efficiency and Adaptability in Critical Embedded Systems. VLSI-SoC Jean-Philippe Noël, Emanuele Valea, Laurent Grenouillet, B. Chapuis, Clément Fisher, A. Recoquillay, Bastien Giraud
2022	—	`conf`	An Automated Design Methodology for Computational SRAM Dedicated to Highly Data-Centric Applications: Invited Paper. SLIP A. Philippe, Lorenzo Ciampolini, M. Gerbaud, M. Ramirez-Corrales, Valentin Egloff, Bastien Giraud, Jean-Philippe Noël
2022	—	`conf`	Experimental demonstration of Single-Level and Multi-Level-Cell RRAM-based In-Memory Computing with up to 16 parallel operations. IRPS Eduardo Esmanhotto, Tifenn Hirtzlin, Niccolo Castellani, S. Martin, Bastien Giraud, François Andrieu, Jean-François Nodin, Damien Querlioz, Jean-Michel Portal, Elisa Vianello
2022	J	`jnl`	Experimental demonstration of Single-Level and Multi-Level-Cell RRAM-based In-Memory Computing with up to 16 parallel operations. CoRR Eduardo Esmanhotto, Tifenn Hirtzlin, Niccolo Castellani, S. Martin, Bastien Giraud, François Andrieu, Jean-Francois Nodin, Damien Querlioz, Jean-Michel Portal, Elisa Vianello
2022	J	`jnl`	Towards a Truly Integrated Vector Processing Unit for Memory-bound Applications Based on a Cost-competitive Computational SRAM Design Solution. ACM J. Emerg. Technol. Comput. Syst. Maha Kooli, Antoine Heraud, Henri-Pierre Charles, Bastien Giraud, Roman Gauchi, Mona Ezzadeen, Kevin Mambu, Valentin Egloff, Jean-Philippe Noel
2021	—	`conf`	A Near-Instantaneous and Non-Invasive Erasure Design Technique to Protect Sensitive Data Stored in Secure SRAMs. ESSCIRC Jean-Philippe Noel, Manuel Pezzin, Jean-Frédéric Christmann, Lorenzo Ciampolini, M. Le Coadou, M. Diallo, Florent Lepin, B. Blampey, Simone Bacles-Min, R. Wacquez, Bastien Giraud
2021	—	`conf`	A Regulated Sensing Solution Based on a Self-reference Principle for PCM + OTS Memory Array. VLSI-SoC (Selected Papers) J. Gasquez, Bastien Giraud, P. Boivin, Y. Moustapha-Rabault, Vincenzo Della Marca, Jean-Michel Walder, Jean-Michel Portal
2021	C	`conf`	A Self-referenced and regulated sensing solution for PCM with OTS selector. VLSI-SoC J. Gasquez, Bastien Giraud, P. Boivin, Y. Moustapha-Rabault, Vincenzo Della Marca, Jean-Pierre Walder, Jean-Michel Portal
2021	—	`conf`	Low-Overhead Implementation of Binarized Neural Networks Employing Robust 2T2R Resistive RAM Bridges. ESSCIRC Mona Ezzadeen, Atreya Majumdar, Marc Bocquet, Bastien Giraud, Jean-Philippe Noël, François Andrieu, Damien Querlioz, Jean-Michel Portal
2021	—	`conf`	Low-Overhead Implementation of Binarized Neural Networks Employing Robust 2T2R Resistive RAM Bridges. ESSDERC Mona Ezzadeen, Atreya Majumdar, Marc Bocquet, Bastien Giraud, Jean-Philippe Noël, François Andrieu, Damien Querlioz, Jean-Michel Portal
2021	A	`conf`	Storage Class Memory with Computing Row Buffer: A Design Space Exploration. DATE Valentin Egloff, Jean-Philippe Noel, Maha Kooli, Bastien Giraud, Lorenzo Ciampolini, Roman Gauchi, César Fuguet Tortolero, Eric Guthmuller, Mathieu Moreau, Jean-Michel Portal
2020	A	`conf`	Binary Linear ECCs Optimized for Bit Inversion in Memories with Asymmetric Error Probabilities. DATE Valentin Gherman, Samuel Evain, Bastien Giraud
2020	A	`conf`	Computational SRAM Design Automation using Pushed-Rule Bitcells for Energy-Efficient Vector Processing. DATE Jean-Philippe Noël, Valentin Egloff, Maha Kooli, Roman Gauchi, Jean-Michel Portal, Henri-Pierre Charles, Pascal Vivet, Bastien Giraud
2020	A	`conf`	Reconfigurable tiles of computing-in-memory SRAM architecture for scalable vectorization. ISLPED Roman Gauchi, Valentin Egloff, Maha Kooli, Jean-Philippe Noël, Bastien Giraud, Pascal Vivet, Subhasish Mitra, Henri-Pierre Charles
2020	J	`jnl`	Ultra-High-density 3D vertical RRAM with stacked JunctionLess nanowires for In-Memory-Computing applications. CoRR Mona Ezzadeen, D. Bosch, Bastien Giraud, Sylvain Barraud, Jean-Philippe Noël, Didier Lattard, Joris Lacord, Jean-Michel Portal, François Andrieu
2019	—	`conf`	RRAMSpec: A Design Space Exploration Framework for High Density Resistive RAM. SAMOS Deepak M. Mathew, André Lucas Chinazzo, Christian Weis, Matthias Jung, Bastien Giraud, Pascal Vivet, Alexandre Levisse, Norbert Wehn
2018	—	`conf`	Energy-Efficient 4T SRAM Bitcell with 2T Read-Port for Ultra-Low-Voltage Operations in 28 nm 3D Monolithic CoolCubeTM Technology. NANOARCH Reda Boumchedda, Jean-Philippe Noel, Bastien Giraud, Adam Makosiej, Marco Antonio Rios, Eduardo Esmanhotto, Emilien Bourde-Cicé, Mathis Bellet, David Turgis, Edith Beigné
2018	J	`jnl`	Experimental Investigation of 4-kb RRAM Arrays Programming Conditions Suitable for TCAM. IEEE Trans. Very Large Scale Integr. Syst. Alessandro Grossi, Elisa Vianello, Cristian Zambelli, Pablo Royer, Jean-Philippe Noel, Bastien Giraud, Luca Perniola, Piero Olivo, Etienne Nowak
2018	C	`conf`	Prospects for energy-efficient edge computing with integrated HfO2-based ferroelectric devices. VLSI-SoC Ian O'Connor, Mayeul Cantan, Cédric Marchand, Bertrand Vilquin, Stefan Slesazeck, Evelyn T. Breyer, Halid Mulaosmanovic, Thomas Mikolajick, Bastien Giraud, Jean-Philippe Noel, Adrian M. Ionescu, Igor Stolichnov
2018	—	`conf`	RRAM Crossbar Arrays for Storage Class Memory Applications: Throughput and Density Considerations. DCIS Alexandre Levisse, Bastien Giraud, Jean-Philippe Noël, Mathieu Moreau, Jean-Michel Portal
2018	C	`conf`	Reliable ReRAM-based Logic Operations for Computing in Memory. VLSI-SoC Mathieu Moreau, Eloi Muhr, Marc Bocquet, Hassen Aziza, Jean-Michel Portal, Bastien Giraud, Jean-Philippe Noel
2018	A	`conf`	Smart instruction codes for in-memory computing architectures compatible with standard SRAM interfaces. DATE Maha Kooli, Henri-Pierre Charles, Clément Touzet, Bastien Giraud, Jean-Philippe Noel
2017	J	`jnl`	A 32 kb 0.35-1.2 V, 50 MHz-2.5 GHz Bit-Interleaved SRAM With 8 T SRAM Cell and Data Dependent Write Assist in 28-nm UTBB-FDSOI CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. Anuj Grover, G. S. Visweswaran, Chittoor R. Parthasarathy, Mohammad Daud, David Turgis, Bastien Giraud, Jean-Philippe Noel, Ivan Miro Panades, Guillaume Moritz, Edith Beigné, Philippe Flatresse, Promod Kumar, Shamsi Azmi
2017	—	`conf`	Architecture, design and technology guidelines for crosspoint memories. NANOARCH Alexandre Levisse, Pablo Royer, Bastien Giraud, Jean-Philippe Noël, Mathieu Moreau, Jean-Michel Portal
2017	C	`conf`	Design methodology for area and energy efficient OxRAM-based non-volatile flip-flop. ISCAS Mahesh Nataraj, Alexandre Levisse, Bastien Giraud, Jean-Philippe Noël, Pascal Andreas Meinerzhagen, Jean-Michel Portal, Pierre-Emmanuel Gaillardon
2017	—	`conf`	High density emerging resistive memories: What are the limits? LASCAS Alexandre Levisse, Bastien Giraud, Jean-Philippe Noël, Mathieu Moreau, Jean-Michel Portal
2017	J	`jnl`	High-Density 4T SRAM Bitcell in 14-nm 3-D CoolCube Technology Exploiting Assist Techniques. IEEE Trans. Very Large Scale Integr. Syst. Reda Boumchedda, Jean-Philippe Noel, Bastien Giraud, Kaya Can Akyel, Melanie Brocard, David Turgis, Edith Beigné
2017	C	`conf`	Software platform dedicated for in-memory computing circuit evaluation. RSP Maha Kooli, Henri-Pierre Charles, Clément Touzet, Bastien Giraud, Jean-Philippe Noël
2016	—	`conf`	Capacitor based SneakPath compensation circuit for transistor-less ReRAM architectures. NANOARCH Alexandre Levisse, Bastien Giraud, Jean-Philippe Noel, Mathieu Moreau, Jean-Michel Portal
2016	—	`conf`	DRC ICRC Kaya Can Akyel, Henri-Pierre Charles, Julien Mottin, Bastien Giraud, Gregory Suraci, Sébastien Thuries, Jean-Philippe Noel
2015	J	`jnl`	A 460 MHz at 397 mV, 2.6 GHz at 1.3 V, 32 bits VLIW DSP Embedding F MAX Tracking. IEEE J. Solid State Circuits Edith Beigné, Alexandre Valentian, Ivan Miro Panades, Robin Wilson, Philippe Flatresse, Fady Abouzeid, Thomas Benoist, Christian Bernard, Sebastien Bernard, Olivier Billoint, Sylvain Clerc, Bastien Giraud, Anuj Grover, Julien Le Coz, Jean-Philippe Noel, Olivier Thomas, Yvain Thonnart
2015	—	`conf`	Low Standby Power Capacitively Coupled Sense Amplifier for wide voltage range operation of dual rail SRAMs. ICICDT Anuj Grover, Promod Kumar, Mohammad Daud, G. S. Visweswaran, Chittoor R. Parthasarathy, Jean-Philippe Noel, David Turgis, Bastien Giraud, Guillaume Moritz
2015	—	`conf`	SneakPath compensation circuit for programming and read operations in RRAM-based CrossPoint architectures. NVMTS Alexandre Levisse, Bastien Giraud, Jean-Philippe Noël, Mathieu Moreau, Jean-Michel Portal
2014	—	`conf`	27.1 A 460MHz at 397mV, 2.6GHz at 1.3V, 32b VLIW DSP, embedding FMAX tracking. ISSCC Robin Wilson, Edith Beigné, Philippe Flatresse, Alexandre Valentian, Fady Abouzeid, Thomas Benoist, Christian Bernard, Sebastien Bernard, Olivier Billoint, Sylvain Clerc, Bastien Giraud, Anuj Grover, Julien Le Coz, Ivan Miro Panades, Jean-Philippe Noël, Bertrand Pelloux-Prayer, Philippe Roche, Olivier Thomas, Yvain Thonnart, David Turgis, Fabien Clermidy, Philippe Magarshack
2013	C	`conf`	Fine grain multi-VT co-integration methodology in UTBB FD-SOI technology. VLSI-SoC Bertrand Pelloux-Prayer, Alexandre Valentian, Bastien Giraud, Yvain Thonnart, Jean-Philippe Noel, Philippe Flatresse, Edith Beigné
2013	—	`conf`	Optimization of a voltage sense amplifier operating in ultra wide voltage range with back bias design techniques in 28nm UTBB FD-SOI technology. ICICDT Guillaume Moritz, Bastien Giraud, Jean-Philippe Noel, David Turgis, Anuj Grover
2013	—	`conf`	Ultra-wide body-bias range LDPC decoder in 28nm UTBB FDSOI technology. ISSCC Philippe Flatresse, Bastien Giraud, Jean-Philippe Noel, Bertrand Pelloux-Prayer, Fabien Giner, Deepak-Kumar Arora, Franck Arnaud, Nicolas Planes, Julien Le Coz, Olivier Thomas, Sylvain Engels, Giorgio Cesana, Robin Wilson, Pascal Urard
2013	A	`conf`	Ultra-wide voltage range designs in fully-depleted silicon-on-insulator FETs. DATE Edith Beigné, Alexandre Valentian, Bastien Giraud, Olivier Thomas, Thomas Benoist, Yvain Thonnart, Serge Bernard, Guillaume Moritz, Olivier Billoint, Y. Maneglia, Philippe Flatresse, Jean-Philippe Noel, Fady Abouzeid, Bertrand Pelloux-Prayer, Anuj Grover, Sylvain Clerc, Philippe Roche, Julien Le Coz, Sylvain Engels, Robin Wilson
2011	J	`jnl`	Technology Variability From a Design Perspective. IEEE Trans. Circuits Syst. I Regul. Pap. Borivoje Nikolic, Ji-Hoon Park, Jaehwa Kwak, Bastien Giraud, Zheng Guo, Liang-Teck Pang, Seng Oon Toh, Ruzica Jevtic, Kun Qian, Costas J. Spanos
2010	—	`conf`	An Innovative 6T Hybrid SRAM Cell in sub-32 nm Double-Gate MOS Technology. DELTA Amara Amara, Bastien Giraud, Olivier Thomas
2010	—	`conf`	Technology variability from a design perspective. CICC Borivoje Nikolic, Bastien Giraud, Zheng Guo, Liang-Teck Pang, Ji-Hoon Park, Seng Oon Toh
2009	C	`conf`	SRAM Voltage and Current Sense Amplifiers in sub-32nm Double-gate CMOS Insensitive to Process Variations and Transistor Mismatch. ISCAS Piotr Nasalski, Adam Makosiej, Bastien Giraud, Andrei Vladimirescu, Amara Amara
2008	C	`conf`	A novel 4T asymmetric single-ended SRAM cell in sub-32 nm double gate technology. ISCAS Bastien Giraud, Amara Amara
2008	—	`conf`	An innovative sub-32nm SRAM voltage sense amplifier in double-gate CMOS insensitive to process variations and transistor mismatch. ICECS Piotr Nasalski, Adam Makosiej, Bastien Giraud, Andrei Vladimirescu, Amara Amara
2008	—	`conf`	Read Stability and Write Ability Tradeoff for 6T SRAM Cells in Double-Gate CMOS. DELTA Bastien Giraud, Amara Amara
2007	C	`conf`	A Comparative Study of 6T and 4T SRAM Cells in Double-Gate CMOS with Statistical Variation. ISCAS Bastien Giraud, Amara Amara, Andrei Vladimirescu