Basavaraj Talawar

36 papers Misc 1Journal 18Unranked 17
YearRankTypeTitle / Venue / Authors
2026 J jnl
Ultra-Fast and Accurate Estimation of Large-Scale and Multi-Level Mesh-Based On-Chip Architectures Using Machine Learning and Multiprocessing.
IEEE Access
Anil Kumar, Basavaraj Talawar, S. Mahadevi
2024 J jnl
A Detailed Study of SOT-MRAM as an Alternative to DRAM Primary Memory in Multi-Core Environment.
IEEE Access
H. D. Kallinatha, Sadhana Rai, Basavaraj Talawar
2024 — conf
History aware interference distance based Page replacement policy for Hybrid Memory.
HIPCW
Sadhana Rai, Basavaraj Talawar
2024 — conf
Object Detection for Autonomous Vehicles in Adverse Weather and Varying Lighting Conditions Using a Hybrid YOLO Approach.
HIPCW
Saritha A N, Basavaraj Talawar
2024 — conf
ViTFuser: Advancements in Global Context Understanding for Autonomous Vehicles.
MIND (1)
Atanu Chatterjee, P. Ajay Vikram, Aniketh Narayan Bellala, T. Naga Tarun, Basavaraj Talawar, M. Vani, Jeny Rajan
2022 J jnl
Knowledgeable network-on-chip accelerator for fast and accurate simulations using supervised learning algorithms and multiprocessing.
Int. J. Intell. Eng. Informatics
Anil Kumar, Basavaraj Talawar
2022 J jnl
LBF-NoC: Learning-Based Framework to Predict Performance, Power and Area for Network-On-Chip Architectures.
J. Circuits Syst. Comput.
Anil Kumar, Basavaraj Talawar
2021 J jnl
FPGA friendly NoC simulation acceleration framework employing the hard blocks.
Computing
Prabhu B. M. Prasad, Khyamling Parane, Basavaraj Talawar
2021 J jnl
Parallel Version of Local Search Heuristic Algorithm to Solve Capacitated Vehicle Routing Problem.
Clust. Comput.
Pramod Yelmewad, Basavaraj Talawar
2021 J jnl
Parallel deterministic local search heuristic for minimum latency problem.
Clust. Comput.
Pramod Yelmewad, Basavaraj Talawar
2020 J jnl
An Efficient FPGA-Based Network-on-Chip Simulation Framework Utilizing the Hard Blocks.
Circuits Syst. Signal Process.
Prabhu B. M. Prasad, Khyamling Parane, Basavaraj Talawar
2020 J jnl
ELBA-NoC: ensemble learning-based accelerator for 2D and 3D network-on-chip architectures.
Int. J. Comput. Sci. Eng.
Anil Kumar, Basavaraj Talawar
2020 J jnl
LBNoC: Design of Low-latency Router Architecture with Lookahead Bypass for Network-on-Chip Using FPGA.
ACM Trans. Design Autom. Electr. Syst.
Khyamling Parane, Prabhu B. M. Prasad, Basavaraj Talawar
2020 J jnl
P-NoC: Performance Evaluation and Design Space Exploration of NoCs for Chip Multiprocessor Architecture Using FPGA.
Wirel. Pers. Commun.
Khyamling Parane, Prabhu B. M. Prasad, Basavaraj Talawar
2020 J jnl
Power and performance analysis of 3D network-on-chip architectures.
Comput. Electr. Eng.
Bheemappa Halavar, Basavaraj Talawar
2020 — conf
PowerDPDK: Software-Based Real-Time Power Measurement for DPDK Applications.
NFV-SDN
Mishal Shah, Mehnaz Yunus, Pavan Vachhani, Leslie Monis, Mohit P. Tahiliani, Basavaraj Talawar
2019 J jnl
Analysis of cache behaviour and software optimizations for faster on-chip network simulations.
Int. J. Syst. Assur. Eng. Manag.
Prabhu B. M. Prasad, Khyamling Parane, Basavaraj Talawar
2019 — conf
Design of an Adaptive and Reliable Network on Chip Router Architecture Using FPGA.
VLSI-DAT
Khyamling Parane, Prabhu B. M. Prasad, Basavaraj Talawar
2019 J jnl
Extending BookSim2.0 and HotSpot6.0 for power, performance and thermal evaluation of 3D NoC architectures.
Simul. Model. Pract. Theory
Bheemappa Halavar, Ujjwal Pasupulety, Basavaraj Talawar
2019 — conf
High-Performance NoC Simulation Acceleration Framework Employing the Xilinx DSP48E1 Blocks.
VLSI-DAT
Prabhu B. M. Prasad, Khyamling Parane, Basavaraj Talawar
2019 — conf
High-Performance NoCs Employing the DSP48E1 Blocks of the Xilinx FPGAs.
ISQED
Prabhu B. M. Prasad, Khyamling Parane, Basavaraj Talawar
2019 — conf
MMAS on GPU for Large TSP Instances.
ICCCNT
Pramod Yelmewad, Aniket Kumar, Basavaraj Talawar
2019 J jnl
Parallel iterative hill climbing algorithm to solve TSP on GPU.
Concurr. Comput. Pract. Exp.
Pramod Yelmewad, Basavaraj Talawar
2019 J jnl
Storage Class Memory: Principles, Problems, and Possibilities.
CoRR
Aditya K. Kamath, Leslie Monis, A. Tarun Karthik, Basavaraj Talawar
2019 J jnl
YaNoC: Yet Another Network-on-Chip Simulation Acceleration Engine Supporting Congestion-Aware Adaptive Routing Using FPGAs.
J. Circuits Syst. Comput.
Khyamling Parane, Prabhu B. M. Prasad, Basavaraj Talawar
2018 — conf
Accurate Power and Latency Analysis of a Through-Silicon Via(TSV).
ICACCI
Ujjwal Pasupulety, Bheemappa Halavar, Basavaraj Talawar
2018 — conf
Floorplan Based Performance Evaluation of 3D Variants of Mesh and BFT Networks-on-Chip.
SPCOM
Bheemappa Halavar, Basavaraj Talawar
2018 — conf
Machine Learning Based Framework to Predict Performance Evaluation of On-Chip Networks.
IC3
Anil Kumar, Basavaraj Talawar
2018 — conf
OP3DBFT: A Power and Performance Optimal 3D BFT NoC Architecture.
ISDA (1)
Bheemappa Halavar, Basavaraj Talawar
2018 — conf
Thermal Aware Design for Through-Silicon Via (TSV) based 3D Network-on-Chip (NoC) Architectures.
ISED
Ujjwal Pasupulety, Bheemappa Halavar, Basavaraj Talawar
2018 — conf
Trace-Driven Simulation and Design Space Exploration of Network-on-Chip Topologies on FPGA.
ISED
G. S. Sangeetha, Vignesh Radhakrishnan, Prabhu B. M. Prasad, Khyamling Parane, Basavaraj Talawar
2018 Misc conf
YaNoC: Yet Another Network-on-Chip Simulation Acceleration Engine Using FPGAs.
VLSID
Khyamling Parane, Basavaraj Talawar, Prabhu B. M. Prasad
2017 J jnl
GPU implementation of non-local maximum likelihood estimation method for denoising magnetic resonance images.
J. Real Time Image Process.
Adithya H. K. Upadhya, Basavaraj Talawar, Jeny Rajan
2017 — conf
GPU-Based Iterative Hill Climbing Algorithm to Solve Symmetric Traveling Salesman Problem.
TopHPC
Basavaraj Talawar, Pramod Yelmewad
2016 — conf
Cache analysis and software optimizations for faster on-chip network simulations.
ICIIS
Khyamling Parane, Prabhu B. M. Prasad, Basavaraj Talawar
2015 — conf
A Crossbar Interconnection Network in DNA.
IPDPS Workshops
Basavaraj Talawar