Basant K. Mohanty

29 papers C 3Journal 17Unranked 9

Year	Rank	Type	Title / Venue / Authors
2023	J	`jnl`	A novel computing scheme based on pattern matching for identification of nephron loss and chronic kidney disease stage. Turkish J. Electr. Eng. Comput. Sci. Rehan Ahmad, Basant K. Mohanty
2021	J	`jnl`	Chronic kidney disease stage identification using texture analysis of ultrasound images. Biomed. Signal Process. Control. Rehan Ahmad, Basant K. Mohanty
2020	J	`jnl`	Efficient Diminished-1 Modulo (2n+1) Adder Using Parallel Prefix Adder. J. Circuits Syst. Comput. Subodh Kumar Singhal, Basant K. Mohanty, Sujit Kumar Patel, Gaurav Saxena
2019	J	`jnl`	Area-Delay-Energy Efficient VLSI Architecture for Scalable In-Place Computation of FFT on Real Data. IEEE Trans. Circuits Syst. I Regul. Pap. Basant K. Mohanty, Pramod Kumar Meher
2016	J	`jnl`	LUT Optimization for Distributed Arithmetic-Based Block Least Mean Square Adaptive Filter. IEEE Trans. Very Large Scale Integr. Syst. Basant K. Mohanty, Pramod Kumar Meher, Sujit Kumar Patel
2015	C	`conf`	Critical-path optimization for efficient hardware realization of lifting and flipping DWTs. ISCAS Basant K. Mohanty, Pramod Kumar Meher, Thambipillai Srikanthan
2015	—	`conf`	FPGA implementation of LMS-based FIR adaptive filter for real time digital signal processing applications. DSP Carlo Safarian, Tokunbo Ogunfunmi, Walter J. Kozacky, Basant K. Mohanty
2015	—	`conf`	Leakage-aware intra-task dynamic voltage scaling technique for energy reduction in real-time embedded systems. DSP Vivek Chaturvedi, Basant K. Mohanty, Thambipillai Srikanthan
2015	—	`conf`	Memory-access aware work-load distribution for peak-temperature reduction of 3D multi-core embedded systems. DSP Basant K. Mohanty, Vivek Chaturvedi, Vijeta Rathore, Thambipillai Srikanthan
2014	C	`conf`	Area-delay efficient architecture for MP algorithm using reconfigurable inner-product circuits. ISCAS Pramod Kumar Meher, Basant K. Mohanty, Thambipillai Srikanthan
2014	J	`jnl`	Area-delay-power-efficient architecture for folded two-dimensional discrete wavelet transform by multiple lifting computation. IET Image Process. Basant K. Mohanty, Pramod Kumar Meher
2014	J	`jnl`	Memory Footprint Reduction for Power-Efficient Realization of 2-D Finite Impulse Response Filters. IEEE Trans. Circuits Syst. I Regul. Pap. Basant K. Mohanty, Pramod Kumar Meher, Somaya Al-Máadeed, Abbes Amira
2014	J	`jnl`	Modified PEB Formulation for Hardware-Efficient Fixed-Width Booth Multiplier. Circuits Syst. Signal Process. Basant K. Mohanty, Vikas Tiwari
2013	J	`jnl`	A High-Performance Energy-Efficient Architecture for FIR Adaptive Filter Based on New Distributed Arithmetic Formulation of Block LMS Algorithm. IEEE Trans. Signal Process. Basant K. Mohanty, Pramod Kumar Meher
2013	J	`jnl`	Efficient-Block-Processing Parallel Architecture for Multilevel Lifting 2-D DWT. J. Low Power Electron. Basant K. Mohanty, Anurag Mahajan
2013	J	`jnl`	Memory-Efficient High-Speed Convolution-Based Generic Structure for Multilevel 2-D DWT. IEEE Trans. Circuits Syst. Video Technol. Basant K. Mohanty, Pramod Kumar Meher
2013	J	`jnl`	Scheduling-scheme and parallel structure for multi-level lifting two-dimensional discrete wavelet transform without using frame-buffer. IET Circuits Devices Syst. Basant K. Mohanty, Anurag Mahajan
2013	—	`conf`	Systolic architecture for hardware implementation of two-dimensional non-separable filter-bank. IDT Basant K. Mohanty, Somaya Al-Máadeed, Abbes Amira
2012	J	`jnl`	Area- and Power-Efficient Architecture for High-Throughput Implementation of Lifting 2-D DWT. IEEE Trans. Circuits Syst. II Express Briefs Basant K. Mohanty, Anurag Mahajan, Pramod Kumar Meher
2012	C	`conf`	Efficient architectures for VLSI implementation of 2-D discrete Hadamard transform. ISCAS Basant K. Mohanty, Pramod Kumar Meher, Subodh Kumar Singhal
2011	J	`jnl`	Memory Efficient Modular VLSI Architecture for Highthroughput and Low-Latency Implementation of Multilevel Lifting 2-D DWT. IEEE Trans. Signal Process. Basant K. Mohanty, Pramod Kumar Meher
2011	J	`jnl`	Memory-Efficient Architecture for 3-D DWT Using Overlapped Grouping of Frames. IEEE Trans. Signal Process. Basant K. Mohanty, Pramod Kumar Meher
2010	—	`conf`	Efficient VLSI architecture for implementation of 1-D discrete wavelet transform based on distributed arithmetic. APCCAS Anurag Mahajan, Basant K. Mohanty
2010	J	`jnl`	Parallel and Pipeline Architectures for High-Throughput Computation of Multilevel 3-D DWT. IEEE Trans. Circuits Syst. Video Technol. Basant K. Mohanty, Pramod Kumar Meher
2008	—	`conf`	Concurrent systolic architecture for high-throughput implementation of 3-dimensional discrete wavelet transform. ASAP Basant K. Mohanty, Pramod Kumar Meher
2008	J	`jnl`	Hardware-Efficient Systolic-Like Modular Design for Two-Dimensional Discrete Wavelet Transform. IEEE Trans. Circuits Syst. II Express Briefs Pramod Kumar Meher, Basant K. Mohanty, Jagdish Chandra Patra
2008	—	`conf`	Throughput-scalable hybrid-pipeline architecture for multilevel lifting 2-D DWT of JPEG 2000 coder. ASAP Basant K. Mohanty, Pramod Kumar Meher
2006	—	`conf`	Merged-Cascaded Systolic Array for VLSI Implementation of Discrete Wavelet Transform. APCCAS Basant K. Mohanty, Pramod Kumar Meher
2006	—	`conf`	VLSI Architecture for High-Speed / Low-Power Implementation of Multilevel Lifting DWT. APCCAS Basant K. Mohanty, Pramod Kumar Meher