Bart Vermeulen

51 papers A* 1A 16B 5C 3Misc 2Journal 14Unranked 10

Year	Rank	Type	Title / Venue / Authors
2021	J	`jnl`	Automotive Architecture Topologies: Analysis for Safety-Critical Autonomous Vehicle Applications. IEEE Access Alessandro Frigerio, Bart Vermeulen, Kees G. W. Goossens
2021	—	`conf`	Isolation of redundant and mixed-critical automotive applications: effects on the system architecture. VTC Spring Alessandro Frigerio, Bart Vermeulen, Kees Goossens
2020	A	`conf`	A Distributed Safety Mechanism using Middleware and Hypervisors for Autonomous Vehicles. DATE Tjerk Bijlsma, Andrii Buriachevskyi, Alessandro Frigerio, Yuting Fu, Kees Goossens, Ali Osman Örs, Pieter J. van der Perk, Andrei Sergeevich Terechko, Bart Vermeulen
2019	—	`conf`	Component-Level ASIL Decomposition for Automotive Architectures. DSN Workshops Alessandro Frigerio, Bart Vermeulen, Kees Goossens
2018	B	`conf`	A Generic Method for a Bottom-Up ASIL Decomposition. SAFECOMP Alessandro Frigerio, Bart Vermeulen, Kees Goossens
2016	—	`conf`	Overview of Health Monitoring Techniques for Reliability. ERMAVSS@DATE Abhijit K. Deb, Bart Vermeulen, Luc van Dijk
2014	A	`conf`	Startup error detection and containment to improve the robustness of hybrid FlexRay networks. DATE Alexander Kordes, Bart Vermeulen, Abhijit K. Deb, Michael G. Wahl
2014	A	`conf`	Transient errors resiliency analysis technique for automotive safety critical applications. DATE Sujan Pandey, Bart Vermeulen
2012	C	`conf`	Architecture and design flow for a debug event distribution interconnect. ICCD Arnaldo Azevedo, Bart Vermeulen, Kees Goossens
2011	J	`jnl`	Interactive Debug of SoCs with Multiple Clocks. IEEE Des. Test Comput. Bart Vermeulen, Kees Goossens
2011	A	`conf`	Optimal scheduling of switched FlexRay networks. DATE Thijs Schenkelaars, Bart Vermeulen, Kees Goossens
2010	B	`conf`	A distributed architecture to check global properties for post-silicon debug. ETS Erik Larsson, Bart Vermeulen, Kees Goossens
2010	B	`conf`	INDEXYS, a Logical Step beyond GENESYS. SAFECOMP Andreas Eckel, Paul Milbredt, Zaid Al-Ars, Stefan Schneele, Bart Vermeulen, György Csertán, Christoph Scheerer, Neeraj Suri, Abdelmajid Khelil, Gerhard Fohler
2010	B	`conf`	New scan-based test strategy for a dependable many-core processor using a NoC as a Test Access Mechanism. ETS Xiao Zhang, Hans G. Kerkhoff, Bart Vermeulen
2010	—	`conf`	Obtaining consistent global state dumps to interactively debug systems on chip with multiple clocks. HLDVT Bart Vermeulen, Kees Goossens
2010	J	`jnl`	Obtaining more information from conjoint experiments by best-worst choices. Comput. Stat. Data Anal. Bart Vermeulen, Peter Goos, Martina Vandebroek
2010	C	`conf`	On-chip Scan-Based Test Strategy for a Dependable Many-Core Processor Using a NoC as a Test Access Mechanism. DSD Xiao Zhang, Hans G. Kerkhoff, Bart Vermeulen
2010	—	`conf`	On-line dependability enhancement of multiprocessor SoCs by resource management. SoC Timon D. ter Braak, S. T. Burgess, H. Hurskainen, Hans G. Kerkhoff, Bart Vermeulen, Xiao Zhang
2010	C	`conf`	Switched FlexRay: Increasing the effective bandwidth and safety of FlexRay networks. ETFA Paul Milbredt, Bart Vermeulen, Gökhan Tabanoglu, Martin Lukasiewycz
2010	J	`jnl`	Webcams for Bird Detection and Monitoring: A Demonstration Study. Sensors Willem W. Verstraeten, Bart Vermeulen, Jan Stuckens, Stefaan Lhermitte, Dimitry Van der Zande, Marc Van Ranst, Pol Coppin
2009	A	`conf`	A high-level debug environment for communication-centric debug. DATE Kees Goossens, Bart Vermeulen, Ashkan Beyranvand Nejad
2008	—	`conf`	Debugging Distributed-Shared-Memory Communication at Multiple Granularities in Networks on Chip. NOCS Bart Vermeulen, Kees Goossens, Siddharth Umrani
2008	J	`jnl`	Functional Debug Techniques for Embedded Systems. IEEE Des. Test Comput. Bart Vermeulen
2008	A	`conf`	Integration of Hardware Assertions in Systems-on-Chip. ITC Jeroen Geuzebroek, Bart Vermeulen
2008	J	`jnl`	Overview of Debug Standardization Activities. IEEE Des. Test Comput. Bart Vermeulen, Neal Stollon, Rolf Kühnis, Gary Swoboda, Jeff Rearick
2008	J	`jnl`	Xetal-II: A 107 GOPS, 600 mW Massively Parallel Processor for Video Scene Analysis. IEEE J. Solid State Circuits Anteneh A. Abbo, Richard P. Kleihorst, Vishal Choudhary, Leo Sevat, Paul Wielage, Sebastien Mouy, Bart Vermeulen, Marc J. M. Heijligers
2008	Misc	`conf`	You can catch more bugs with transaction level honey. CODES+ISSS Miron Abramovici, Kees Goossens, Bart Vermeulen, Jack Greenbaum, Neal Stollon, Adam Donlin
2007	—	`conf`	A Run-Time Memory Protection Methodology. ASP-DAC Udaya Seshua, Nagaraju Bussa, Bart Vermeulen
2007	B	`conf`	Communication-Centric SoC Debug Using Transactions. ETS Bart Vermeulen, Kees Goossens, Remco van Steeden, Martijn T. Bennebroek
2007	J	`jnl`	Debug architecture for the En-II system chip. IET Comput. Digit. Tech. Bart Vermeulen, Sjaak Bakker
2007	—	`conf`	Transaction-Based Communication-Centric Debug. NOCS Kees Goossens, Bart Vermeulen, Remco van Steeden, Martijn T. Bennebroek
2005	J	`jnl`	Optimal Interconnect ATPG Under a Ground-Bounce Constraint. J. Electron. Test. Henk D. L. Hollmann, Erik Jan Marinissen, Bart Vermeulen
2005	A	`conf`	Test and debug features of the RTO7 chip. ITC Kees van Kaam, Bart Vermeulen, Henk Jan Bergveld
2004	A*	`conf`	Automatic generation of breakpoint hardware for silicon debug. DAC Bart Vermeulen, Mohammad Zalfany Urfianto, Sandeep Kumar Goel
2004	A	`conf`	Trends in Testing Integrated Circuits. ITC Bart Vermeulen, Camelia Hora, Bram Kruseman, Erik Jan Marinissen, Robert Van Rijsinge
2003	J	`jnl`	Bringing communication networks on a chip: test and verification implications. IEEE Commun. Mag. Bart Vermeulen, John Dielissen, Kees Goossens, Calin Ciordas
2003	A	`conf`	Creating Value Through Test. DATE Erik Jan Marinissen, Bart Vermeulen, Robert Madge, Michael Kessler, Michael Müller
2003	J	`jnl`	Data Invalidation Analysis for Scan-Based Debug on Multiple-Clock System Chips. J. Electron. Test. Sandeep Kumar Goel, Bart Vermeulen
2003	J	`jnl`	Minimizing Pattern Count for Interconnect Test under a Ground Bounce Constraint. IEEE Des. Test Comput. Erik Jan Marinissen, Bart Vermeulen, Henk D. L. Hollmann, Ben Bennetts
2003	J	`jnl`	Multi-TAP Controller Architecture for Digital System Chips. J. Electron. Test. Bart Vermeulen, Tom Waayers, Sjaak Bakker
2003	A	`conf`	Optimal Interconnect ATPG Under a Ground-Bounce Constraint. ITC Henk D. L. Hollmann, Erik Jan Marinissen, Bart Vermeulen
2002	A	`conf`	Core-Based Scan Architecture for Silicon Debug. ITC Bart Vermeulen, Tom Waayers, Sandeep Kumar Goel
2002	—	`conf`	Data invalidation analysis for scan-based debug on multiple-clock system chips. ETW Sandeep Kumar Goel, Bart Vermeulen
2002	J	`jnl`	Design for Debug: Catching Design Errors in Digital Chips. IEEE Des. Test Comput. Bart Vermeulen, Sandeep Kumar Goel
2002	A	`conf`	EEE 1149.1-Compliant Access Architecture for Multiple Core Debug on Digital System Chips. ITC Bart Vermeulen, Tom Waayers, Sjaak Bakker
2002	A	`conf`	Hierarchical Data Invalidation Analysis for Scan-Based Debug on Multiple-Clock System Chips. ITC Sandeep Kumar Goel, Bart Vermeulen
2002	Misc	`conf`	Reducing Time to Volume and Time to Market: Is Silicon Debug and Diagnosis the Answer? VTS Fidel Muradali, Mike Ricchetti, Bart Vermeulen, Bulent I. Dervisoglu, Bob Gottlieb, Bernd Koenemann, C. J. Clark
2002	A	`conf`	TAPS All Over My Chips! So Now What Do I Do? ITC Bart Vermeulen
2001	A	`conf`	Test and debug strategy of the PNX8525 Nexperia ITC Bart Vermeulen, Steven Oostdijk, Frank Bouwman
2000	—	`conf`	Silicon debug of a co-processor array for video applications. HLDVT Bart Vermeulen, Gert-Jan van Rootselaar
1999	A	`conf`	Silicon debug: scan chains alone are not enough. ITC Gert-Jan van Rootselaar, Bart Vermeulen