Bart Kienhuis - RankMe

46 papers A 7B 3C 5Misc 1Journal 11Unranked 18

Year	Rank	Type	Title / Venue / Authors
2016	C	`conf`	Determining Performance Boundaries on High-Level System Specifications. SCOPES Wouter van Teijlingen, Rene van Leuken, Carlo Galuzzi, Bart Kienhuis
2016	—	`conf`	Parametrized system level design: Real-time X-Ray image processing case study. ASAP Tsvetan Shoshkov, Todor P. Stefanov, Bart Kienhuis
2013	J	`jnl`	HEAP: A Highly Efficient Adaptive multi-Processor framework. Microprocess. Microsystems Luciano Lavagno, Mihai T. Lazarescu, Ioannis Papaefstathiou, Andreas Brokalakis, Johan Walters, Bart Kienhuis, Florian Schäfer
2012	—	`conf`	Enabling Automatic Pipeline Utilization Improvement in Polyhedral Process Network Implementations. ASAP Sven van Haastregt, Bart Kienhuis
2012	—	`conf`	FIFO Exploration in Mapping Streaming Applications onto the TI OMAP3530 Platform: Case Study and Optimizations. MCSoC Weihua Sheng, Artur Wiebe, Anastasia Stulova, Rainer Leupers, Bart Kienhuis, Johan Walters, Gerd Ascheid
2012	C	`conf`	HEAP: A Highly Efficient Adaptive Multi-processor Framework. DSD Luciano Lavagno, Mihai T. Lazarescu, Ioannis Papaefstathiou, Andreas Brokalakis, Johan Walters, Bart Kienhuis, Florian Schäfer
2012	—	`conf`	Scaling Data-Intensive Applications on Heterogeneous Platforms with Accelerators. IPDPS Workshops Ana Balevic, Bart Kienhuis
2011	C	`conf`	A data parallel view on polyhedral process networks. SCOPES Ana Balevic, Bart Kienhuis
2011	A	`conf`	High level synthesis for FPGAs applied to a sphere decoder channel preprocessor (abstract only). FPGA Sven van Haastregt, Stephen Neuendorffer, Kees A. Vissers, Bart Kienhuis
2011	—	`conf`	IP-XACT extensions for Reconfigurable Computing. ASAP Razvan Nane, Sven van Haastregt, Todor P. Stefanov, Bart Kienhuis, Vlad Mihai Sima, Koen Bertels
2011	J	`jnl`	KPN2GPU: an approach for discovery and exploitation of fine-grain data parallelism in process networks. SIGARCH Comput. Archit. News Ana Balevic, Bart Kienhuis
2010	A	`conf`	Cool MPSoC programming. DATE Rainer Leupers, Lothar Thiele, Xiaoning Nie, Bart Kienhuis, Matthias Weiss, Tsuyoshi Isshiki
2010	A	`conf`	Cost modeling and cycle-accurate co-simulation of heterogeneous multiprocessor systems. DATE Sven van Haastregt, Eyal Halm, Bart Kienhuis
2009	A	`conf`	Automated synthesis of streaming C applications to process networks in hardware. DATE Sven van Haastregt, Bart Kienhuis
2009	—	`conf`	Introduction. Euro-Par Barbara M. Chapman, Bart Kienhuis, Eduard Ayguadé, François Bodin, Oscar G. Plata, Eric Stotzer
2008	J	`jnl`	Deriving efficient control in Process Networks with Compaan/Laura. Int. J. Embed. Syst. Steven Derrien, Alexandru Turjan, Claudiu Zissulescu, Bart Kienhuis, Ed F. Deprettere
2008	—	`conf`	Hierarchical run time deadlock detection in process networks. SiPS Bin Jiang, Ed F. Deprettere, Bart Kienhuis
2007	C	`conf`	Automatic partitioning and mapping of stream-based applications onto the Intel IXP Network processor. SCOPES Sjoerd Meijer, Bart Kienhuis, Johan Walters, David Snuijf
2007	J	`jnl`	Classifying interprocess communication in process network representation of nested-loop programs. ACM Trans. Embed. Comput. Syst. Alexandru Turjan, Bart Kienhuis, Ed F. Deprettere
2007	A	`conf`	Interactive presentation: A process splitting transformation for Kahn process networks. DATE Sjoerd Meijer, Bart Kienhuis, Alexandru Turjan, Erwin A. de Kock
2007	J	`jnl`	Parameterized Looped Schedules for Compact Representation of Execution Sequences in DSP Hardware and Software Implementation. IEEE Trans. Signal Process. Ming-Yung Ko, Claudiu Zissulescu, Sebastian Puthenpurayil, Shuvra S. Bhattacharyya, Bart Kienhuis, Ed F. Deprettere
2005	B	`conf`	Communication Synthesis in a multiprocessor environment. FPL Claudiu Zissulescu, Bart Kienhuis, Ed F. Deprettere
2005	—	`conf`	Expression Synthesis in Process Networks generated by LAURA. ASAP Claudiu Zissulescu, Bart Kienhuis, Ed F. Deprettere
2005	J	`jnl`	Solving Out-of-Order Communication in Kahn Process Networks. J. VLSI Signal Process. Alexandru Turjan, Bart Kienhuis, Ed F. Deprettere
2004	—	`conf`	A Hierarchical Classification Scheme to Derive Interprocess Communication in Process Networks. ASAP Alexandru Turjan, Bart Kienhuis, Ed F. Deprettere
2004	C	`conf`	An Integer Linear Programming Approach to Classify the Communication in Process Networks. SCOPES Alexandru Turjan, Bart Kienhuis, Ed F. Deprettere
2004	—	`ch.`	Architectures and Design Techniques for Energy Efficient Embedded DSP and Multimedia Processing. Ultra Low-Power Electronics and Design Ingrid Verbauwhede, Patrick Schaumont, Christian Piguet, Bart Kienhuis
2004	A	`conf`	Architectures and Design Techniques for Energy Efficient Embedded DSP and Multimedia Processing. DATE Ingrid Verbauwhede, Patrick Schaumont, Christian Piguet, Bart Kienhuis
2004	B	`conf`	Increasing Pipelined IP Core Utilization in Process Networks Using Exploration. FPL Claudiu Zissulescu, Bart Kienhuis, Ed F. Deprettere
2004	A	`conf`	System Design Using Kahn Process Networks: The Compaan/Laura Approach. DATE Todor P. Stefanov, Claudiu Zissulescu, Alexandru Turjan, Bart Kienhuis, Ed F. Deprettere
2004	Misc	`conf`	Translating affine nested-loop programs to process networks. CASES Alexandru Turjan, Bart Kienhuis, Ed F. Deprettere
2003	B	`conf`	Laura: Leiden Architecture Research and Exploration Tool. FPL Claudiu Zissulescu, Todor P. Stefanov, Bart Kienhuis, Ed F. Deprettere
2003	J	`jnl`	Modeling Stream-Based Applications Using the SBF Model of Computation. J. VLSI Signal Process. Bart Kienhuis, Ed F. Deprettere
2003	—	`conf`	Storage Management in Process Networks using the Lexicographically Maximal Preimage. ASAP Alexandru Turjan, Bart Kienhuis
2002	—	`conf`	A Compile Time Based Approach for Solving Out-of-Order Communication in Kahn Process Networks. ASAP Alexandru Turjan, Bart Kienhuis, Ed F. Deprettere
2002	—	`conf`	A Methodology to Design Programmable Embedded Systems - The Y-Chart Approach. Embedded Processor Design Challenges Bart Kienhuis, Ed F. Deprettere, Pieter van der Wolf, Kees A. Vissers
2002	—	`conf`	Algorithmic transformation techniques for efficient exploration of alternative application instances. CODES Todor P. Stefanov, Bart Kienhuis, Ed F. Deprettere
2002	J	`jnl`	Compilation From Matlab to Process Networks Realized in FPGA. Des. Autom. Embed. Syst. Tim Harriss, Richard L. Walke, Bart Kienhuis, Ed F. Deprettere
2002	J	`jnl`	Preface. Des. Autom. Embed. Syst. Ed F. Deprettere, Bart Kienhuis, Richard L. Walke
2002	—	`conf`	Translating Imperative Affine Nested Loop Programs into Process Networks. Embedded Processor Design Challenges Ed F. Deprettere, Edwin Rijpkema, Bart Kienhuis
2000	—	`conf`	Compaan: deriving process networks from Matlab for embedded signal processing architectures. CODES Bart Kienhuis, Edwin Rijpkema, Ed F. Deprettere
2000	J	`jnl`	Deriving Process Networks from Nested Loop Algorithms. Parallel Process. Lett. Edwin Rijpkema, Ed F. Deprettere, Bart Kienhuis
2000	—	`conf`	High Level Modeling for Parallel Executions of Nested Loop Algorithms. ASAP Ed F. Deprettere, Edwin Rijpkema, Paul Lieverse, Bart Kienhuis
1999	J	`jnl`	A Clustering Approach to Explore Grain-Sizes in the Definition of Processing Elements in Dataflow Architectures. J. VLSI Signal Process. Paul Lieverse, Ed F. Deprettere, Bart Kienhuis, Erwin A. de Kock
1998	—	`conf`	The construction of a retargetable simulator for an architecture template. CODES Bart Kienhuis, Ed F. Deprettere, Kees A. Vissers, Pieter van der Wolf
1997	—	`conf`	An Approach for Quantitative Analysis of Application-Specific Dataflow Architectures. ASAP Bart Kienhuis, Ed F. Deprettere, Kees A. Vissers, Pieter van der Wolf