Baris Taskin - RankMe

131 papers A* 1A 11B 2C 30Misc 4Journal 35Unranked 45

Year	Rank	Type	Title / Venue / Authors
2025	A	`conf`	A Multi-Stage Potts Machine Based on Coupled CMOS Ring Oscillators. DATE Yilmaz Ege Gonul, Baris Taskin
2025	J	`jnl`	A Multi-Stage Potts Machine based on Coupled CMOS Ring Oscillators. CoRR Yilmaz Ege Gonul, Baris Taskin
2025	—	`conf`	GPU-Accelerated Simulated Oscillator Ising/Potts Machine Solving Combinatorial Optimization Problems. ACM Great Lakes Symposium on VLSI Yilmaz Ege Gonul, Ceyhun Efe Kayan, Ilknur Mustafazade, Nagarajan Kandasamy, Baris Taskin
2025	J	`jnl`	GPU-Accelerated Simulated Oscillator Ising/Potts Machine Solving Combinatorial Optimization Problems. CoRR Yilmaz Ege Gonul, Ceyhun Efe Kayan, Ilknur Mustafazade, Nagarajan Kandasamy, Baris Taskin
2025	J	`jnl`	Multi-Phase Coupled CMOS Ring Oscillator based Potts Machine. CoRR Yilmaz Ege Gonul, Baris Taskin
2024	C	`conf`	Design Automation for Charge Recovery Logic. ISCAS Yilmaz Ege Gonul, Leo Filippini, Junghoon Oh, Ragh Kuttappa, Scott Lerner, Mineo Kaneko, Baris Taskin
2024	C	`conf`	High-Speed Phase-Based Computing. ISCAS Nicholas Sica, Ragh Kuttappa, Vinayak Honkote, Baris Taskin
2024	A	`conf`	Multi-phase Coupled CMOS Ring Oscillator based Potts Machine. ICCAD Yilmaz Ege Gonul, Baris Taskin
2022	C	`conf`	A 0.45 pJ/bit 20 Gb/s/Wire Parallel Die-to-Die Interface with Rotary Traveling Wave Oscillators. ISCAS Ragh Kuttappa, Baris Taskin
2022	J	`jnl`	Interconnects for DNA, Quantum, In-Memory, and Optical Computing: Insights From a Panel Discussion. IEEE Micro Amlan Ganguly, Sergi Abadal, Ishan G. Thakkar, Natalie Enright Jerger, Marc D. Riedel, Masoud Babaie, Rajeev Balasubramonian, Abu Sebastian, Sudeep Pasricha, Baris Taskin
2022	J	`jnl`	Multiphase Digital Low-Dropout Regulators. IEEE Trans. Very Large Scale Integr. Syst. Ragh Kuttappa, Longfei Wang, Selçuk Köse, Baris Taskin
2022	C	`conf`	Resonant Rotary Clock Synchronization with Active and Passive Silicon Interposer. ISCAS Ragh Kuttappa, Baris Taskin, Vinayak Honkote, Satish Yada, Jainaveen Sundaram, Dileep Kurian, Tanay Karnik, Anuradha Srinivasan
2021	J	`jnl`	Resonant Clock Synchronization With Active Silicon Interposer for Multi-Die Systems. IEEE Trans. Circuits Syst. I Regul. Pap. Ragh Kuttappa, Baris Taskin, Scott Lerner, Vasil Pano
2021	—	`conf`	Scalable Resonant Power Clock Generation for Adiabatic Logic Design. ISVLSI Ragh Kuttappa, Leo Filippini, Nicholas Sica, Baris Taskin
2020	C	`conf`	Comprehensive Low Power Adiabatic Circuit Design with Resonant Power Clocking. ISCAS Ragh Kuttappa, Steven Khoa, Leo Filippini, Vasil Pano, Baris Taskin
2020	C	`conf`	FinFET - Based Low Swing Rotary Traveling Wave Oscillators. ISCAS Ragh Kuttappa, Baris Taskin
2020	A*	`conf`	SnackNoC: Processing in the Communication Layer. HPCA Karthik Sangaiah, Michael Lui, Ragh Kuttappa, Baris Taskin, Mark Hempstead
2020	J	`jnl`	TSV Antennas for Multi-Band Wireless Communication. IEEE J. Emerg. Sel. Topics Circuits Syst. Vasil Pano, Ibrahim Tekin, Isikcan Yilmaz, Yuqiao Liu, Kapil R. Dandekar, Baris Taskin
2019	—	`conf`	3D NoCs with active interposer for multi-die systems. NOCS Vasil Pano, Ragh Kuttappa, Baris Taskin
2019	J	`jnl`	Custard: ASIC Workload-Aware Reliable Design for Multicore IoT Processors. IEEE Trans. Very Large Scale Integr. Syst. Scott Lerner, Isikcan Yilmaz, Baris Taskin
2019	—	`conf`	Distributed Digital Low-Dropout Regulators with Phase Interleaving for On-Chip Voltage Noise Mitigation. SLIP Longfei Wang, Ragh Kuttappa, Baris Taskin, Selçuk Köse
2019	J	`jnl`	FOPAC: Flexible On-Chip Power and Clock. IEEE Trans. Circuits Syst. I Regul. Pap. Ragh Kuttappa, Selçuk Köse, Baris Taskin
2019	C	`conf`	Low Swing - Low Frequency Rotary Traveling Wave Oscillators. ISCAS Ragh Kuttappa, Scott Lerner, Leo Filippini, Baris Taskin
2019	—	`conf`	Low Voltage Clock Tree Synthesis with Local Gate Clusters. ACM Great Lakes Symposium on VLSI Can Sitik, Weicheng Liu, Baris Taskin, Emre Salman
2019	—	`conf`	On-chip wireless interconnect paradigm. NoCArc@MICRO Baris Taskin
2019	—	`ed.`	Proceedings of the 2019 on Great Lakes Symposium on VLSI, GLSVLSI 2019, Tysons Corner, VA, USA, May 9-11, 2019 ACM Great Lakes Symposium on VLSI Houman Homayoun, Baris Taskin, Tinoosh Mohsenin, Weisheng Zhao
2019	A	`conf`	Robust Low Power Clock Synchronization for Multi-Die Systems. ISLPED Ragh Kuttappa, Baris Taskin, Scott Lerner, Vasil Pano, Ioannis Savidis
2019	J	`jnl`	RotaSYN: Rotary Traveling Wave Oscillator SYNthesizer. IEEE Trans. Circuits Syst. I Regul. Pap. Ragh Kuttappa, Adarsha Balaji, Vasil Pano, Baris Taskin, Hamid Mahmoodi
2019	J	`jnl`	SLECTS: Slew-Driven Clock Tree Synthesis. IEEE Trans. Very Large Scale Integr. Syst. Weicheng Liu, Can Sitik, Emre Salman, Baris Taskin, Savithri Sundareswaran, Benjamin Huang
2019	J	`jnl`	Slew Merging Region Propagation for Bounded Slew and Skew Clock Tree Synthesis. IEEE Trans. Very Large Scale Integr. Syst. Scott Lerner, Baris Taskin
2019	J	`jnl`	The Adiabatically Driven StrongARM Comparator. IEEE Trans. Circuits Syst. II Express Briefs Leo Filippini, Baris Taskin
2018	C	`conf`	A 900 MHz Charge Recovery Comparator With 40 fJ per Conversion. ISCAS Leo Filippini, Baris Taskin
2018	C	`conf`	Low Frequency Rotary Traveling Wave Oscillators. ISCAS Ragh Kuttappa, Baris Taskin
2018	C	`conf`	NoC Router Lifetime Improvement using Per-Port Router Utilization. ISCAS Scott Lerner, Vasil Pano, Baris Taskin
2018	—	`ed.`	Proceedings of the 2018 on Great Lakes Symposium on VLSI, GLSVLSI 2018, Chicago, IL, USA, May 23-25, 2018 ACM Great Lakes Symposium on VLSI Deming Chen, Houman Homayoun, Baris Taskin
2018	J	`jnl`	SynchroTrace: Synchronization-Aware Architecture-Agnostic Traces for Lightweight Multicore Simulation of CMP and HPC Workloads. ACM Trans. Archit. Code Optim. Karthik Sangaiah, Michael Lui, Radhika Jagtap, Stephan Diestelhorst, Siddharth Nilakantan, Ankit More, Baris Taskin, Mark Hempstead
2018	B	`conf`	Towards Cross-Framework Workload Analysis via Flexible Event-Driven Interfaces. ISPASS Michael Lui, Karthik Sangaiah, Mark Hempstead, Baris Taskin
2018	—	`conf`	Towards Design Decisions for Genetic Algorithms in Clock Tree Synthesis. IGSC Scott Lerner, Baris Taskin
2018	J	`jnl`	Vertical Arbitration-Free 3-D NoCs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ankit More, Vasil Pano, Baris Taskin
2018	C	`conf`	Workload-Aware Routing (WAR) for Network-on-Chip Lifetime Improvement. ISCAS Vasil Pano, Scott Lerner, Isikcan Yilmaz, Michael Lui, Baris Taskin
2017	—	`conf`	A charge recovery logic system bus. SLIP Leo Filippini, Baris Taskin
2017	—	`conf`	Charge recovery implementation of an analog comparator: Initial results. MWSCAS Leo Filippini, Lunal Khuon, Baris Taskin
2017	A	`conf`	Reconfigurable threshold logic gates using optoelectronic capacitors. DATE Ragh Kuttappa, Lunal Khuon, Bahram Nabet, Baris Taskin
2017	—	`conf`	Slew-down: analysis of slew relaxation for low-impact clock buffers. SLIP Scott Lerner, Eric Leggett, Baris Taskin
2017	J	`jnl`	Special issue on IEEE/ACM System Level Interconnect Prediction (SLIP) Workshop 2016. Integr. Tsung-Yi Ho, Baris Taskin
2017	C	`conf`	Stability of Rotary Traveling Wave Oscillators under process variations and NBTI. ISCAS Ragh Kuttappa, Leo Filippini, Scott Lerner, Baris Taskin
2017	—	`conf`	WT-CTS: Incremental Delay Balancing Using Parallel Wiring Type For CTS. ISVLSI Scott Lerner, Baris Taskin
2017	—	`conf`	Wireless NoCs Using Directional and Substrate Propagation Antennas. ISVLSI Vasil Pano, Yuqiao Liu, Isikcan Yilmaz, Ankit More, Baris Taskin, Kapil R. Dandekar
2017	—	`conf`	Wireless charge recovery system for implanted electroencephalography applications in mice. ISQED Leo Filippini, Diane Lim, Lunal Khuon, Baris Taskin
2017	—	`conf`	Workload-aware ASIC flow for lifetime improvement of multi-core IoT processors. ISQED Scott Lerner, Baris Taskin
2016	C	`conf`	Charge recovery logic for thermal harvesting applications. ISCAS Leo Filippini, Baris Taskin
2016	J	`jnl`	Design Methodology for Voltage-Scaled Clock Distribution Networks. IEEE Trans. Very Large Scale Integr. Syst. Can Sitik, Weicheng Liu, Baris Taskin, Emre Salman
2016	C	`conf`	Energy aware routing of multi-level Network-on-Chip traffic. ICCD Vasil Pano, Isikcan Yilmaz, Ankit More, Baris Taskin
2016	C	`conf`	Exploiting useful skew in gated low voltage clock trees. ISCAS Weicheng Liu, Emre Salman, Can Sitik, Baris Taskin
2016	—	`ed.`	Proceedings of the 18th System Level Interconnect Prediction Workshop, SLIP 2016, Austin, TX, USA, June 4, 2016 SLIP Baris Taskin, Tsung-Yi Ho
2016	C	`conf`	Wireless Network-on-Chip analysis of propagation technique for on-chip communication. ICCD Vasil Pano, Isikcan Yilmaz, Yuqiao Liu, Baris Taskin, Kapil R. Dandekar
2015	—	`conf`	A Novel Static D-Flip-Flop Topology for Low Swing Clocking. ACM Great Lakes Symposium on VLSI Mallika Rathore, Weicheng Liu, Emre Salman, Can Sitik, Baris Taskin
2015	C	`conf`	A wirelessly powered system with charge recovery logic. ICCD Leo Filippini, Emre Salman, Baris Taskin
2015	Misc	`conf`	Can You Trust Your Memory Trace? A Comparison of Memory Traces from Binary Instrumentation and Simulation. VLSID Siddharth Nilakantan, Scott Lerner, Mark Hempstead, Baris Taskin
2015	—	`conf`	Clock Skew Scheduling in the Presence of Heavily Gated Clock Networks. ACM Great Lakes Symposium on VLSI Weicheng Liu, Emre Salman, Can Sitik, Baris Taskin
2015	Misc	`conf`	Effects of Nondeterminism in Hardware and Software Simulation with Thread Mapping. VLSID Giordano Salvador, Siddharth Nilakantan, Baris Taskin, Mark Hempstead, Ankit More
2015	C	`conf`	Enhanced level shifter for multi-voltage operation. ISCAS Weicheng Liu, Emre Salman, Can Sitik, Baris Taskin
2015	J	`jnl`	FinFET-Based Low-Swing Clocking. ACM J. Emerg. Technol. Comput. Syst. Can Sitik, Emre Salman, Leo Filippini, Sung-Jun Yoon, Baris Taskin
2015	J	`jnl`	Locality-Aware Network Utilization Balancing in NoCs. ACM Trans. Design Autom. Electr. Syst. Ankit More, Baris Taskin
2015	J	`jnl`	ROA-Brick Topology for Low-Skew Rotary Resonant Clock Network Design. IEEE Trans. Very Large Scale Integr. Syst. Ying Teng, Baris Taskin
2015	B	`conf`	Synchrotrace: synchronization-aware architecture-agnostic traces for light-weight multicore simulation. ISPASS Siddharth Nilakantan, Karthik Sangaiah, Ankit More, Giordano Salvador, Baris Taskin, Mark Hempstead
2015	A	`conf`	Uncore RPD: Rapid Design Space Exploration of the Uncore via Regression Modeling. ICCAD Karthik Sangaiah, Mark Hempstead, Baris Taskin
2014	A	`conf`	Frequency-centric resonant rotary clock distribution network design. ICCAD Ying Teng, Baris Taskin
2014	—	`conf`	High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design. ISVLSI Can Sitik, Leo Filippini, Emre Salman, Baris Taskin
2014	J	`jnl`	Iterative skew minimization for low swing clocks. Integr. Can Sitik, Baris Taskin
2014	—	`conf`	Range-based dynamic routing of hierarchical on chip network traffic. SLIP Julian Kemmerer, Baris Taskin
2014	C	`conf`	Static thread mapping for NoCs via binary instrumentation traces. ICCD Giordano Salvador, Siddharth Nilakantan, Baris Taskin, Mark Hempstead, Ankit More
2014	C	`conf`	Timing characterization of clock buffers for clock tree synthesis. ICCD Can Sitik, Scott Lerner, Baris Taskin
2013	—	`conf`	A microcontroller-based embedded system design course with PSoC3. MSE Can Sitik, Prawat Nagvajara, Baris Taskin
2013	—	`conf`	Multi-corner multi-voltage domain clock mesh design. ACM Great Lakes Symposium on VLSI Can Sitik, Baris Taskin
2013	C	`conf`	Resonant frequency divider design methodology for dynamic frequency scaling. ICCD Ying Teng, Baris Taskin
2013	—	`conf`	Rotary traveling wave oscillator frequency division at nanoscale technologies. ACM Great Lakes Symposium on VLSI Ying Teng, Baris Taskin
2013	—	`conf`	Skew-bounded low swing clock tree optimization. ACM Great Lakes Symposium on VLSI Can Sitik, Baris Taskin
2013	A	`conf`	Sparse-rotary oscillator array (SROA) design for power and skew reduction. DATE Ying Teng, Baris Taskin
2013	—	`conf`	Wireless on Networks-on-Chip. SLIP Baris Taskin
2012	Misc	`conf`	3-D Parasitic Modeling for Rotary Interconnects. VLSI Design Vinayak Honkote, Ankit More, Baris Taskin
2012	J	`jnl`	A Reconfigurable Clock Polarity Assignment Flow for Clock Gated Designs. IEEE Trans. Very Large Scale Integr. Syst. Jianchao Lu, Ying Teng, Baris Taskin
2012	—	`conf`	A locality-aware bi-level mesh-mesh 2d-noc architecture for future thousand core CMPs. SLIP Ankit More, Baris Taskin
2012	C	`conf`	A unified design methodology for a hybrid wireless 2-D NoC. ISCAS Ankit More, Baris Taskin
2012	C	`conf`	Clock mesh synthesis method using the Earth Mover's Distance under transformations. ICCD Ying Teng, Baris Taskin
2012	A	`conf`	Clock mesh synthesis with gated local trees and activity driven register clustering. ICCAD Jianchao Lu, Xiaomi Mao, Baris Taskin
2012	A	`conf`	High-Performance, Low-Power Resonant Clocking: Embedded tutorial. ICCAD Matthew R. Guthaus, Baris Taskin
2012	J	`jnl`	Integrated Clock Mesh Synthesis With Incremental Register Placement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jianchao Lu, Xiaomi Mao, Baris Taskin
2012	C	`conf`	Multi-voltage domain clock mesh design. ICCD Can Sitik, Baris Taskin
2012	—	`conf`	Synchronization scheme for brick-based rotary oscillator arrays. ACM Great Lakes Symposium on VLSI Ying Teng, Baris Taskin
2012	J	`jnl`	ZeROA: Zero Clock Skew Rotary Oscillatory Array. IEEE Trans. Very Large Scale Integr. Syst. Vinayak Honkote, Baris Taskin
2011	J	`jnl`	CROA: Design and Analysis of the Custom Rotary Oscillatory Array. IEEE Trans. Very Large Scale Integr. Syst. Vinayak Honkote, Baris Taskin
2011	J	`jnl`	Clock buffer polarity assignment with skew tuning. ACM Trans. Design Autom. Electr. Syst. Jianchao Lu, Baris Taskin
2011	C	`conf`	EM and circuit co-simulation of a reconfigurable hybrid wireless NoC on 2D ICs. ICCD Ankit More, Baris Taskin
2011	—	`conf`	From RTL to GDSII: An ASIC design course development using Synopsys® University Program. MSE Jianchao Lu, Baris Taskin
2011	—	`conf`	Process variation sensitivity of the Rotary Traveling Wave Oscillator. ISQED Ying Teng, Baris Taskin
2011	C	`conf`	ROA-brick topology for rotary resonant clocks. ICCD Ying Teng, Jianchao Lu, Baris Taskin
2011	C	`conf`	Reconfigurable clock polarity assignment for peak current reduction of clock-gated circuits. ISCAS Jianchao Lu, Baris Taskin
2011	C	`conf`	Register On MEsh (ROME): A novel approach for clock mesh network synthesis. ISCAS Jianchao Lu, Yusuf Aksehir, Baris Taskin
2011	—	`conf`	Simulation based study of on-chip antennas for a reconfigurable hybrid 2D wireless network-on-chip. SLIP Ankit More, Baris Taskin
2011	J	`jnl`	Statistical Timing Analysis of the Clock Period Improvement through Clock Skew Scheduling. J. Circuits Syst. Comput. Shannon M. Kurtas, Baris Taskin
2011	A	`conf`	Steiner tree based rotary clock routing with bounded skew and capacitive load balancing. DATE Jianchao Lu, Vinayak Honkote, Xin Chen, Baris Taskin
2011	—	`conf`	Timing slack aware incremental register placement with non-uniform grid generation for clock mesh synthesis. ISPD Jianchao Lu, Xiaomi Mao, Baris Taskin
2010	Misc	`conf`	Analysis, Design and Simulation of Capacitive Load Balanced Rotary Oscillatory Array. VLSI Design Vinayak Honkote, Baris Taskin
2010	—	`conf`	Clock Tree Synthesis with XOR Gates for Polarity Assignment. ISVLSI Jianchao Lu, Baris Taskin
2010	—	`conf`	Clock buffer polarity assignment considering capacitive load. ISQED Jianchao Lu, Baris Taskin
2010	—	`conf`	Electromagnetic interaction of on-chip antennas and CMOS metal layers for wireless IC interconnects. ACM Great Lakes Symposium on VLSI Ankit More, Baris Taskin
2010	—	`conf`	Leakage current analysis for intra-chip wireless interconnects. ISQED Ankit More, Baris Taskin
2010	J	`jnl`	Look-Up Table Based Low Power Rotary Traveling Wave Oscillator Design Considering the Skin Effect. J. Low Power Electron. Ying Teng, Baris Taskin
2010	A	`conf`	PEEC based parasitic modeling for power analysis on custom rotary rings. ISLPED Vinayak Honkote, Baris Taskin
2010	J	`jnl`	Post-CTS Delay Insertion. VLSI Design Jianchao Lu, Baris Taskin
2010	—	`conf`	Simulation Based Feasibility Study of Wireless RF Interconnects for 3D ICs. ISVLSI Ankit More, Baris Taskin
2010	—	`conf`	Simulation based study of on-chip antennas for a reconfigurable hybrid 3D wireless NoC. SoCC Ankit More, Baris Taskin
2010	—	`conf`	Simulation based study of wireless RF interconnects for practical CMOs implementation. SLIP Ankit More, Baris Taskin
2010	—	`conf`	Skew analysis and bounded skew constraint methodology for rotary clocking technology. ISQED Vinayak Honkote, Baris Taskin
2010	C	`conf`	Skew-aware capacitive load balancing for low-power zero clock skew rotary oscillatory array. ICCD Vinayak Honkote, Baris Taskin
2009	J	`jnl`	A shift-register-based QCA memory architecture. ACM J. Emerg. Technol. Comput. Syst. Baris Taskin, Andy Chiu, Jonathan Salkind, Daniel Venutolo
2009	J	`jnl`	Custom topology rotary clock router with tree subnetworks. ACM Trans. Design Autom. Electr. Syst. Baris Taskin, Joseph Demaio, Owen Farell, Michael Hazeltine, Ryan Ketner
2009	J	`jnl`	Multi-Phase Rotary Clock Synchronization of Level-Sensitive Circuits. J. Circuits Syst. Comput. Baris Taskin, Ivan S. Kourtev
2009	—	`conf`	Zero clock skew synchronization with rotary clocking technology. ISQED Vinayak Honkote, Baris Taskin
2008	C	`conf`	Custom rotary clock router. ICCD Vinayak Honkote, Baris Taskin
2008	J	`jnl`	Improving Line-Based QCA Memory Cell Design Through Dual Phase Clocking. IEEE Trans. Very Large Scale Integr. Syst. Baris Taskin, Bo Hong
2007	—	`conf`	A shift-register-based QCA memory architecture. NANOARCH Baris Taskin, Andy Chiu, Jonathan Salkind, Daniel Venutolo
2007	—	`conf`	Design-for-Debug: A Vital Aspect in Education. MSE Prawat Nagvajara, Baris Taskin
2006	J	`jnl`	Delay Insertion Method in Clock Skew Scheduling. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Baris Taskin, Ivan S. Kourtev
2005	—	`conf`	Delay insertion method in clock skew scheduling. ISPD Baris Taskin, Ivan S. Kourtev
2004	—	`conf`	Advanced timing of level-sensitive sequential circuits. ICECS Baris Taskin, Ivan S. Kourtev
2004	J	`jnl`	Linearization of the timing analysis and optimization of level-sensitive digital synchronous circuits. IEEE Trans. Very Large Scale Integr. Syst. Baris Taskin, Ivan S. Kourtev
2004	—	`conf`	Performance improvement of edge-triggered sequential circuits. ICECS Baris Taskin, Ivan S. Kourtev
2004	—	`conf`	Time borrowing and clock skew scheduling effects on multi-phase level-sensitive circuits. ISCAS (2) Baris Taskin, Ivan S. Kourtev
2002	—	`conf`	Performance optimization of single-phase level-sensitive circuits using time borrowing and non-zero clock skew. Timing Issues in the Specification and Synthesis of Digital Systems Baris Taskin, Ivan S. Kourtev