Bapi Kar - RankMe

18 papers C 1Misc 2Journal 8Unranked 7

Year	Rank	Type	Title / Venue / Authors
2020	J	`jnl`	ADEPOS: A Novel Approximate Computing Framework for Anomaly Detection Systems and its Implementation in 65-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. Sumon Kumar Bose, Bapi Kar, Mohendra Roy, Pradeep Kumar Gopalakrishnan, Lei Zhang, Aakash Patil, Arindam Basu
2020	J	`jnl`	ADIC: Anomaly Detection Integrated Circuit in 65-nm CMOS Utilizing Approximate Computing. IEEE Trans. Very Large Scale Integr. Syst. Bapi Kar, Pradeep Kumar Gopalakrishnan, Sumon Kumar Bose, Mohendra Roy, Arindam Basu
2020	J	`jnl`	ADIC: Anomaly Detection Integrated Circuit in 65nm CMOS utilizing Approximate Computing. CoRR Bapi Kar, Pradeep Kumar Gopalakrishnan, Sumon Kumar Bose, Mohendra Roy, Arindam Basu
2019	J	`jnl`	ADEPOS: A Novel Approximate Computing Framework for Anomaly Detection Systems and its Implementation in 65nm CMOS. CoRR Sumon Kumar Bose, Bapi Kar, Mohendra Roy, Pradeep Kumar Gopalakrishnan, Lei Zhang, Aakash Patil, Arindam Basu
2019	—	`conf`	ADEPOS: anomaly detection based power saving for predictive maintenance using edge computing. ASP-DAC Sumon Kumar Bose, Bapi Kar, Mohendra Roy, Pradeep Kumar Gopalakrishnan, Arindam Basu
2019	C	`conf`	Live Demonstration: Autoencoder-Based Predictive Maintenance for IoT. ISCAS Pradeep Kumar Gopalakrishnan, Bapi Kar, Sumon Kumar Bose, Mohendra Roy, Arindam Basu
2018	—	`conf`	A Stacked Autoencoder Neural Network based Automated Feature Extraction Method for Anomaly detection in On-line Condition Monitoring. SSCI Mohendra Roy, Sumon Kumar Bose, Bapi Kar, Pradeep Kumar Gopalakrishnan, Arindam Basu
2018	J	`jnl`	A Stacked Autoencoder Neural Network based Automated Feature Extraction Method for Anomaly detection in On-line Condition Monitoring. CoRR Mohendra Roy, Sumon Kumar Bose, Bapi Kar, Pradeep Kumar Gopalakrishnan, Arindam Basu
2018	J	`jnl`	Early Routability Assessment in VLSI Floorplans: A Generalized Routing Model. CoRR Bapi Kar, Susmita Sur-Kolay, Chittaranjan A. Mandal
2018	J	`jnl`	Exploring the Scope of Unconstrained Via Minimization by Recursive Floorplan Bipartitioning. CoRR Bapi Kar, Susmita Sur-Kolay, Chittaranjan A. Mandal
2018	J	`jnl`	STAIRoute: Early Global Routing using Monotone Staircases for Congestion Reduction. CoRR Bapi Kar, Susmita Sur-Kolay, Chittaranjan A. Mandal
2016	Misc	`conf`	A Novel EPE Aware Hybrid Global Route Planner after Floorplanning. VLSID Bapi Kar, Susmita Sur-Kolay, Chittaranjan A. Mandal
2016	—	`conf`	An early global routing framework for uniform wire distribution in SoCs. SoCC Bapi Kar, Susmita Sur-Kolay, Chittaranjan A. Mandal
2015	—	`conf`	A New Method for Defining Monotone Staircases in VLSI Floorplans. ISVLSI Bapi Kar, Susmita Sur-Kolay, Chittaranjan A. Mandal
2014	—	`conf`	A novel architecture for QPSK modulation based on time-mode signal processing. VDAT Sumit Saha, Bapi Kar, Susmita Sur-Kolay
2014	Misc	`conf`	Global Routing Using Monotone Staircases with Minimal Bends. VLSID Bapi Kar, Susmita Sur-Kolay, Chittaranjan A. Mandal
2013	—	`conf`	STAIRoute: Global routing using monotone staircase channels. ISVLSI Bapi Kar, Susmita Sur-Kolay, Chittaranjan A. Mandal
2012	—	`conf`	A Faster Hierarchical Balanced Bipartitioner for VLSI Floorplans Using Monotone Staircase Cuts. VDAT Bapi Kar, Susmita Sur-Kolay, Sridhar H. Rangarajan, Chittaranjan A. Mandal