Balwinder Raj

26 papers Journal 15Unranked 9
YearRankTypeTitle / Venue / Authors
2025 J jnl
FPGA Implementation of Hybrid ECG Compression and Decompression Method to Improve the Compression Ratio.
J. Circuits Syst. Comput.
G. Erna, Varshith Pelluru, Shreyas Shetty, Banoth Krishna, Balwinder Raj
2025 J jnl
OFETs Electric Characteristics with Different Organic Materials for Low-Power Flexible Electronics Design.
J. Circuits Syst. Comput.
Parminder Kaur, Balwant Raj, Shashi Bala, Balwinder Raj
2025 J jnl
Performance Analysis of Spin Orbit Torque Magneto-Resistive RAM Caches in 4-core ARM Systems.
J. Circuits Syst. Comput.
Inderjit Singh, Balwinder Raj, Mamta Khosla
2023 J jnl
Design and simulation of junctionless nanowire tunnel field effect transistor for highly sensitive biosensor.
Microelectron. J.
Parveen Kumar, Balwinder Raj
2022 J jnl
Spintronics Based Non-Volatile MRAM for Intelligent Systems: Memory for Intelligent Systems Design.
Int. J. Semantic Web Inf. Syst.
Parul Sharma, Balwinder Raj, Sandeep Singh Gill
2021 J jnl
Comparative radio-frequency and crosstalk analysis of carbon-based nano-interconnects.
IET Circuits Devices Syst.
Manjit Kaur, Neena Gupta, Sanjeev Kumar, Balwinder Raj, Arun K. Singh
2021 J jnl
Design and simulation of triple metal double-gate germanium on insulator vertical tunnel field effect transistor.
Microelectron. J.
Tulika Chawla, Mamta Khosla, Balwinder Raj
2020 — ch.
SOI FinFET for Computer Networks and Cyber Security Systems.
Handbook of Computer Networks and Cyber Security
Neeraj Jain, Balwinder Raj
2019 J jnl
A low leakage TG-CNTFET-based inexact full adder for low power image processing applications.
Int. J. Circuit Theory Appl.
Candy Goyal, Jagpal Singh Ubhi, Balwinder Raj
2019 J jnl
Design and Investigation of 7T2M-NVSRAM With Enhanced Stability and Temperature Impact on Store/Restore Energy.
IEEE Trans. Very Large Scale Integr. Syst.
Jeetendra Singh, Balwinder Raj
2019 J jnl
Design and analysis of dynamically configurable electrostatic doped carbon nanotube tunnel FET.
Microelectron. J.
Amandeep Singh, Mamta Khosla, Balwinder Raj
2019 — ch.
IoT-Based Ambient Intelligence Microcontroller for Remote Temperature Monitoring.
Guide to Ambient Intelligence in the IoT Environment
Balwinder Raj, Jeetendra Singh, Santosh Kumar Vishvakarma, Shailesh Singh Chouhan
2018 J jnl
Fault-tolerant design and analysis of QCA-based circuits.
IET Circuits Devices Syst.
Gurmohan Singh, Balwinder Raj, Rakesh Kumar Sarin
2017 J jnl
Design and analysis of area efficient QCA based reversible logic gates.
Microprocess. Microsystems
Gurmohan Singh, Rakesh Kumar Sarin, Balwinder Raj
2016 J jnl
A Gaussian approach for analytical subthreshold current model of cylindrical nanowire FET with quantum mechanical effects.
Microelectron. J.
Sanjeev Kumar Sharma, Balwinder Raj, Mamta Khosla
2016 — conf
CNTFET modeling and low power SRAM cell design.
GCCE
Amandeep Singh, Mamta Khosla, Balwinder Raj
2015 — conf
Comparative analysis of carbon nanotube field effect transistors.
GCCE
Amandeep Singh, Mamta Khosla, Balwinder Raj
2015 — conf
Modeling of DG-Tunnel FET for low power VLSI circuit design.
IC3
Sunil Kumar, Balwinder Raj
2015 — conf
Performance enhancement of junctionless nanowire FET with laterally graded channel doping and high-K spacers.
GCCE
Sanjeev Kumar Sharma, Balwinder Raj, Mamta Khosla
2015 — conf
Thermally aware modeling and performance for MWCNT bundle as VLSI interconnects for high performance integrated circuits.
GCCE
Karmjit Singh Sandha, Balwinder Raj
2014 J jnl
PVT variations aware low leakage INDEP approach for nanoscale CMOS circuits.
Microelectron. Reliab.
Vijay Kumar Sharma, Manisha Pattanaik, Balwinder Raj
2012 — conf
Analyzing Different Mode FinFET Based Memory cell at different power supply for Leakage Reduction.
BIC-TA (2)
Sushil Bhushan, Saurabh Khandelwal, Balwinder Raj
2012 — conf
Signal Stepping Based Multimode Multi-threshold CMOS Technique for Ground Bounce Noise Reduction in Static CMOS Adders.
ISED
Shashikant Sharma, Manisha Pattanaik, Balwinder Raj
2011 J jnl
Process Variation Tolerant FinFET Based Robust Low Power SRAM Cell Design at 32 nm Technology.
J. Low Power Electron.
Balwinder Raj, Jatin Mitra, Deepak Kumar Bihani, V. Rangharajan, Ashok K. Saxena, Sudeb Dasgupta
2011 — conf
Quantum Mechanical Analytical Drain Current Modeling and Simulation for Double Gate FinFET Device Using Quasi Fermi Potential Approach.
SocProS (2)
Balwinder Raj, Ashok K. Saxena, Sudeb Dasgupta
2010 — conf
Quantum Inversion Charge and Drain Current Analysis for Double Gate FinFET Device: Analytical Modeling and TCAD Simulation Approach.
EMS
Balwinder Raj, Ashok K. Saxena, Sudeb Dasgupta