Balaram Sinharoy

30 papers A* 4A 1Journal 18Unranked 6
YearRankTypeTitle / Venue / Authors
2021 A* conf
Energy Efficiency Boost in the AI-Infused POWER10 Processor.
ISCA
Brian W. Thompto, Dung Q. Nguyen, José E. Moreira, Ramon Bertran, Hans M. Jacobson, Richard J. Eickemeyer, Rahul M. Rao, Michael Goulet, Marcy Byers, Christopher J. Gonzalez, Karthik Swaminathan, Nagu R. Dhanwada, Silvia M. Müller, Andreas Wagner, Satish Kumar Sadasivam, Robert K. Montoye, William J. Starke, Christian G. Zoellin, Michael S. Floyd, Jeffrey Stuecheli, Nandhini Chandramoorthy, John-David Wellman, Alper Buyuktosunoglu, Matthias Pflanz, Balaram Sinharoy, Pradip Bose
2015 J jnl
Advanced features in IBM POWER8 systems.
IBM J. Res. Dev.
Balaram Sinharoy, Randal C. Swanberg, Naresh Nayar, Bruce G. Mealey, Jeffrey Stuecheli, Berni Schiefer, Jens Leenstra, Joefon Jann, P. Oehler, D. Levitan, S. Eisen, D. Sanner, Thomas Pflueger, Cédric Lichtenau, W. E. Hall, T. Block
2015 J jnl
IBM POWER8 processor core microarchitecture.
IBM J. Res. Dev.
Balaram Sinharoy, James Van Norstrand, Richard J. Eickemeyer, Hung Q. Le, Jens Leenstra, Dung Q. Nguyen, B. Konigsburg, K. Ward, M. D. Brown, José E. Moreira, D. Levitan, S. Tung, David Hrusecky, James W. Bishop, Michael Gschwind, Maarten Boersma, Michael Kroener, Markus Kaltenbach, Tejas Karkhanis, K. M. Fernsler
2014 — conf
The POWER8
ICICDT
Joshua Friedrich, Hung Q. Le, William J. Starke, Jeff Stuecheli, Balaram Sinharoy, Eric J. Fluhr, Daniel M. Dreps, Victor V. Zyuban, Gregory S. Still, Christopher J. Gonzalez, David Hogenmiller, Frank Malgioglio, Ryan Nett, Ruchir Puri, Phillip J. Restle, David Shan, Zeynep Toprak Deniz, Dieter F. Wendel, Matthew M. Ziegler, Dave W. Victor
2011 J jnl
POWER7™, a Highly Parallel, Scalable Multi-Core High End Server Processor.
IEEE J. Solid State Circuits
Dieter F. Wendel, Ronald N. Kalla, James D. Warnock, Robert Cargnoni, Sam G. Chu, Joachim G. Clabes, Daniel Dreps, David Hrusecky, Joshua Friedrich, Md. Saiful Islam, James A. Kahle, Jens Leenstra, Gaurav Mittal, Jose Paredes, Juergen Pille, Phillip J. Restle, Balaram Sinharoy, George Smith, William J. Starke, Scott A. Taylor, James Van Norstrand, Stephen Weitzel, Phillip G. Williams, Victor V. Zyuban
2010 J jnl
Power7: IBM's Next-Generation Server Processor.
IEEE Micro
Ronald N. Kalla, Balaram Sinharoy, William J. Starke, Michael S. Floyd
2010 — conf
The implementation of POWER7
ISSCC
Dieter F. Wendel, Ronald N. Kalla, Robert Cargnoni, Joachim G. Clabes, Joshua Friedrich, Roland Frech, James A. Kahle, Balaram Sinharoy, William J. Starke, Scott A. Taylor, Steve Weitzel, Sam G. Chu, Md. Saiful Islam, Victor V. Zyuban
2009 A* conf
POWER7 multi-core processor design.
MICRO
Balaram Sinharoy
2009 — conf
POWER7: IBM's next generation server processor.
Hot Chips Symposium
Ronald N. Kalla, Balaram Sinharoy
2005 J jnl
POWER5 system microarchitecture.
IBM J. Res. Dev.
Balaram Sinharoy, Ronald N. Kalla, Joel M. Tendler, Richard J. Eickemeyer, Jody B. Joyner
2005 A* conf
Stretching the Limits of Clock-Gating Efficiency in Server-Class Processors.
HPCA
Hans M. Jacobson, Pradip Bose, Zhigang Hu, Alper Buyuktosunoglu, Victor V. Zyuban, Richard J. Eickemeyer, Lee Eisen, John Griswell, Doug Logan, Balaram Sinharoy, Joel M. Tendler
2004 A* conf
Design and implementation of the POWER5 microprocessor.
DAC
Joachim G. Clabes, Joshua Friedrich, Mark Sweet, Jack DiLullo, Sam G. Chu, Donald W. Plass, James Dawson, Paul Muench, Larry Powell, Michael S. Floyd, Balaram Sinharoy, Mike Lee, Michael Goulet, James Wagoner, Nicole S. Schwartz, Stephen L. Runyon, Gary Gorman, Phillip J. Restle, Ronald N. Kalla, Joseph McGill, J. Steve Dodson
2004 J jnl
IBM Power5 Chip: A Dual-Core Multithreaded Processor.
IEEE Micro
Ronald N. Kalla, Balaram Sinharoy, Joel M. Tendler
2002 A conf
A microarchitectural-level step-power analysis tool.
ISLPED
Wael El-Essawy, David H. Albonesi, Balaram Sinharoy
2002 J jnl
POWER4 system microarchitecture.
IBM J. Res. Dev.
Joel M. Tendler, J. Steve Dodson, J. S. Fields Jr., Hung Q. Le, Balaram Sinharoy
1999 J jnl
Compiler optimization to improve data locality for processor multithreading.
Sci. Program.
Balaram Sinharoy
1997 J jnl
Introduction: Special Issue on Optimising Compilers for Parallel Languages.
Parallel Algorithms Appl.
Balaram Sinharoy, Boleslaw K. Szymanski
1997 J jnl
Optimized Thread Creation for Processor Multithreading.
Comput. J.
Balaram Sinharoy
1997 J jnl
Parallelising Compilers and Systems.
Parallel Algorithms Appl.
Balaram Sinharoy, Boleslaw K. Szymanski
1996 — conf
Improving Software MP Efficiency for Shared Memory Systems.
HICSS (1)
Balaram Sinharoy, Rama Govindaraju
1996 — ed.
Languages, Compilers and Run-Time Systems for Scalable Computers, Third Workshop, LCR 1995, Troy, NY, USA, May 1995
LCR
Boleslaw K. Szymanski, Balaram Sinharoy
1995 J jnl
Announcement of a Special Issue of the Journal of Parallel Algorithms and Applications on Optimising Compilers for Parallel Languages.
Parallel Algorithms Appl.
Balaram Sinharoy, Boleslaw K. Szymanski
1995 — conf
Compiling for Multithreaded Multicomputer.
LCR
Balaram Sinharoy
1995 J jnl
Simultaneous Parallel Reduction on SIMD Machines.
Parallel Process. Lett.
Boleslaw K. Szymanski, William Maniatty, Balaram Sinharoy
1994 J jnl
Compiler Technology for Parallel Scientific Computation.
Sci. Program.
Can C. Özturan, Balaram Sinharoy, Boleslaw K. Szymanski
1994 J jnl
Data and Task Alignment in Distributed Memory Architectures.
J. Parallel Distributed Comput.
Balaram Sinharoy, Boleslaw K. Szymanski
1994 J jnl
Finding Optimum Wavefront of Parallel Computation.
Parallel Algorithms Appl.
Balaram Sinharoy, Boleslaw K. Szymanski
1992 J jnl
Complexity of the Closest Vector Problem in a Lattice Generated by (0, 1)-Matrix.
Inf. Process. Lett.
Boleslaw K. Szymanski, Balaram Sinharoy
1992 J jnl
Corrigenda: Complexity of the Closest Vector Problem in a Lattice Generated by (0, 1)-Matrix.
Inf. Process. Lett.
Boleslaw K. Szymanski, Balaram Sinharoy
1992 — conf
Efficiency of Data Alignment on Maspar.
SIGPLAN Workshop
William Maniatty, Boleslaw K. Szymanski, Balaram Sinharoy