Bahram Rashidi

41 papers Journal 40Unranked 1

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	Area-efficient and high-performance approximate multiplier based on approximate 4:2 compressors. Integr. Bahram Rashidi
2025	J	`jnl`	A Compact 16-bit S-box over Tower Field \mathbb{F} CoRR Bahram Rashidi, Behrooz Khadem
2025	J	`jnl`	A High Secure Image Encryption Method Based on an Efficient and Low-Cost Cryptographic System. Secur. Priv. Bahram Rashidi
2025	J	`jnl`	High-Performance Hardware Structure of ChaCha20 Stream Cipher Based on Sparse Parallel Prefix Adder. Int. J. Circuit Theory Appl. Bahram Rashidi
2025	J	`jnl`	High-performance and non-contact energy harvesters from high-voltage power lines magnetic fields. Comput. Electr. Eng. Bahram Rashidi
2024	J	`jnl`	APPAs: fast and efficient approximate parallel prefix adders and multipliers. J. Supercomput. Bahram Rashidi
2024	J	`jnl`	An Image Encryption Method Based on a High-performance and Efficient Block Cipher. J. Signal Process. Syst. Bahram Rashidi
2024	J	`jnl`	Efficient and low-cost approximate multipliers for image processing applications. Integr. Bahram Rashidi
2024	J	`jnl`	Fault-tolerant and error-correcting 4-bit S-boxes for cryptography applications with multiple errors detection. J. Supercomput. Bahram Rashidi
2023	J	`jnl`	Error-correcting cryptographic S-boxes with multiple error detection and correction. Int. J. Circuit Theory Appl. Bahram Rashidi
2023	J	`jnl`	Lightweight Cryptographic S-Boxes Based on Efficient Hardware Structures for Block Ciphers. ISC Int. J. Inf. Secur. Bahram Rashidi
2022	J	`jnl`	Glitch-less hardware implementation of block ciphers based on an efficient glitch filter. Integr. Bahram Rashidi
2021	J	`jnl`	Compact and efficient structure of 8-bit S-box for lightweight cryptography. Integr. Bahram Rashidi
2021	J	`jnl`	Efficient full data-path width and serialized hardware structures of SPONGENT lightweight hash function. Microelectron. J. Bahram Rashidi
2021	J	`jnl`	Flexible and high-throughput structures of Camellia block cipher for security of the Internet of Things. IET Comput. Digit. Tech. Bahram Rashidi
2021	J	`jnl`	Lightweight 8-bit S-box and combined S-box/S-box-1 for cryptographic applications. Int. J. Circuit Theory Appl. Bahram Rashidi
2020	J	`jnl`	Efficient and flexible hardware structures of the 128 bit CLEFIA block cipher. IET Comput. Digit. Tech. Bahram Rashidi
2020	J	`jnl`	Flexible structures of lightweight block ciphers PRESENT, SIMON and LED. IET Circuits Devices Syst. Bahram Rashidi
2020	J	`jnl`	Low-cost and two-cycle hardware structures of PRINCE lightweight block cipher. Int. J. Circuit Theory Appl. Bahram Rashidi
2020	J	`jnl`	Throughput/Area Efficient Implementation of Scalable Polynomial Basis Multiplication. J. Hardw. Syst. Secur. Bahram Rashidi
2019	J	`jnl`	Efficient Lightweight Hardware Structures of Point Multiplication on Binary Edwards Curves for Elliptic Curve Cryptosystems. J. Circuits Syst. Comput. Bahram Rashidi, Mohammad Abedini
2019	J	`jnl`	Efficient and high-throughput application-specific integrated circuit implementations of HIGHT and PRESENT block ciphers. IET Circuits Devices Syst. Bahram Rashidi
2019	J	`jnl`	Efficient hardware structure for extended Euclidean-based inversion over F 2 m. IET Comput. Digit. Tech. Bahram Rashidi
2019	J	`jnl`	High-throughput and flexible ASIC implementations of SIMON and SPECK lightweight block ciphers. Int. J. Circuit Theory Appl. Bahram Rashidi
2019	J	`jnl`	High-throughput and lightweight hardware structures of HIGHT and PRESENT block ciphers. Microelectron. J. Bahram Rashidi
2018	J	`jnl`	Efficient hardware implementations of point multiplication for binary Edwards curves. Int. J. Circuit Theory Appl. Bahram Rashidi
2017	J	`jnl`	A Survey on Hardware Implementations of Elliptic Curve Cryptosystems. CoRR Bahram Rashidi
2017	J	`jnl`	Efficient and low-complexity hardware architecture of Gaussian normal basis multiplication over GF(2 IET Circuits Devices Syst. Bahram Rashidi, Sayed Masoud Sayedi, Reza Rezaeian Farashahi
2017	J	`jnl`	Full-custom hardware implementation of point multiplication on binary Edwards curves for application-specific integrated circuit elliptic curve cryptosystem applications. IET Circuits Devices Syst. Bahram Rashidi, Sayed Masoud Sayedi, Reza Rezaeian Farashahi
2017	J	`jnl`	High-performance and high-speed implementation of polynomial basis Itoh-Tsujii inversion algorithm over GF(2 IET Inf. Secur. Bahram Rashidi, Reza Rezaeian Farashahi, Sayed Masoud Sayedi
2017	J	`jnl`	High-speed Hardware Implementations of Point Multiplication for Binary Edwards and Generalized Hessian Curves. IACR Cryptol. ePrint Arch. Bahram Rashidi, Reza Rezaeian Farashahi, Sayed Masoud Sayedi
2017	J	`jnl`	High-speed hardware implementation of Gaussian normal basis inversion algorithm over F Microelectron. J. Bahram Rashidi
2016	J	`jnl`	An efficient and high-speed VLSI implementation of optimal normal basis multiplication over GF(2 Integr. Bahram Rashidi, Sayed Masoud Sayedi, Reza Rezaeian Farashahi
2016	J	`jnl`	Efficient implementation of bit-parallel fault tolerant polynomial basis multiplication and squaring over GF(2 IET Comput. Digit. Tech. Bahram Rashidi, Sayed Masoud Sayedi, Reza Rezaeian Farashahi
2016	J	`jnl`	High-speed VLSI implementation of Digit-serial Gaussian normal basis Multiplication over GF(2m). IACR Cryptol. ePrint Arch. Bahram Rashidi, Sayed Masoud Sayedi, Reza Rezaeian Farashahi
2016	J	`jnl`	High-speed hardware architecture of scalar multiplication for binary elliptic curve cryptosystems. Microelectron. J. Bahram Rashidi, Sayed Masoud Sayedi, Reza Rezaeian Farashahi
2015	J	`jnl`	Efficient and Low-complexity Hardware Architecture of Gaussian Normal Basis Multiplication over GF(2m) for Elliptic Curve Cryptosystems. IACR Cryptol. ePrint Arch. Bahram Rashidi, Sayed Masoud Sayedi, Reza Rezaeian Farashahi
2015	J	`jnl`	Efficient implementation of low time complexity and pipelined bit-parallel polynomial basis multiplier over binary finite fields. ISC Int. J. Inf. Secur. Bahram Rashidi, Reza Rezaeian Farashahi, Sayed Masoud Sayedi
2014	J	`jnl`	FPGA based fast and high-throughput 2-slow retiming 128-bit AES encryption algorithm. Microelectron. J. Reza Rezaeian Farashahi, Bahram Rashidi, Sayed Masoud Sayedi
2014	—	`conf`	High-speed and pipelined finite field bit-parallel multiplier over GF(2 ISCISC Bahram Rashidi, Reza Rezaeian Farashahi, Sayed Masoud Sayedi
2013	J	`jnl`	High performance and low-power finite impulse response filter based on ring topology with modified retiming serial multiplier on FPGA. IET Signal Process. Bahram Rashidi