Baher Haroun

36 papers A 3C 7Journal 12Unranked 14
YearRankTypeTitle / Venue / Authors
2024 — conf
A Sub-THz CMOS Transceiver IC and System for Medium-Reach Guided Wave and Short-Reach Wireless Communication Links.
MWSCAS
Swaminathan Sankaran, Gerd Schuppener, Juan Herbsommer, Bradley Kramer, Hassan Ali, Robert Payne, Carole Rush, Baher Haroun, Nirmal Warke
2023 — conf
A 0.5-to-400MHz Programmable BAW Oscillator with Fractional Output Divider Achieving 4ppm Frequency Stability over Temperature and <95fs Jitter.
ISSCC
Subhashish Mukherjee, Yogesh Darwhekar, Jayawardan Janardhanan, Peeyoosh Mirajkar, Raghavendra Reddy, Harish Ramesh, Bichoy Bahr, Jagdish Chand, Uday Meda, Baher Haroun, Shankar Karantha, Ernest Ting-Ta Yen, Keegan Martin, Daniel Gan, Amin Sijelmassi, Sankaran Aniruddhan
2023 C conf
High-Linearity High-Bandwidth (>20GHz) T&H Front Ends Using Active Bootstrapping and Heterogeneous SiGe/CMOS Circuit Co-Design.
ISCAS
Athanasios Ramkaj, Michael Perrott, Baher Haroun, Boris Murmann
2022 J jnl
A Duty-Cycled Integrated-Fluxgate Magnetometer for Current Sensing.
IEEE J. Solid State Circuits
Preet Garcha, Viola Schaffer, Baher Haroun, Srinath Ramaswamy, Jim Wieser, Jeffrey H. Lang, Anantha P. Chandrakasan
2022 J jnl
A Sub-100 Fs RMS
IEEE J. Solid State Circuits
Sachin Kalia, Salvatore Finocchiaro, Tolga Dinc, Bichoy Bahr, Ashwin Raghunathan, Gerd Schuppener, Siraj Akhtar, Tobias Fritz, Baher Haroun, Benjamin Cook, Swaminathan Sankaran
2022 J jnl
High-Efficiency Class-E Power Amplifiers for mmWave Radar Sensors: Design and Implementation.
IEEE J. Solid State Circuits
Tolga Dinc, Sachin Kalia, Siraj Akhtar, Baher Haroun, Benjamin Cook, Swaminathan Sankaran
2021 — conf
A 770 kS/s Duty-Cycled Integrated-Fluxgate Magnetometer for Contactless Current Sensing.
ISSCC
Preet Garcha, Viola Schaffer, Baher Haroun, Srinath Ramaswamy, Jim Wieser, Jeffrey H. Lang, Anantha P. Chandrakasan
2021 — conf
An Ultra-Low Close-In Phase Noise Series-Resonance BAW Oscillator in a 130-nm BiCMOS process.
A-SSCC
Sachin Kalia, Bichoy Bahr, Tolga Dinc, Baher Haroun, Swaminathan Sankaran
2020 — conf
3.1 An Integrated BAW Oscillator with <±30ppm Frequency Stability Over Temperature, Package Stress, and Aging Suitable for High-Volume Production.
ISSCC
Danielle Griffith, Ernest Ting-Ta Yen, Kaichien Tsai, Habeeb Ur Rahman Mohammed, Baher Haroun, Ali Kiaei, Ahmad Bahai
2018 — conf
Autonomous Vehicles SEnsor Needs.
ESSDERC
Baher Haroun
2018 — conf
Autonomous Vehicles Sensor Needs.
ESSCIRC
Baher Haroun
2017 J jnl
A 29.5 dBm Class-E Outphasing RF Power Amplifier With Efficiency and Output Power Enhancement Circuits in 45nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap.
Aritra Banerjee, Rahmi Hezar, Lei Ding, Baher Haroun
2015 J jnl
A 25 dBm Outphasing Power Amplifier With Cross-Bridge Combiners.
IEEE J. Solid State Circuits
Lei Ding, Joonhoi Hur, Aritra Banerjee, Rahmi Hezar, Baher Haroun
2015 J jnl
A PWM Based Fully Integrated Digital Transmitter/PA for WLAN and LTE Applications.
IEEE J. Solid State Circuits
Rahmi Hezar, Lei Ding, Aritra Banerjee, Joonhoi Hur, Baher Haroun
2014 J jnl
A 160 GHz Pulsed Radar Transceiver in 65 nm CMOS.
IEEE J. Solid State Circuits
Brian P. Ginsburg, Srinath Ramaswamy, Vijay Rentala, Eunyoung Seok, Swaminathan Sankaran, Baher Haroun
2014 — conf
A 29.5 dBm class-E outphasing RF power amplifier with performance enhancement circuits in 45nm CMOS.
ESSCIRC
Aritra Banerjee, Rahmi Hezar, Lei Ding, Nathan Schemm, Baher Haroun
2013 J jnl
Architectures and Circuit Techniques for Multi-Purpose Digital Phase Lock Loops.
IEEE Trans. Circuits Syst. I Regul. Pap.
Krishnaswamy Nagaraj, Anant S. Kamath, Karthik Subburaj, Biman Chattopadhyay, Gopalkrishna Nayak, Satyasai Evani, Neeraj P. Nayak, Indu Prathapan, Frank Zhang, Baher Haroun
2012 — conf
A 20mW 61dB SNDR (60MHz BW) 1b 3
ISSCC
Venkatesh Srinivasan, Victoria Wang, Patrick Satarzadeh, Baher Haroun, Marco Corsi
2012 — conf
Low power ADC's for wireless communications.
MWSCAS
Vijay Rentala, Venkatesh Srinivasan, Victoria Wang, Srinath Ramaswamy, Baher Haroun, Marco Corsi
2012 — conf
Session 16 overview: Switching power control techniques: Analog subcommittee.
ISSCC
Baher Haroun, Gyu-Hyeong Cho
2010 — conf
A 0.16mm
ISSCC
Yogesh K. Ramadass, Ayman A. Fayed, Baher Haroun, Anantha P. Chandrakasan
2010 — conf
A 110dB SNR and 0.5mW current-steering audio DAC implemented in 45nm CMOS.
ISSCC
Rahmi Hezar, Lars Risbo, Halil Kiper, Mounir Fares, Baher Haroun, Gangadhar Burra, Gabriel Gomez
2006 J jnl
A Sigma-Delta ADC with Decimation and Gain Control Function for a Bluetooth Receiver in 130 nm Digital CMOS.
EURASIP J. Wirel. Commun. Netw.
Jinseok Koh, Gabriel Gomez, Khurram Muhammad, Robert Bogdan Staszewski, Baher Haroun
2002 — conf
A Robust Digital Delay Line Architecture in a 0.13µm CMOS Technology Node for Reduced Design and Process Sensitivities.
ISQED
Prasun Raha, Scott Randall, Richard Jennings, Bob Helmick, Ajith Amerasekera, Baher Haroun
2002 J jnl
An embedded 0.8 V/480 μW 6b/22 MHz flash ADC in 0.13-μm digital CMOS process using a nonlinear double interpolation technique.
IEEE J. Solid State Circuits
Jerry (Heng-Chih) Lin, Baher Haroun
1995 C conf
Floorplanning with Datapath Optimization.
ISCAS
Abdelhakim Safir, Baher Haroun, Krishnaiyan Thulasiraman
1995 A conf
Synthesis of Signal Processing Structured Datapaths for FPGAs Supporting RAMs and Busses.
FPGA
Baher Haroun, Behzad Sajjadi
1994 C conf
A Floorplanner driven by Structural & Timing Constraints.
ISCAS
Abdelhakim Safir, Baher Haroun, Krishnaiyan Thulasiraman
1994 C conf
A Novel Reduced Swing CMOS Bus Interface Circuit for High Speed Low Power VLSI Systems.
ISCAS
Reza Golshan, Baher Haroun
1994 C conf
A Two Stage Structure for High Order Multi-Bit Sigma-Delta ADC with Multiplier-less Digital Correction Logic.
ISCAS
Baher Haroun, Chao Hua Wu
1994 C conf
Optimal Datapath Synthesis of Partitioned Signal Processing Algorithm for Multiple FPGAs.
ICCD
Baher Haroun, Behzard Sajjadi
1992 A conf
Power estimation tool for sub-micron CMOS VLSI circuits.
ICCAD
F. Rouatbi, Baher Haroun, Asim J. Al-Khalili
1992 C conf
Synthesis of Multiple Bus/Functional Unit Architectures Implementing Neural Networks.
ICCD
Baher Haroun, Elie Torbey
1989 J jnl
Architectural synthesis for DSP silicon compilers.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Baher Haroun, Mohamed I. Elmasry
1989 J jnl
SPAID: an architectural synthesis tool for DSP custom applications.
IEEE J. Solid State Circuits
Baher Haroun, Mohamed I. Elmasry
1988 A conf
Automatic synthesis of a multi-bus architecture for DSP.
ICCAD
Baher Haroun, Mohamed I. Elmasry