Bahar Asgari - RankMe

50 papers A* 11A 2B 4C 2Misc 1Journal 21Unranked 8

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	Arcalis: Accelerating Remote Procedure Calls Using a Lightweight Near-Cache Solution. CoRR Johnson Umeike, Pongstorn Maidee, Bahar Asgari
2026	J	`jnl`	Tureis: Transformer-based Unified Resilience for IoT Devices in Smart Homes. CoRR Alireza Borhani, Vafa Andalibi, Bahar Asgari
2025	—	`conf`	Belenos: Bottleneck Evaluation to Link Biomechanics to Novel Computing Optimizations. IISWC Hana Chitsaz, Johnson Umeike, Amirmahdi Namjoo, Babak N. Safa, Bahar Asgari
2025	J	`jnl`	Belenos: Bottleneck Evaluation to Link Biomechanics to Novel Computing Optimizations. CoRR Hana Chitsaz, Johnson Umeike, Amirmahdi Namjoo, Babak N. Safa, Bahar Asgari
2025	A*	`conf`	Bootes: Boosting the Efficiency of Sparse Accelerators Using Spectral Clustering. MICRO Sanjali Yadav, Bahar Asgari
2025	A*	`conf`	Chasoň: Supporting Cross HBM Channel Data Migration to Enable Efficient Sparse Algebraic Acceleration. MICRO Ubaid Bakhtiar, Amirmahdi Namjoo, Bahar Asgari
2025	A*	`conf`	Coruscant: Co-Designing GPU Kernel and Sparse Tensor Core to Advocate Unstructured Sparsity in Efficient LLM Inference. MICRO Donghyeon Joo, Helya Hosseini, Ramyad Hadidi, Bahar Asgari
2025	J	`jnl`	DynaFlow: An ML Framework for Dynamic Dataflow Selection in SpGEMM Accelerators. IEEE Comput. Archit. Lett. Sanjali Yadav, Bahar Asgari
2025	J	`jnl`	Electra: Eliminating the Ineffectual Computations on Bitmap Compressed Matrices. IEEE Comput. Archit. Lett. Chaithanya Krishna Vadlamudi, Bahar Asgari
2025	B	`conf`	La Superba: Leveraging a Self-Comparison Method to Understand the Performance Benefits of Sparse Acceleration Optimizations. ISPASS Nebil Ozer, Gregory Kollmer, Ramyad Hadidi, Bahar Asgari
2025	A*	`conf`	Misam: Machine Learning Assisted Dataflow Selection in Accelerators for Sparse Matrix Multiplication. MICRO Sanjali Yadav, Amirmahdi Namjoo, Bahar Asgari
2025	J	`jnl`	Mustafar: Promoting Unstructured Sparsity for KV Cache Pruning in LLM Inference. CoRR Donghyeon Joo, Helya Hosseini, Ramyad Hadidi, Bahar Asgari
2025	A*	`conf`	Pipirima: Predicting Patterns in Sparsity to Accelerate Matrix Algebra. DAC Ubaid Bakhtiar, Donghyeon Joo, Bahar Asgari
2025	J	`jnl`	Segin: Synergistically Enabling Fine-Grained Multi-Tenant and Resource Optimized SpMV. IEEE Comput. Archit. Lett. Helya Hosseini, Ubaid Bakhtiar, Donghyeon Joo, Bahar Asgari
2024	A*	`conf`	Acamar: A Dynamically Reconfigurable Scientific Computing Accelerator for Robust Convergence and Minimal Resource Underutilization. MICRO Ubaid Bakhtiar, Helya Hosseini, Bahar Asgari
2024	J	`jnl`	Endor: Hardware-Friendly Sparse Format for Offloaded LLM Inference. CoRR Donghyeon Joo, Ramyad Hadidi, Soheil Feizi, Bahar Asgari
2024	—	`conf`	GUST: Graph Edge-Coloring Utilization for Accelerating Sparse Matrix Vector Multiplication. ASPLOS (4) Armin Gerami, Bahar Asgari
2024	J	`jnl`	GUST: Graph Edge-Coloring Utilization for Accelerating Sparse Matrix Vector Multiplication. CoRR Armin Gerami, Bahar Asgari
2024	J	`jnl`	Misam: Using ML in Dataflow Selection of Sparse-Sparse Matrix Multiplication. CoRR Sanjali Yadav, Bahar Asgari
2023	—	`conf`	Context-Aware Task Handling in Resource-Constrained Robots with Virtualization. EDGE Ramyad Hadidi, Nima Shoghi Ghaleshahi, Bahar Asgari, Hyesoon Kim
2023	—	`conf`	Creating Robust Deep Neural Networks with Coded Distributed Computing for IoT. EDGE Ramyad Hadidi, Jiashen Cao, Bahar Asgari, Hyesoon Kim
2023	C	`conf`	Memory-Based Computing for Energy-Efficient AI: Grand Challenges. VLSI-SoC Foroozan Karimzadeh, Mohsen Imani, Bahar Asgari, Ningyuan Cao, Yingyan Lin, Yan Fang
2023	—	`conf`	Spica: Exploring FPGA Optimizations to Enable an Efficient SpMV Implementation for Computations at Edge. EDGE Dheeraj Ramchandani, Bahar Asgari, Hyesoon Kim
2022	B	`conf`	Maia: Matrix Inversion Acceleration Near Memory. FPL Bahar Asgari, Dheeraj Ramchandani, Amaan Marfatia, Hyesoon Kim
2021	J	`jnl`	Context-Aware Task Handling in Resource-Constrained Robots with Virtualization. CoRR Ramyad Hadidi, Nima Shoghi Ghaleshahi, Bahar Asgari, Hyesoon Kim
2021	—	`conf`	Copernicus: Characterizing the Performance Implications of Compression Formats Used in Sparse Workloads. IISWC Bahar Asgari, Ramyad Hadidi, Joshua Dierberger, Charlotte Steinichen, Amaan Marfatia, Hyesoon Kim
2021	—	`—`	Efficiently Accelerating Sparse Problems by Enabling Stream Accesses to Memory using Hardware/Software Techniques. Bahar Asgari
2021	J	`jnl`	Efficiently Solving Partial Differential Equations in a Partially Reconfigurable Specialized Hardware. IEEE Trans. Computers Bahar Asgari, Ramyad Hadidi, Tushar Krishna, Hyesoon Kim, Sudhakar Yalamanchili
2021	A*	`conf`	FAFNIR: Accelerating Sparse Gathering by Using Efficient Near-Memory Intelligent Reduction. HPCA Bahar Asgari, Ramyad Hadidi, Jiashen Cao, Da Eun Shim, Sung Kyu Lim, Hyesoon Kim
2021	J	`jnl`	MAHASIM: Machine-Learning Hardware Acceleration Using a Software-Defined Intelligent Memory System. J. Signal Process. Syst. Bahar Asgari, Saibal Mukhopadhyay, Sudhakar Yalamanchili
2021	A*	`conf`	Quantifying the design-space tradeoffs in autonomous drones. ASPLOS Ramyad Hadidi, Bahar Asgari, Sam Jijina, Adriana Amyette, Nima Shoghi, Hyesoon Kim
2020	A*	`conf`	ALRESCHA: A Lightweight Reconfigurable Sparse-Computation Accelerator. HPCA Bahar Asgari, Ramyad Hadidi, Tushar Krishna, Hyesoon Kim, Sudhakar Yalamanchili
2020	A	`conf`	ASCELLA: Accelerating Sparse Computation by Enabling Stream Accesses to Memory. DATE Bahar Asgari, Ramyad Hadidi, Hyesoon Kim
2020	J	`jnl`	Copernicus: Characterizing the Performance Implications of Compression Formats Used in Sparse Workloads. CoRR Bahar Asgari, Ramyad Hadidi, Joshua Dierberger, Charlotte Steinichen, Hyesoon Kim
2020	J	`jnl`	Edge-Tailored Perception: Fast Inferencing in-the-Edge with Efficient Model Distribution. CoRR Ramyad Hadidi, Bahar Asgari, Jiashen Cao, Younmin Bae, Hyojong Kim, Michael S. Ryoo, Hyesoon Kim
2020	C	`conf`	MEISSA: Multiplying Matrices Efficiently in a Scalable Systolic Architecture. ICCD Bahar Asgari, Ramyad Hadidi, Hyesoon Kim
2020	A*	`conf`	PISCES: Power-Aware Implementation of SLAM by Customizing Efficient Sparse Algebra. DAC Bahar Asgari, Ramyad Hadidi, Nima Shoghi Ghaleshahi, Hyesoon Kim
2020	Misc	`conf`	Proposing a Fast and Scalable Systolic Array for Matrix Multiplication. FCCM Bahar Asgari, Ramyad Hadidi, Hyesoon Kim
2019	B	`conf`	Capella: Customizing Perception for Edge Devices by Efficiently Allocating FPGAs to DNNs. FPL Younmin Bae, Ramyad Hadidi, Bahar Asgari, Jiashen Cao, Hyesoon Kim
2019	—	`conf`	Characterizing the Deployment of Deep Neural Networks on Commercial Edge Devices. IISWC Ramyad Hadidi, Jiashen Cao, Yilun Xie, Bahar Asgari, Tushar Krishna, Hyesoon Kim
2019	J	`jnl`	ERIDANUS: Efficiently Running Inference of DNNs Using Systolic Arrays. IEEE Micro Bahar Asgari, Ramyad Hadidi, Hyesoon Kim, Sudhakar Yalamanchili
2019	A*	`conf`	LODESTAR: Creating Locally-Dense CNNs for Efficient Inference on Systolic Arrays. DAC Bahar Asgari, Ramyad Hadidi, Hyesoon Kim, Sudhakar Yalamanchili
2019	A	`conf`	SuDoku: Tolerating High-Rate of Transient Failures for Enabling Scalable STTRAM. DSN Prashant J. Nair, Bahar Asgari, Moinuddin K. Qureshi
2018	J	`jnl`	Memory Slices: A Modular Building Block for Scalable, Intelligent Memory Systems. CoRR Bahar Asgari, Saibal Mukhopadhyay, Sudhakar Yalamanchili
2018	B	`conf`	Performance Implications of NoCs on 3D-Stacked Memories: Insights from the Hybrid Memory Cube. ISPASS Ramyad Hadidi, Bahar Asgari, Jeffrey S. Young, Burhan Ahmad Mudassar, Kartikay Garg, Tushar Krishna, Hyesoon Kim
2017	J	`jnl`	Demystifying the Characteristics of 3D-Stacked Memories: A Case Study for Hybrid Memory Cube. CoRR Ramyad Hadidi, Bahar Asgari, Burhan Ahmad Mudassar, Saibal Mukhopadhyay, Sudhakar Yalamanchili, Hyesoon Kim
2017	—	`conf`	Demystifying the characteristics of 3D-stacked memories: A case study for Hybrid Memory Cube. IISWC Ramyad Hadidi, Bahar Asgari, Burhan Ahmad Mudassar, Saibal Mukhopadhyay, Sudhakar Yalamanchili, Hyesoon Kim
2017	J	`jnl`	Micro-architectural approach to the efficient employment of STTRAM cells in a microprocessor register file. IET Comput. Digit. Tech. Bahar Asgari, Mahdi Fazeli, Ahmad Patooghy, Seyed Vahid Azhari
2017	J	`jnl`	Performance Implications of NoCs on 3D-Stacked Memories: Insights from the Hybrid Memory Cube. CoRR Ramyad Hadidi, Bahar Asgari, Jeffrey S. Young, Burhan Ahmad Mudassar, Kartikay Garg, Tushar Krishna, Hyesoon Kim
2017	J	`jnl`	Single event multiple upset-tolerant SRAM cell designs for nano-scale CMOS technology. Turkish J. Electr. Eng. Comput. Sci. Ramin Rajaei, Bahar Asgari, Mahmoud Tabandeh, Mahdi Fazeli