Bah-Hwee Gwee - RankMe

140 papers A 1B 1C 54Journal 46Unranked 38

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	DQSA: Dynamic Quantized Self-Attention for Multi-Task Encrypted Network Traffic Classification. IEEE Trans. Inf. Forensics Secur. Yongming Chen, Hongsheng Lan, Bah-Hwee Gwee, Qi Cao, Sirajudeen Gulam Razul, Zhiping Lin
2026	J	`jnl`	Explainable Error Detection in Integrated Circuits Image Segmentation via Graph Neural Networks. Trans. Mach. Learn. Res. Ma Xiaoyu, Jingyang Dai, Feng Ji, Deruo Cheng, Yiqiong Shi, Bah-Hwee Gwee
2026	J	`jnl`	Integrated Circuit Image Synthesis for Unsupervised Circuit Annotation via Shape Consistent Image Translation. IEEE Intell. Syst. Yee-Yang Tee, Xuenong Hong, Deruo Cheng, Tong Lin, Yiqiong Shi, Bah-Hwee Gwee
2025	C	`conf`	A Novel Energy-Efficient Continuous-Time Hysteretic VCO-Based Comparator. ISCAS Jinhen Lee, Victor Adrian, Kinglouis Steven Tantra, Bah-Hwee Gwee, Joseph S. Chang
2025	J	`jnl`	GNNReveal: A Novel Graph-Neural-Network-Based Attack Method for Integrated Circuit Logic Gate Decamouflaging. IEEE Intell. Syst. Xuenong Hong, Yee-Yang Tee, Zilong Hu, Tong Lin, Yiqiong Shi, Deruo Cheng, Bah-Hwee Gwee
2025	C	`conf`	Live Demonstration: An Area and Energy Efficient Reconfigurable Cryptographic Accelerator Based SoC Design for Securing IoT Devices. ISCAS Xvpeng Zhang, Bingqiang Liu, Lingyun Hu, Zixuan Shen, Zaisheng He, Dengke Xu, Bah-Hwee Gwee, Chao Wang
2025	C	`conf`	Long-Short-GNN: A Novel Graph Neural Network for Detecting FPGA IP Circuits for Hardware Assurance. ISCAS Heyi Zhang, Tong Lin, Feng Ji, Deruo Cheng, Yiqiong Shi, Bah-Hwee Gwee
2025	C	`conf`	Multiple Hypothesis Testing for SEM Image Processing: A Case Study on Standard Cell Partition. ISCAS Xiaoyu Ma, Yizhen Li, Feng Ji, Tong Lin, Yiqiong Shi, Deruo Cheng, Bah-Hwee Gwee
2025	C	`conf`	N-MUX: Neighborhood-Based Logic Locking Against Machine Learning Attacks. ISCAS Han Zhang, Xuenong Hong, Shirui Sheng, Juncheng Chen, Nay Aung Kyaw, Kwen-Siong Chong, Zhiping Lin, Bah-Hwee Gwee
2025	C	`conf`	SSRNet: Few-shot IC Segmentation in Automated PCB Image Processing. ISCAS Yuhang Wang, Xinrui Wang, Deruo Cheng, Tong Lin, Feng Ji, Yiqiong Shi, Bah-Hwee Gwee
2024	C	`conf`	A Method for Out-of-Distribution Detection in Encrypted Mobile Traffic Classification. ISCAS Yuzhou Tong, Yongming Chen, Bah-Hwee Gwee, Qi Cao, Sirajudeen Gulam Razul, Zhiping Lin
2024	C	`conf`	A Novel Non-profiling Side-Channel Attack on Masked Devices with Connectivity Matrix. ISCAS Juncheng Chen, Han Zhang, Zishuo Yang, Yicheng Xu, Nay Aung Kyaw, Kwen-Siong Chong, Zhiping Lin, Bah-Hwee Gwee
2024	—	`conf`	A Novel Voltage-Controlled Oscillator Linearized by a Resistorless Dynamic-Degeneration Technique. APCCAS Jinhen Lee, Victor Adrian, Bah-Hwee Gwee, Joseph Sylvester Chang
2024	—	`conf`	An Energy-Efficient and High-Accuracy Spiking Neural Network Utilizing Asynchronous CORDIC for On-FPGA STDP Learning. APCCAS Shirui Sheng, Kwen-Siong Chong, Jun-Sheng Ng, Zhiping Lin, Joseph S. Chang, Bah-Hwee Gwee
2024	J	`jnl`	Integrated Circuit Mask-Generative Adversarial Network for Circuit Annotation With Targeted Data Augmentation. IEEE Intell. Syst. Yee-Yang Tee, Deruo Cheng, Yiqiong Shi, Tong Lin, Bah-Hwee Gwee
2024	C	`conf`	MLConnect: A Machine Learning Based Connection Prediction Framework for Error Correction in Recovered Circuit. ISCAS Xuenong Hong, Zilong Hu, Han Zhang, Yee-Yang Tee, Tong Lin, Yiqiong Shi, Deruo Cheng, Bah-Hwee Gwee
2024	C	`conf`	SAMIC: Segment Anything Model for Integrated Circuit Image Analysis. TENCON Yong-Jian Ng, Yee-Yang Tee, Deruo Cheng, Bah-Hwee Gwee
2024	J	`jnl`	Securing Against Side-Channel Attacks With Wide-Range In Situ Random Voltage Dithering on Async-Logic AES Engine. IEEE Trans. Very Large Scale Integr. Syst. Jun-Sheng Ng, Juncheng Chen, Nay Aung Kyaw, Kwen-Siong Chong, Bah-Hwee Gwee
2024	—	`conf`	Unpaired Synthesis of IC Scanning Electron Microscopy Images with Structural Constraints. IST Luyun Li, Deruo Cheng, Yiqiong Shi, Bah-Hwee Gwee
2023	C	`conf`	A 3D-Printed Fourth-Order Stacked Filter for Integrated DC-DC Converters. ISCAS Jinhen Lee, Victor Adrian, Sun-Yang Tay, Yanshan Xie, Bah-Hwee Gwee, Joseph S. Chang
2023	C	`conf`	A Residual-Remainder Coupled Unlimited Sampling Framework for High Dynamic Range Signal Conversion. ISCAS Zixiang Zhou, Lei Sun, Hangcheng Han, Juncheng Chen, Bah-Hwee Gwee, Zhiping Lin
2023	—	`conf`	Deep-learning-based X-ray CT Slice Analysis for Layout Verification in Printed Circuit Boards. AICAS Deruo Cheng, Yiqiong Shi, Yee-Yang Tee, Jingsi Song, Xue Wang, Bihan Wen, Bah-Hwee Gwee
2023	C	`conf`	GRACER: Graph-Based Standard Cell Recognition in IC Images for Hardware Assurance. IECON Erdong Huang, Xuenong Hong, Tong Lin, Yiqiong Shi, Bah-Hwee Gwee
2023	J	`jnl`	GraphClusNet: A Hierarchical Graph Neural Network for Recovered Circuit Netlist Partitioning. IEEE Trans. Artif. Intell. Xuenong Hong, Tong Lin, Yiqiong Shi, Bah-Hwee Gwee
2023	C	`conf`	Improving FPGA-based Async-logic AES Accelerator with the Integration of Sync-logic Block RAMs. ISCAS Jun-Sheng Ng, Juncheng Chen, Si Wu, Nay Aung Kyaw, Kwen-Siong Chong, Zhiping Lin, Bah-Hwee Gwee
2023	J	`jnl`	Patch-Based Adversarial Training for Error-Aware Circuit Annotation of Delayered IC Images. IEEE Trans. Circuits Syst. II Express Briefs Yee-Yang Tee, Xuenong Hong, Deruo Cheng, Chye-Soon Chee, Yiqiong Shi, Tong Lin, Bah-Hwee Gwee
2023	C	`conf`	Real-time Traffic Classification in Encrypted Wireless Communication Network. ISCAS Yongming Chen, Yuzhou Tong, Bah-Hwee Gwee, Qi Cao, Sirajudeen Gulam Razul, Zhiping Lin
2023	C	`conf`	SEM2GDS: A Deep-Learning Based Framework To Detect Malicious Modifications In IC Layout. ISCAS Tong Lin, Yiqiong Shi, Bah-Hwee Gwee
2022	J	`jnl`	A Highly Secure FPGA-Based Dual-Hiding Asynchronous-Logic AES Accelerator Against Side-Channel Attacks. IEEE Trans. Very Large Scale Integr. Syst. Jun-Sheng Ng, Juncheng Chen, Kwen-Siong Chong, Joseph S. Chang, Bah-Hwee Gwee
2022	C	`conf`	A Versatile and Accurate Vector-Based Method for Modeling and Analyzing Planar Air-Core Inductors. ISCAS Sun-Yang Tay, Victor Adrian, Joseph S. Chang, Jinhen Lee, Bah-Hwee Gwee
2022	C	`conf`	An Asynchronous-Logic Masked Advanced Encryption Standard (AES) Accelerator and its Side-Channel Attack Evaluations. ISCAS Jun-Sheng Ng, Juncheng Chen, Nay Aung Kyaw, Ne Kyaw Zwa Lwin, Kwen-Siong Chong, Joseph S. Chang, Bah-Hwee Gwee
2022	J	`jnl`	Delayered IC image analysis with template-based Tanimoto Convolution and Morphological Decision. IET Circuits Devices Syst. Deruo Cheng, Yiqiong Shi, Tong Lin, Bah-Hwee Gwee, Kar-Ann Toh
2022	—	`conf`	Incremental Linear Regression Attack. AsianHOST Juncheng Chen, Jun-Sheng Ng, Nay Aung Kyaw, Zhili Zou, Kwen-Siong Chong, Zhiping Lin, Bah-Hwee Gwee
2022	C	`conf`	Non-profiling based Correlation Optimization Deep Learning Analysis. ISCAS Juncheng Chen, Jun-Sheng Ng, Nay Aung Kyaw, Ne Kyaw Zwa Lwin, Kwen-Siong Chong, Zhiping Lin, Joseph Sylvester Chang, Bah-Hwee Gwee
2022	J	`jnl`	Unsupervised Domain Adaptation with Histogram-gated Image Translation for Delayered IC Image Analysis. CoRR Yee-Yang Tee, Deruo Cheng, Chye-Soon Chee, Tong Lin, Yiqiong Shi, Bah-Hwee Gwee
2021	J	`jnl`	A Novel Normalized Variance-Based Differential Power Analysis Against Masking Countermeasures. IEEE Trans. Inf. Forensics Secur. Juncheng Chen, Jun-Sheng Ng, Kwen-Siong Chong, Zhiping Lin, Bah-Hwee Gwee
2021	J	`jnl`	A Power-Aware Toggling-Frequency Actuator in Data-Toggling SRAM for Secure Data Protection. IEEE Trans. Circuits Syst. II Express Briefs Weng-Geng Ho, Kwen-Siong Chong, Tony Tae-Hyoung Kim, Bah-Hwee Gwee
2021	J	`jnl`	Dual-Hiding Side-Channel-Attack Resistant FPGA-Based Asynchronous-Logic AES: Design, Countermeasures and Evaluation. IEEE J. Emerg. Sel. Topics Circuits Syst. Kwen-Siong Chong, Jun-Sheng Ng, Juncheng Chen, Ne Kyaw Zwa Lwin, Nay Aung Kyaw, Weng-Geng Ho, Joseph Sylvester Chang, Bah-Hwee Gwee
2021	B	`conf`	Joint Anomaly Detection and Inpainting for Microscopy Images Via Deep Self-Supervised Learning. ICIP Ling Huang, Deruo Cheng, XuLei Yang, Tong Lin, Yiqiong Shi, Kaiyi Yang, Bah-Hwee Gwee, Bihan Wen
2021	C	`conf`	Normalized Differential Power Analysis - for Ghost Peaks Mitigation. ISCAS Juncheng Chen, Jun-Sheng Ng, Nay Aung Kyaw, Ne Kyaw Zwa Lwin, Weng-Geng Ho, Kwen-Siong Chong, Zhiping Lin, Joseph Sylvester Chang, Bah-Hwee Gwee
2020	C	`conf`	A DPA-Resistant Asynchronous-Logic NoC Router with Dual-Supply-Voltage-Scaling for Multicore Cryptographic Applications. ISCAS Weng-Geng Ho, Ne Kyaw Zwa Lwin, Nay Aung Kyaw, Jun-Sheng Ng, Juncheng Chen, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang
2020	C	`conf`	A Highly Efficient Power Model for Correlation Power Analysis (CPA) of Pipelined Advanced Encryption Standard (AES). ISCAS Jun-Sheng Ng, Juncheng Chen, Nay Aung Kyaw, Ne Kyaw Zwa Lwin, Weng-Geng Ho, Kwen-Siong Chong, Bah-Hwee Gwee
2020	C	`conf`	A Secure Data-Toggling SRAM for Confidential Data Protection. ISCAS Weng-Geng Ho, Kwen-Siong Chong, Tony Tae-Hyoung Kim, Bah-Hwee Gwee
2020	—	`conf`	Hardware Attack and Assurance with Machine Learning: A Security Threat to Circuits and Systems. APCCAS Bah-Hwee Gwee
2020	—	`conf`	High Efficiency Early-Complete Brute Force Elimination Method for Security Analysis of Camouflage IC. APCCAS Weng-Geng Ho, Chuan-Seng Ng, Nay Aung Kyaw, Ne Kyaw Zwa Lwin, Kwen-Siong Chong, Bah-Hwee Gwee
2020	—	`conf`	High Throughput and Secure Authentication-Encryption on Asynchronous Multicore Processor for Edge Computing IoT Applications. ISOCC Weng-Geng Ho, Ali Akbar Pammu, Ne Kyaw Zwa Lwin, Kwen-Siong Chong, Bah-Hwee Gwee
2019	J	`jnl`	A Hierarchical Multiclassifier System for Automated Analysis of Delayered IC Images. IEEE Intell. Syst. Deruo Cheng, Yiqiong Shi, Bah-Hwee Gwee, Kar-Ann Toh, Tong Lin
2019	J	`jnl`	A High Throughput and Secure Authentication-Encryption AES-CCM Algorithm on Asynchronous Multicore Processor. IEEE Trans. Inf. Forensics Secur. Ali Akbar Pammu, Weng-Geng Ho, Ne Kyaw Zwa Lwin, Kwen-Siong Chong, Bah-Hwee Gwee
2019	J	`jnl`	A Highly Efficient Side Channel Attack with Profiling through Relevance-Learning on Physical Leakage Information. IEEE Trans. Dependable Secur. Comput. Ali Akbar Pammu, Kwen-Siong Chong, Yi Wang, Bah-Hwee Gwee
2019	J	`jnl`	A Secure Data-Toggling SRAM for Confidential Data Protection. IEEE Trans. Circuits Syst. I Regul. Pap. Weng-Geng Ho, Kwen-Siong Chong, Tony Tae-Hyoung Kim, Bah-Hwee Gwee
2019	C	`conf`	Global Template Projection and Matching Method for Training-Free Analysis of Delayered IC Images. ISCAS Deruo Cheng, Yiqiong Shi, Tong Lin, Bah-Hwee Gwee, Kar-Ann Toh
2019	C	`conf`	Low Gate-Count Ultra-Small Area Nano Advanced Encryption Standard (AES) Design. ISCAS Aparna Shreedhar, Kwen-Siong Chong, Ne Kyaw Zwa Lwin, Nay Aung Kyaw, L. Nalangilli, Wei Shu, Joseph S. Chang, Bah-Hwee Gwee
2019	—	`conf`	Reconfigurable Routing Paths As Noise Generators Using NoC Platform for Hardware Security Applications. SoCC Weng-Geng Ho, Ali Akbar Pammu, Kyaw Zwa Lwin Ne, Kwen-Siong Chong, Bah-Hwee Gwee
2019	—	`conf`	Side-Channel-Attack Resistant Dual-Rail Asynchronous-Logic AES Accelerator Based on Standard Library Cells. AsianHOST Kwen-Siong Chong, Aparna Shreedhar, Ne Kyaw Zwa Lwin, Nay Aung Kyaw, Weng-Geng Ho, Chao Wang, Jun Zhou, Bah-Hwee Gwee, Joseph S. Chang
2018	—	`conf`	A Comparative Analysis of 65nm CMOS SRAM and Commercial SRAMs in Security Vulnerability Evaluation. DSP Weng-Geng Ho, Zixian Zheng, Kwen-Siong Chong, Bah-Hwee Gwee
2018	J	`jnl`	A Noise-Shaped Randomized Modulation for Switched-Mode DC-DC Converters. IEEE Trans. Circuits Syst. I Regul. Pap. Cui Keer, Victor Adrian, Bah-Hwee Gwee, Joseph S. Chang
2018	J	`jnl`	Asynchronous-Logic QDI Quad-Rail Sense-Amplifier Half-Buffer Approach for NoC Router Design. IEEE Trans. Very Large Scale Integr. Syst. Weng-Geng Ho, Kwen-Siong Chong, Kyaw Zwa Lwin Ne, Bah-Hwee Gwee, Joseph S. Chang
2018	—	`conf`	Deep Learning for Automatic IC Image Analysis. DSP Xuenong Hong, Deruo Cheng, Yiqiong Shi, Tong Lin, Bah-Hwee Gwee
2018	J	`jnl`	Hybrid K-Means Clustering and Support Vector Machine Method for via and Metal Line Detections in Delayered IC Images. IEEE Trans. Circuits Syst. II Express Briefs Deruo Cheng, Yiqiong Shi, Tong Lin, Bah-Hwee Gwee, Kar-Ann Toh
2017	C	`conf`	A class-E RF power amplifier with a novel matching network for high-efficiency dynamic load modulation. ISCAS Qianqian Liu, Victor Adrian, Bah-Hwee Gwee, Joseph S. Chang
2017	—	`conf`	A low-harmonics low-noise randomized modulation scheme for multi-phase DC-DC converters. NEWCAS Cui Keer, Victor Adrian, Yin Sun, Bah-Hwee Gwee, Joseph S. Chang
2017	C	`conf`	DPA-resistant QDI dual-rail AES S-Box based on power-balanced weak-conditioned half-buffer. ISCAS James Lim, Weng-Geng Ho, Kwen-Siong Chong, Bah-Hwee Gwee
2017	C	`conf`	Highly secured state-shift local clock circuit to countermeasure against side channel attack. ISCAS Ali Akbar Pammu, Kwen-Siong Chong, Bah-Hwee Gwee
2017	J	`jnl`	Sense Amplifier Half-Buffer (SAHB) A Low-Power High-Performance Asynchronous Logic QDI Cell Template. IEEE Trans. Very Large Scale Integr. Syst. Kwen-Siong Chong, Weng-Geng Ho, Tong Lin, Bah-Hwee Gwee, Joseph S. Chang
2016	—	`conf`	A high-efficiency Class-E polar power-amplifier with a novel digitally-controlled output matching network. ISIC Qianqian Liu, Victor Adrian, Bah-Hwee Gwee, Joseph S. Chang
2016	C	`conf`	Area-efficient and low stand-by power 1k-byte transmission-gate-based non-imprinting high-speed erase (TNIHE) SRAM. ISCAS Weng-Geng Ho, Kyaw Zwa Lwin Ne, N. Prashanth Srinivas, Kwen-Siong Chong, Tony Tae-Hyoung Kim, Bah-Hwee Gwee
2016	C	`conf`	High performance low overhead template-based Cell-Interleave Pipeline (TCIP) for asynchronous-logic QDI circuits. ISCAS Weng-Geng Ho, Nan Liu, Kyaw Zwa Lwin Ne, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang
2016	—	`conf`	Highly secured arithmetic hiding based S-Box on AES-128 implementation. ISIC Ali Akbar Pammu, Kwen-Siong Chong, Bah-Hwee Gwee
2016	—	`conf`	Interceptive side channel attack on AES-128 wireless communications for IoT applications. APCCAS Ali Akbar Pammu, Kwen-Siong Chong, Weng-Geng Ho, Bah-Hwee Gwee
2016	A	`conf`	Low normalized energy derivation asynchronous circuit synthesis flow through fork-join slack matching for cryptographic applications. DATE Nan Liu, Kwen-Siong Chong, Weng-Geng Ho, Bah-Hwee Gwee, Joseph Sylvester Chang
2016	—	`conf`	Secured Low Power Overhead Compensator Look-Up-Table (LUT) Substitution Box (S-Box) Architecture. NAS Ali Akbar Pammu, Kwen-Siong Chong, Bah-Hwee Gwee
2016	—	`conf`	Security analysis of asynchronous-logic QDI cell approach for differential power analysis attack. ISIC Weng-Geng Ho, Ali Akbar Pammu, Nan Liu, Kyaw Zwa Lwin Ne, Kwen-Siong Chong, Bah-Hwee Gwee
2016	—	`conf`	Success rate model for fully AES-128 in correlation power analysis. APCCAS Ali Akbar Pammu, Kwen-Siong Chong, Ne Kyaw Zwa Lwin, Weng-Geng Ho, Nan Liu, Bah-Hwee Gwee
2015	C	`conf`	A single-VDD half-clock-tolerant fine-grained dynamic voltage scaling pipeline. ISCAS Rong Zhou, Kwen-Siong Chong, Tong Lin, Bah-Hwee Gwee, Joseph S. Chang
2015	C	`conf`	High robustness energy- and area-efficient dynamic-voltage-scaling 4-phase 4-rail asynchronous-logic Network-on-Chip (ANoC). ISCAS Weng-Geng Ho, Kwen-Siong Chong, Ne Kyaw Zwa Lwin, Bah-Hwee Gwee, Joseph S. Chang
2015	J	`jnl`	Low power sub-threshold asynchronous quasi-delay-insensitive 32-bit arithmetic and logic unit based on autonomous signal-validity half-buffer. IET Circuits Devices Syst. Weng-Geng Ho, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang
2015	C	`conf`	Novel real-time system design for floating-point sub-Nyquist multi-coset signal blind reconstruction. ISCAS Hongxu Yin, Bah-Hwee Gwee, Zhiping Lin, Achanna Anil Kumar, Sirajudeen Gulam Razul, Chong Meng Samson See
2014	J	`jnl`	A Low Overhead Quasi-Delay-Insensitive (QDI) Asynchronous Data Path Synthesis Based on Microcell-Interleaving Genetic Algorithm (MIGA). IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Rong Zhou, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang
2014	C	`conf`	A Randomized Modulation scheme for filterless digital Class D audio amplifiers. ISCAS Victor Adrian, Cui Keer, Bah-Hwee Gwee, Joseph Sylvester Chang
2014	—	`conf`	A dynamic-voltage-scaling 1kbyte×8-bit non-imprinting Master-Slave SRAM with high speed erase for low-power operation. ISIC Weng-Geng Ho, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang, Ne Kyaw Zwa Lwin
2014	—	`conf`	A self-oscillating class D audio amplifier with dual voltage and current feedback. ISIC Salma Nashit, Victor Adrian, Cui Keer, Quoc-An Mai, Bah-Hwee Gwee, Joseph S. Chang
2014	—	`conf`	Design of an output stage for high switching frequency DC-DC converters. ISIC Tian-Shun Ng, Yin Sun, Victor Adrian, Bah-Hwee Gwee, Joseph S. Chang
2014	—	`conf`	Low delay-variation sub-/near-threshold asynchronous-to-synchronous interface controller for GALS Network-on-Chips. APCCAS Weng-Geng Ho, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang
2014	C	`conf`	Synthesis of asynchronous QDI circuits using synchronous coding specifications. ISCAS Rong Zhou, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang, Weng-Geng Ho
2014	J	`jnl`	Ultra-Low Power Read-Decoupled SRAMs with Ultra-Low Write-Bitline Voltage Swing. Circuits Syst. Signal Process. Junchao Chen, Kwen-Siong Chong, Bah-Hwee Gwee
2013	C	`conf`	A dual-core 8051 microcontroller system based on synchronous-logic and asynchronous-logic. ISCAS Kok-Leong Chang, Tong Lin, Weng-Geng Ho, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang
2013	J	`jnl`	An Ultra-Low Power Asynchronous-Logic In-Situ Self-Adaptive V IEEE J. Solid State Circuits Tong Lin, Kwen-Siong Chong, Joseph S. Chang, Bah-Hwee Gwee
2013	—	`conf`	Designing globally-asynchronous-locally-system from multi-rate Simulink model. NEWCAS Yiqiong Shi, Bah-Hwee Gwee
2013	C	`conf`	Low power sub-threshold asynchronous QDI Static Logic Transistor-level Implementation (SLTI) 32-bit ALU. ISCAS Weng-Geng Ho, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang
2013	J	`jnl`	Synchronous-Logic and Asynchronous-Logic 8051 Microcontroller Cores for Realizing the Internet of Things: A Comparative Study on Dynamic Voltage Scaling and Variation Effects. IEEE J. Emerg. Sel. Topics Circuits Syst. Kok-Leong Chang, Joseph S. Chang, Bah-Hwee Gwee, Kwen-Siong Chong
2012	C	`conf`	A comparative study on asynchronous Quasi-Delay-Insensitive templates. ISCAS Kok-Leong Chang, Tong Lin, Weng-Geng Ho, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang
2012	C	`conf`	An Ultra-Dynamic Voltage Scalable (U-DVS) 10T SRAM with bit-interleaving capability. ISCAS Junchao Chen, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang
2012	C	`conf`	Energy-delay efficient asynchronous-logic 16×16-bit pipelined multiplier based on Sense Amplifier-Based Pass Transistor Logic. ISCAS Weng-Geng Ho, Kwen-Siong Chong, Tong Lin, Bah-Hwee Gwee, Joseph S. Chang
2012	—	`conf`	Extracting functional modules from flattened gate-level netlist. ISCIT Yiqiong Shi, Bah-Hwee Gwee, Ye Ren, Thet Khaing Phone, Chan Wai Ting
2012	J	`jnl`	Synchronous-Logic and Globally-Asynchronous-Locally-Synchronous (GALS) Acoustic Digital Signal Processors. IEEE J. Solid State Circuits Kwen-Siong Chong, Kok-Leong Chang, Bah-Hwee Gwee, Joseph S. Chang
2011	C	`conf`	A low-power dual-rail inputs write method for bit-interleaved memory cells. ISCAS Junchao Chen, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang
2011	J	`jnl`	Asynchronous DSP for low-power energy-efficient embedded systems. Microprocess. Microsystems Yiqiong Shi, Bah-Hwee Gwee, Joseph Sylvester Chang
2011	C	`conf`	Improved asynchronous-logic dual-rail Sense Amplifier-based Pass Transistor Logic with high speed and low power operation. ISCAS Weng-Geng Ho, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang, Yin Sun, Kok-Leong Chang
2011	J	`jnl`	Modeling and Synthesis of Asynchronous Pipelines. IEEE Trans. Very Large Scale Integr. Syst. Chong-Fatt Law, Bah-Hwee Gwee, Joseph Sylvester Chang
2010	J	`jnl`	A Randomized Wrapped-Around Pulse Position Modulation Scheme for DC-DC Converters. IEEE Trans. Circuits Syst. I Regul. Pap. Victor Adrian, Joseph S. Chang, Bah-Hwee Gwee
2010	C	`conf`	A highly efficient method for extracting FSMs from flattened gate-level netlist. ISCAS Yiqiong Shi, Chan Wai Ting, Bah-Hwee Gwee, Ye Ren
2009	J	`jnl`	A Low-Voltage Micropower Asynchronous Multiplier With Shift-Add Multiplication Approach. IEEE Trans. Circuits Syst. I Regul. Pap. Bah-Hwee Gwee, Joseph S. Chang, Yiqiong Shi, Chien-Chung Chua, Kwen-Siong Chong
2009	J	`jnl`	A Low-Voltage Micropower Digital Class-D Amplifier Modulator for Hearing Aids. IEEE Trans. Circuits Syst. I Regul. Pap. Victor Adrian, Joseph S. Chang, Bah-Hwee Gwee
2009	C	`conf`	A Performance Comparison on Asynchronous Matched-delay Templates. ISCAS Kok-Leong Chang, Bah-Hwee Gwee, Yuanjin Zheng
2009	C	`conf`	Fine-grained Power Gating for Leakage and Short-circuit Power Reduction by using Asynchronous-logic. ISCAS Tong Lin, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang
2008	C	`conf`	A semi-custom memory design for an asynchronous 8051 microcontroller. ISCAS Kok-Leong Chang, Bah-Hwee Gwee, Yuanjin Zheng
2008	J	`jnl`	Asynchronous Control Network Optimization Using Fast Minimum-Cycle-Time Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chong-Fatt Law, Bah-Hwee Gwee, Joseph Sylvester Chang
2008	C	`conf`	De-synchronization of a point-of-sales digital-logic controller. ISCAS Kok-Leong Chang, Yao Zhu, Bah-Hwee Gwee
2007	C	`conf`	A 32-point FFT based Noise Reduction Algorithm for Single Channel Speech Signals. ISCAS Kunal Mukherjee, Bah-Hwee Gwee
2007	C	`conf`	A Low Energy FFT/IFFT Processor for Hearing Aids. ISCAS Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang
2007	C	`conf`	An Asynchronous Dual-Rail Multiplier based on Energy-Efficient STFB Templates. ISCAS Kok-Leong Chang, Bah-Hwee Gwee, Yuanjin Zheng
2007	J	`jnl`	Design of several asynchronous-logic macrocells for a low-voltage micropower cell library. IET Circuits Devices Syst. Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang
2007	J	`jnl`	Energy-Efficient Synchronous-Logic and Asynchronous-Logic FFT/IFFT Processors. IEEE J. Solid State Circuits Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang
2007	J	`jnl`	Fast and memory-efficient invariant computation of ordinary Petri nets. IET Comput. Digit. Tech. Chong-Fatt Law, Bah-Hwee Gwee, Joseph Sylvester Chang
2007	J	`jnl`	Low energy 16-bit Booth leapfrog array multiplier using dynamic adders. IET Circuits Devices Syst. Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang
2006	J	`jnl`	A 16-Channel Low-Power Nonuniform Spaced Filter Bank Core for Digital Hearing Aids. IEEE Trans. Circuits Syst. II Express Briefs Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang
2006	C	`conf`	A low-energy low-voltage asynchronous 8051 microcontroller core. ISCAS Kok-Leong Chang, Bah-Hwee Gwee
2006	C	`conf`	An acoustic noise suppression system with reduced musical artifacts. ISCAS Victor Adrian, Bah-Hwee Gwee, Joseph Sylvester Chang
2006	—	`conf`	Optimized Algorithm for Computing Invariants of Ordinary Petri Nets. ACIS-ICIS Chong-Fatt Law, Bah-Hwee Gwee, Joseph S. Chang
2005	—	`conf`	A combined interpolatorless interpolation and high accuracy sampling process for digital class D amplifiers. ISCAS (6) Victor Adrian, Bah-Hwee Gwee, Joseph Sylvester Chang
2005	J	`jnl`	A micropower low-distortion digital class-D amplifier based on an algorithmic pulsewidth modulator. IEEE Trans. Circuits Syst. I Regul. Pap. Bah-Hwee Gwee, Joseph Sylvester Chang, Victor Adrian
2005	J	`jnl`	A micropower low-voltage multiplier with reduced spurious switching. IEEE Trans. Very Large Scale Integr. Syst. Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang
2005	J	`jnl`	An evolution search algorithm for solving N-queen problems. Int. J. Comput. Appl. Technol. Bah-Hwee Gwee, Meng-Hiot Lim
2005	—	`conf`	Low-voltage micropower multipliers with reduced spurious switching. ISCAS (4) Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang
2004	—	`conf`	A low power 16-bit Booth Leapfrog array multiplier using Dynamic Adders. ISCAS (2) Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang
2004	—	`conf`	A novel combined first and second order Lagrange interpolation sampling process for a digital class D amplifier. ISCAS (3) Victor Adrian, Bah-Hwee Gwee, Joseph Sylvester Chang
2003	C	`conf`	A Hybrid Genetic Hill-climbing Algorithm for Four-Coloring Map Problems. HIS Bah-Hwee Gwee, Joseph Sylvester Chang
2003	—	`conf`	A Low Voltage Micropower 16-Word by 16-Bit 3-Port Asynchronous Register File. VLSI Khia-Ho Chang, Bah-Hwee Gwee, Joseph Sylvester Chang
2003	—	`conf`	A low-voltage micropower asynchronous multiplier for a multiplierless FIR filter. ISCAS (5) Chien-Chung Chua, Bah-Hwee Gwee, Joseph Sylvester Chang
2003	—	`conf`	A novel sampling process and pulse generator for a low distortion digital pulse-width modulator for digital class D amplifiers. ISCAS (4) Bah-Hwee Gwee, Joseph Sylvester Chang, Victor Adrian, H. Amir
2002	—	`conf`	Low-voltage asynchronous adders for low power and high speed applications. ISCAS (1) Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang
2002	—	`conf`	Low-voltage micropower asynchronous multiplier for hearing instruments. ISCAS (1) Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang
2001	—	`conf`	A digital Class D amplifier design embodying a novel sampling process and pulse generator. ISCAS (4) Huiyun Li, Bah-Hwee Gwee, Joseph Sylvester Chang
2001	—	`conf`	A novel low-power low-voltage Class D amplifier with feedback for improving THD, power efficiency and gain linearity. ISCAS (1) Joseph Sylvester Chang, Bah-Hwee Gwee, Yong Seng Lon, Meng Tong Tan
2000	J	`jnl`	A GA with heuristic-based decoder for IC floorplanning. Integr. Bah-Hwee Gwee, Meng-Hiot Lim
2000	C	`conf`	An investigation on the parameters affecting total harmonic distortion in class D amplifiers. ISCAS Meng Tong Tan, Hock-Chuan Chua, Bah-Hwee Gwee, Joseph S. Chang
1996	J	`jnl`	A GA paradigm for learning fuzzy rules. Fuzzy Sets Syst. M. H. Lim, Susanto Rahardja, Bah-Hwee Gwee
1996	J	`jnl`	Polyominoes tiling by a genetic algorithm. Comput. Optim. Appl. Bah-Hwee Gwee, M. H. Lim
1993	J	`jnl`	Intelligent monitoring of a frequency-trimming process. J. Intell. Manuf. M. H. Lim, Bah-Hwee Gwee, Y. Kawada
1993	—	`conf`	Solving four-colouring map problem using genetic algorithm. ANNES Bah-Hwee Gwee, Meng-Hiot Lim, Jiun-Sien Ho