B. Venkataramani

40 papers B 1Misc 7Journal 24Unranked 8
YearRankTypeTitle / Venue / Authors
2023 J jnl
A Novel Feature Enhancement Technique for ECG Arrhythmia Classification Using Discrete Anamorphic Stretch Transform.
Circuits Syst. Signal Process.
R. Thilagavathy, B. Venkataramani
2021 J jnl
A Low-Noise Area-Efficient Current Feedback Instrumentation Amplifier.
Circuits Syst. Signal Process.
R. Sanjay, B. Venkataramani, S. Kumaravel, V. Senthil Rajan, K. Hari Kishore
2020 J jnl
A novel programmable attenuator based low G
Microelectron. J.
V. Senthil Rajan, K. Hari Kishore, R. Sanjay, S. Kumaravel, B. Venkataramani
2020 J jnl
High-performance asynchronous pipeline using embedded delay element.
Microprocess. Microsystems
R. K. Kavitha, A. Khajamastan, Y. Rama Akhilesh, B. Venkataramani
2019 J jnl
Reconfigurable low voltage low power dual-band self-cascode current-reuse quasi-differential LNA for 5G.
Microelectron. J.
K. Hari Kishore, V. Senthil Rajan, R. Sanjay, B. Venkataramani
2019 J jnl
Wideband Balun-LNAs using asymmetric CCC technique for WLAN and mobile WiMAX applications.
Microelectron. J.
K. Hari Kishore, B. Venkataramani, B. Kasi Raju
2017 J jnl
A 1-V 2.4 GHz Low-Power CMOS LNA Using Gain-Boosting and Derivative Superposition Techniques for WSN.
Wirel. Pers. Commun.
R. Raja, B. Venkataramani, K. Hari Kishore
2017 — conf
A Novel Opamp and Capacitor Sharing 10 Bit 20 MS/s Low Power Pipelined ADC in 0.18µm CMOS Technology.
ISVLSI
Greeshma R, Anoop V. K, B. Venkataramani
2017 J jnl
Erratum to: A 1-V 2.4 GHz Low-Power CMOS LNA Using Gain-Boosting and Derivative Superposition Techniques for WSN.
Wirel. Pers. Commun.
R. Raja, B. Venkataramani, K. Hari Kishore
2017 J jnl
Low Power Data Driven Conditional Precharge Dynamic Flip Flop.
J. Low Power Electron.
R. K. Kavitha, Vineeth Johns Toms, Vipin Vinayakan, B. Venkataramani
2016 J jnl
A Low-Power and Highly Linear Merged Low Noise Amplifier-Mixer for Wireless Sensor Network Applications.
J. Low Power Electron.
R. Raja, Ramesh Theegala, B. Venkataramani
2016 J jnl
A high linearity and high gain Folded Cascode LNA for narrowband receiver applications.
Microelectron. J.
S. Kumaravel, Anand Kukde, B. Venkataramani, R. Raja
2015 — conf
A 4 bit medium speed flash ADC using inverter based comparator in 0.18μm CMOS.
VDAT
D. Malathi, R. Greeshma, R. Sanjay, B. Venkataramani
2014 J jnl
Differential Voltage Mode On-Chip Serial Transceiver for Global Interconnects.
J. Low Power Electron.
M. Bhaskar, B. Venkataramani
2013 — conf
A 1.8V 2.4 GHz Folded-Switch Mixer for Direct Conversion Receiver.
ISED
R. Raja, S. Kumaravel, B. Venkataramani, Ganesh Yashavant Magar
2013 J jnl
A Power Efficient Low Noise Preamplifier for Biomedical Applications.
J. Low Power Electron.
S. Kumaravel, K. N. Bharadwaj Tirumala, B. Venkataramani, R. Raja
2013 — conf
Design of a Biometric Security System Using Support Vector Machine Classifier.
ICACNI
J. Manikandan, V. K. Agrawal, B. Venkataramani
2013 J jnl
Design of a novel differential on-chip wave-pipelined serial interconnect with surfing.
Microprocess. Microsystems
M. Bhaskar, A. Jaswanth, B. Venkataramani
2013 J jnl
System-on-programmable-chip implementation of diminishing learning based pattern recognition system.
Int. J. Mach. Learn. Cybern.
J. Manikandan, B. Venkataramani
2012 — conf
An enhanced folded cascode OTA with push pull input stage.
SSD
S. Kumaravel, B. Venkataramani, S. Rishi, V. Sri Vijay, B. Shailendra
2011 J jnl
A Low Power Reconfigurable Analog Baseband Block for Software Defined Radio.
J. Signal Process. Syst.
S. Ramasamy, B. Venkataramani
2011 J jnl
Design of a real time automatic speech recognition system using Modified One Against All SVM classifier.
Microprocess. Microsystems
J. Manikandan, B. Venkataramani
2011 Misc conf
Hardware Implementation of Real-Time Speech Recognition System Using TMS320C6713 DSP.
VLSI Design
J. Manikandan, B. Venkataramani, K. Girish, H. Karthic, V. Siddharth
2010 Misc conf
Implementation of a Novel Phoneme Recognition System Using TMS320C6713 DSP.
VLSI Design
J. Manikandan, B. Venkataramani, M. Bhaskar, K. Ashish, R. Raghul, V. Mathangi
2010 J jnl
Study and evaluation of a multi-class SVM classifier using diminishing learning technique.
Neurocomputing
J. Manikandan, B. Venkataramani
2009 Misc conf
100KHz-20MHz Programmable Subthreshold G
VLSI Design
S. Ramasamy, B. Venkataramani, R. Niranjini, K. Suganya
2009 — conf
A Scheduling Policy for Battery Management in Mobile Devices.
NetCoM
B. Malarkodi, B. Prasana, B. Venkataramani
2009 J jnl
A low power CMOS voltage reference circuit with sub threshold MOSFETs.
Int. J. Inf. Commun. Technol.
S. Ramasamy, B. Venkataramani, P. Meenatchisundaram
2009 J jnl
Automation Schemes for FPGA Implementation of Wave-Pipelined Circuits.
ACM Trans. Reconfigurable Technol. Syst.
G. Seetharaman, B. Venkataramani
2009 Misc conf
Built in Self Test Based Design of Wave-Pipelined Circuits in ASICs.
VLSI Design
V. Vireen, N. Venugopalachary, G. Seetharaman, B. Venkataramani
2009 B conf
Design of a Modified One-Against-All SVM Classifier.
SMC
J. Manikandan, B. Venkataramani
2009 Misc conf
FPGA Implementation of Support Vector Machine Based Isolated Digit Recognition System.
VLSI Design
J. Manikandan, B. Venkataramani, V. Avanthi
2009 — conf
Performance Evaluation of Adhoc Networks with Different Multicast Routing Protocols and Mobility Models.
ARTCom
B. Malarkodi, P. Gopal, B. Venkataramani
2009 — conf
Performance Evaluation of On-Demand Multipath Distance Vector Routing Protocol under Different Traffic Models.
ARTCom
B. Malarkodi, P. Rakesh, B. Venkataramani
2009 J jnl
Software/Hardware Co-design of HMM Based Speaker Independent Isolated Digit Recognition System.
J. Comput.
V. Amudha, B. Venkataramani, R. Vinoth Kumar, S. Ravishankar
2008 J jnl
Automation techniques for implementation of hybrid wave-pipelined 2D DWT.
J. Real Time Image Process.
G. Seetharaman, B. Venkataramani, Gopalakrishnan Lakshminarayanan
2008 Misc conf
VLSI Implementation of a Digitally Tunable Gm-C Filter with Double CMOS Pair.
VLSI Design
S. Ramasamy, B. Venkataramani, K. Anbugeetha
2007 Misc conf
SOC Implementation of HMM Based Speaker Independent Isolated Digit Recognition System.
VLSI Design
V. Amudha, B. Venkataramani, R. Vinoth Kumar, S. Ravishankar
2005 J jnl
Optimization Techniques for FPGA-Based Wave-Pipelined DSP Blocks.
IEEE Trans. Very Large Scale Integr. Syst.
Gopalakrishnan Lakshminarayanan, B. Venkataramani
1997 J jnl
Queuing analysis of a non-pre-emptive MMPP/D/1 priority system.
Comput. Commun.
B. Venkataramani, Sanjay K. Bose, K. R. Srivathsan