B. Ramakrishna Rau

46 papers A* 18A 1Misc 3Journal 18Unranked 6

Year	Rank	Type	Title / Venue / Authors
2002	J	`jnl`	Constructing and exploiting linear schedules with prescribed parallelism. ACM Trans. Design Autom. Electr. Syst. Alain Darte, Robert Schreiber, B. Ramakrishna Rau, Frédéric Vivien
2002	J	`jnl`	PICO-NPA: High-Level Synthesis of Nonprogrammable Hardware Accelerators. J. VLSI Signal Process. Robert Schreiber, Shail Aditya, Scott A. Mahlke, Vinod Kathail, B. Ramakrishna Rau, Darren C. Cronquist, Mukund Sivaraman
2002	J	`jnl`	PICO: Automatically Designing Custom Computers. Computer Vinod Kathail, Shail Aditya, Robert Schreiber, B. Ramakrishna Rau, Darren C. Cronquist, Mukund Sivaraman
2002	A*	`ed.`	Proceedings of the 35th Annual International Symposium on Microarchitecture, Istanbul, Turkey, November 18-22, 2002 MICRO Erik R. Altman, Kemal Ebcioglu, Scott A. Mahlke, B. Ramakrishna Rau, Sanjay J. Patel
2001	J	`jnl`	Compiling for EPIC architectures. Proc. IEEE Vinod Kathail, Michael S. Schlansker, B. Ramakrishna Rau
2001	J	`jnl`	Embedded Computer Architecture and Automation. Computer B. Ramakrishna Rau, Michael S. Schlansker
2000	A	`conf`	A Constructive Solution to the Juggling Problem in Processor Array Synthesis. IPDPS Alain Darte, Robert Schreiber, B. Ramakrishna Rau, Frédéric Vivien
2000	J	`jnl`	Code size minimization and retargetable assembly for custom EPIC and VLIW instruction formats. ACM Trans. Design Autom. Electr. Syst. Shail Aditya, Scott A. Mahlke, B. Ramakrishna Rau
2000	J	`jnl`	EPIC: Explicititly Parallel Instruction Computing. Computer Michael S. Schlansker, B. Ramakrishna Rau
2000	Misc	`conf`	Efficient design space exploration in PICO. CASES Santosh G. Abraham, B. Ramakrishna Rau
2000	Misc	`conf`	Embedded Computing: New Directions in Architecture and Automation. HiPC B. Ramakrishna Rau, Michael S. Schlansker
2000	—	`conf`	High-Level Synthesis of Nonprogrammable Hardware Accelerators. ASAP Robert Schreiber, Shail Aditya, B. Ramakrishna Rau, Vinod Kathail, Scott A. Mahlke, Santosh G. Abraham, Greg Snider
2000	Misc	`conf`	The era of embedded computing. CASES B. Ramakrishna Rau
1999	—	`conf`	Automatic Architectural Synthesis of VLIW and EPIC Processors. ISSS Shail Aditya, B. Ramakrishna Rau, Vinod Kathail
1999	J	`jnl`	Machine-Description Driven Compilers for EPIC and VLIW Processors. Des. Autom. Embed. Syst. B. Ramakrishna Rau, Vinod Kathail, Shail Aditya
1998	J	`jnl`	Optimization of Machine Descriptions for Efficient Use. Int. J. Parallel Program. John C. Gyllenhaal, Wen-mei W. Hwu, B. Ramakrishna Rau
1997	J	`jnl`	Region-based compilation: Introduction, motivation, and initial experience. Int. J. Parallel Program. Richard E. Hank, Wen-mei W. Hwu, B. Ramakrishna Rau
1996	J	`jnl`	Iterative Modulo Scheduling. Int. J. Parallel Program. B. Ramakrishna Rau
1996	A*	`conf`	Optimization of Machine Descriptions for Efficient Use. MICRO John C. Gyllenhaal, Wen-mei W. Hwu, B. Ramakrishna Rau
1996	A*	`conf`	Profile-driven Instruction Level Parallel Scheduling with Application to Super Blocks. MICRO Chandra Chekuri, Richard Johnson, Rajeev Motwani, B. Natarajan, B. Ramakrishna Rau, Michael S. Schlansker
1995	A*	`conf`	Region-based compilation: an introduction and motivation. MICRO Richard E. Hank, Wen-mei W. Hwu, B. Ramakrishna Rau
1994	A*	`conf`	Iterative modulo scheduling: an algorithm for software pipelining loops. MICRO B. Ramakrishna Rau
1993	A*	`conf`	Dynamically scheduled VLIW processors. MICRO B. Ramakrishna Rau
1993	J	`jnl`	Guest editors' introduction. J. Supercomput. Joseph A. Fisher, B. Ramakrishna Rau
1993	J	`jnl`	Instruction-level parallel processing: History, overview, and perspective. J. Supercomput. B. Ramakrishna Rau, Joseph A. Fisher
1993	A*	`conf`	Predictability of load/store instruction latencies. MICRO Santosh G. Abraham, Rabin A. Sugumar, Daniel Windheiser, B. Ramakrishna Rau, Rajiv Gupta
1993	A*	`conf`	Reverse If-Conversion. PLDI Nancy J. Warter, Scott A. Mahlke, Wen-mei W. Hwu, B. Ramakrishna Rau
1993	J	`jnl`	Sentinel Scheduling for VLIW and Superscalar Processors. ACM Trans. Comput. Syst. Scott A. Mahlke, William Y. Chen, Roger A. Bringmann, Richard E. Hank, Wen-mei W. Hwu, B. Ramakrishna Rau, Michael S. Schlansker
1992	A*	`conf`	Code generation schema for modulo scheduled loops. MICRO B. Ramakrishna Rau, Michael S. Schlansker, Parthasarathy P. Tirumalai
1992	A*	`conf`	Register Allocation for Software Pipelined Loops. PLDI B. Ramakrishna Rau, Meng Lee, Parthasarathy P. Tirumalai, Michael S. Schlansker
1992	A*	`conf`	Sentinel Scheduling for VLIW and Superscalar Processors. ASPLOS Scott A. Mahlke, William Y. Chen, Wen-mei W. Hwu, B. Ramakrishna Rau, Michael S. Schlansker
1991	—	`conf`	Data Flow and Dependence Analysis for Instruction Level Parallelism. LCPC B. Ramakrishna Rau
1991	A*	`conf`	Pseudo-Randomly Interleaved Memory. ISCA B. Ramakrishna Rau
1989	J	`jnl`	Appucations Development On the Very Long Instruction Word Cydra-5. Int. J. High Perform. Comput. Appl. Peter Y.-T. Hsu, B. Ramakrishna Rau, K. J. M. Moriarty
1989	J	`jnl`	The Cydra 5 Departmental Supercomputer: Design Philosophies, Decisions, and Trade-offs. Computer B. Ramakrishna Rau, David W. L. Yen, Wei C. Yen, Ross A. Towle
1989	—	`conf`	The Cydram 5 Stride-Insensitive Memory System. ICPP (1) B. Ramakrishna Rau, Michael S. Schlansker, David W. L. Yen
1988	—	`conf`	Cydra 5 Directed Dataflow Architecture. COMPCON B. Ramakrishna Rau
1982	A*	`conf`	Architectural Support for the Efficient Generation of Code for Horizontal Architectures. ASPLOS B. Ramakrishna Rau, Christopher D. Glaeser, E. M. Greenawalt
1982	A*	`conf`	Efficient code generation for horizontal architectures: Compiler techniques and architectural support. ISCA B. Ramakrishna Rau, Christopher D. Glaeser, Raymond L. Picard
1982	—	`conf`	Systematically derived instruction sets for high-level language support. ACM Southeast Regional Conference Pradip Bose, B. Ramakrishna Rau, Michael S. Schlansker
1981	A*	`conf`	Some scheduling techniques and an easily schedulable horizontal architecture for high performance scientific computing. MICRO B. Ramakrishna Rau, Christopher D. Glaeser
1979	J	`jnl`	Interleaved Memory Bandwidth in a Model of a Muyltiprocessor Computer System. IEEE Trans. Computers B. Ramakrishna Rau
1979	J	`jnl`	Program Behavior and the Performance of Interleaved Memories. IEEE Trans. Computers B. Ramakrishna Rau
1978	A*	`conf`	Levels of representation of programs and the architecture of universal host machines. MICRO B. Ramakrishna Rau
1977	A*	`conf`	The Effect of Instruction Fetch Strategies upon the Performance of Pipelined Instruction Units. ISCA B. Ramakrishna Rau, George E. Rossman
1976	A*	`conf`	A new philosophy for interconnection on multilayer boards. DAC B. Ramakrishna Rau