B. P. Harish

13 papers C 1Journal 6Unranked 6
YearRankTypeTitle / Venue / Authors
2024 J jnl
Integrated AWA fitness PSO-SPICE framework for automated design and optimisation of analogue and mixed-signal ICs.
Int. J. Artif. Intell. Soft Comput.
Harsha Maddur Venkataswamy, B. P. Harish
2024 J jnl
Integrated AWA fitness PSO-SPICE framework for automated design and optimisation of analogue and mixed-signal ICs.
Int. J. Artif. Intell. Soft Comput.
Harsha Maddur Venkataswamy, B. P. Harish
2022 J jnl
A Novel Feasibility Test for Energy Minimization of Real-Time Mixed Task Sets for DVS-Enabled Uniprocessor System.
J. Circuits Syst. Comput.
H. T. Manohara, B. P. Harish
2020 — conf
Artificial Neural Network Model for Design Optimization of 2-stage Op-amp.
VDAT
Harsha M. V., B. P. Harish
2020 J jnl
Process-induced variability modeling of subthreshold leakage power considering device stacking.
Int. J. Circuit Theory Appl.
Anala M. Reddy, B. P. Harish
2019 — conf
Dynamic Supply Voltage Level Generation for Minimum Energy Real Time Tasks using Geometric Programming.
SoCC
H. T. Manohara, B. P. Harish
2019 — conf
Process Variation-Aware Analytical Modeling of Subthreshold Leakage Power.
PATMOS
Anala M., B. P. Harish
2018 — conf
An Integrated MaxFit Genetic Algorithm-SPICE Framework for 2-Stage Op-Amp Design Automation.
ISVLSI
Harsha M. V., B. P. Harish
2018 — conf
Analytical Modeling of Process Variability in Subthreshold Regime for Ultra Low Power Applications.
APCCAS
Anala M., B. P. Harish
2009 C conf
Bridging Technology-CAD and Design-CAD for Variability Aware Nano-CMOS Circuits.
ISCAS
B. P. Harish, Navakanta Bhat, Mahesh B. Patil
2008 J jnl
Hybrid-CV Modeling for Estimating the Variability in Dynamic Power.
J. Low Power Electron.
B. P. Harish, Navakanta Bhat, Mahesh B. Patil
2007 J jnl
On a Generalized Framework for Modeling the Effects of Process Variations on Circuit Delay Performance Using Response Surface Methodology.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
B. P. Harish, Navakanta Bhat, Mahesh B. Patil
2007 — conf
Process Variability-Aware Statistical Hybrid Modeling of Dynamic Power Dissipation in 65 nm CMOS Designs.
ICCTA
B. P. Harish, Navakanta Bhat, Mahesh B. Patil