Azadeh Davoodi

114 papers A* 10A 25B 2C 6Misc 2Journal 40Unranked 26

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	CADI: Carbon-Aware Distributed Inference. COINS Robert Viramontes, Azadeh Davoodi
2025	B	`conf`	FreDDI: Frequency-Driven DNN Partitioning in Distributed Inference. SMARTCOMP Robert Viramontes, Azadeh Davoodi
2025	A	`conf`	ReBERT: LLM for Gate-Level to Word-Level Reverse Engineering. DATE Lizi Zhang, Azadeh Davoodi, Rasit Onur Topaloglu
2025	—	`conf`	Static IR Drop Prediction with Limited Data from Real Designs. ASP-DAC Lizi Zhang, Azadeh Davoodi
2024	B	`conf`	DIME: Distributed Inference Model Estimation for Minimizing Profiled Latency. SMARTCOMP Robert Viramontes, Azadeh Davoodi
2024	—	`conf`	Efficient and Effective Neural Networks for Automatic Test Pattern Generation. MLCAD Lizi Zhang, Azadeh Davoodi
2024	J	`jnl`	Static IR Drop Prediction with Attention U-Net and Saliency-Based Explainability. CoRR Lizi Zhang, Azadeh Davoodi
2023	J	`jnl`	Block Pruning for Enhanced Efficiency in Convolutional Neural Networks. CoRR Cheng-En Wu, Azadeh Davoodi, Yu Hen Hu
2023	J	`jnl`	Introduction to Special Section on FPT'20. ACM Trans. Reconfigurable Technol. Syst. Oliver Sinnen, Qiang Liu, Azadeh Davoodi
2023	—	`conf`	Neural Network Partitioning for Fast Distributed Inference. ISQED Robert Viramontes, Azadeh Davoodi
2023	J	`jnl`	ObfusX: Routing obfuscation with explanatory analysis of a machine learning attack. Integr. Wei Zeng, Azadeh Davoodi, Rasit Onur Topaloglu
2022	—	`conf`	$\text{Edge}^{n}$ AI: Distributed Inference with Local Edge Devices and Minimal Latency. ASP-DAC Maedeh Hemmat, Azadeh Davoodi, Yu Hen Hu
2022	J	`jnl`	CAP'NN: A Class-aware Framework for Personalized Neural Network Inference. ACM Trans. Embed. Comput. Syst. Maedeh Hemmat, Joshua San Miguel, Azadeh Davoodi
2021	J	`jnl`	A Mixture of Experts Approach for Low-Cost DNN Customization. IEEE Des. Test Boyu Zhang, Azadeh Davoodi, Yu Hen Hu
2021	J	`jnl`	AirNN: A Featherweight Framework for Dynamic Input-Dependent Approximation of CNNs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Maedeh Hemmat, Joshua San Miguel, Azadeh Davoodi
2021	A	`conf`	Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization. DATE Shubham Rai, Walter Lau Neto, Yukio Miyasaka, Xinpei Zhang, Mingfei Yu, Qingyang Yi, Masahiro Fujita, Guilherme B. Manske, Matheus F. Pontes, Leomar S. da Rosa, Marilton S. de Aguiar, Paulo F. Butzen, Po-Chun Chien, Yu-Shan Huang, Hoa-Ren Wang, Jie-Hong R. Jiang, Jiaqi Gu, Zheng Zhao, Zixuan Jiang, David Z. Pan, Brunno A. Abreu, Isac de Souza Campos, Augusto Andre Souza Berndt, Cristina Meinhardt, Jônata Tyska Carvalho, Mateus Grellert, Sergio Bampi, Aditya Lohana, Akash Kumar, Wei Zeng, Azadeh Davoodi, Rasit Onur Topaloglu, Yuan Zhou, Jordan Dotzel, Yichi Zhang, Hanyu Wang, Zhiru Zhang, Valerio Tenace, Pierre-Emmanuel Gaillardon, Alan Mishchenko, Satrajit Chatterjee
2021	—	`conf`	Lorax: Machine Learning-Based Oracle Reconstruction With Minimal I/O Patterns. ISVLSI Wei Zeng, Azadeh Davoodi, Rasit Onur Topaloglu
2021	—	`conf`	ObfusX: Routing Obfuscation with Explanatory Analysis of a Machine Learning Attack. ASP-DAC Wei Zeng, Azadeh Davoodi, Rasit Onur Topaloglu
2021	A	`conf`	Sampling-Based Approximate Logic Synthesis: An Explainable Machine Learning Approach. ICCAD Wei Zeng, Azadeh Davoodi, Rasit Onur Topaloglu
2020	A*	`conf`	CAP'NN: Class-Aware Personalized Neural Network Inference. DAC Maedeh Hemmat, Joshua San Miguel, Azadeh Davoodi
2020	—	`conf`	CHaPR: Efficient Inference of CNNs via Channel Pruning. COINS Boyu Zhang, Azadeh Davoodi, Yu Hen Hu
2020	A	`conf`	Explainable DRC Hotspot Prediction with Random Forest and SHAP Tree Explainer. DATE Wei Zeng, Azadeh Davoodi, Rasit Onur Topaloglu
2020	J	`jnl`	Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization. CoRR Shubham Rai, Walter Lau Neto, Yukio Miyasaka, Xinpei Zhang, Mingfei Yu, Qingyang Yi, Masahiro Fujita, Guilherme B. Manske, Matheus F. Pontes, Leomar S. da Rosa Jr., Marilton S. de Aguiar, Paulo F. Butzen, Po-Chun Chien, Yu-Shan Huang, Hoa-Ren Wang, Jie-Hong R. Jiang, Jiaqi Gu, Zheng Zhao, Zixuan Jiang, David Z. Pan, Brunno A. Abreu, Isac de Souza Campos, Augusto Andre Souza Berndt, Cristina Meinhardt, Jônata Tyska Carvalho, Mateus Grellert, Sergio Bampi, Aditya Lohana, Akash Kumar, Wei Zeng, Azadeh Davoodi, Rasit Onur Topaloglu, Yuan Zhou, Jordan Dotzel, Yichi Zhang, Hanyu Wang, Zhiru Zhang, Valerio Tenace, Pierre-Emmanuel Gaillardon, Alan Mishchenko, Satrajit Chatterjee
2019	J	`jnl`	Analysis of Security of Split Manufacturing Using Machine Learning. IEEE Trans. Very Large Scale Integr. Syst. Wei Zeng, Boyu Zhang, Azadeh Davoodi
2019	—	`conf`	Dynamic Reconfiguration of CNNs for Input-Dependent Approximation. ISQED Maedeh Hemmat, Azadeh Davoodi
2019	J	`jnl`	Efficient Inference of CNNs via Channel Pruning. CoRR Boyu Zhang, Azadeh Davoodi, Yu Hen Hu
2019	J	`jnl`	Power-efficient ReRAM-aware CNN model generation. Integr. Maedeh Hemmat, Azadeh Davoodi
2018	—	`conf`	A Comparative Study of Local Net Modeling Using Machine Learning. ACM Great Lakes Symposium on VLSI Jackson Melchert, Boyu Zhang, Azadeh Davoodi
2018	J	`jnl`	A Mixture of Expert Approach for Low-Cost Customization of Deep Neural Networks. CoRR Boyu Zhang, Azadeh Davoodi, Yu Hen Hu
2018	A*	`conf`	Analysis of security of split manufacturing using machine learning. DAC Boyu Zhang, Jonathon Crandall Magaña, Azadeh Davoodi
2018	J	`jnl`	Design Rule Violation Hotspot Prediction Based on Neural Network Ensembles. CoRR Wei Zeng, Azadeh Davoodi, Yu Hen Hu
2018	J	`jnl`	Exploring Energy and Accuracy Tradeoff in Structure Simplification of Trained Deep Neural Networks. IEEE J. Emerg. Sel. Topics Circuits Syst. Boyu Zhang, Azadeh Davoodi, Yu Hen Hu
2018	—	`conf`	Exploring energy and accuracy tradeoff in structure simplification of trained deep neural networks. ASP-DAC Boyu Zhang, Azadeh Davoodi, Yu Hen Hu
2018	C	`conf`	Power-Efficient ReRAM-Aware CNN Model Generation. ICCD Maedeh Hemmat, Azadeh Davoodi
2017	J	`jnl`	Are Proximity Attacks a Threat to the Security of Split Manufacturing of Integrated Circuits? IEEE Trans. Very Large Scale Integr. Syst. Jonathon Magaña, Daohang Shi, Jackson Melchert, Azadeh Davoodi
2017	J	`jnl`	Dynamic Planning of Local Congestion From Varying-Size Vias for Global Routing Layer Assignment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Daohang Shi, Edward Tashjian, Azadeh Davoodi
2017	—	`conf`	Flexible interconnect in 2.5D ICs to minimize the interposer's metal layers. ASP-DAC Daniel P. Seemuth, Azadeh Davoodi, Katherine Morrow
2017	—	`conf`	Improving Detailed Routability and Pin Access with 3D Monolithic Standard Cells. ISPD Daohang Shi, Azadeh Davoodi
2017	A	`conf`	Technology mapping with all spin logic. DATE Boyu Zhang, Azadeh Davoodi
2017	A*	`conf`	TraPL: Track Planning of Local Congestion for Global Routing. DAC Daohang Shi, Azadeh Davoodi
2016	A	`conf`	A procedure for improving the distribution of congestion in global routing. DATE Daohang Shi, Azadeh Davoodi, Jeffrey T. Linderoth
2016	A	`conf`	Are proximity attacks a threat to the security of split manufacturing of integrated circuits? ICCAD Jonathon Magaña, Daohang Shi, Azadeh Davoodi
2016	—	`conf`	Dynamic planning of local congestion from varying-size vias for global routing layer assignment. ASP-DAC Daohang Shi, Edward Tashjian, Azadeh Davoodi
2016	J	`jnl`	Preface to Special Section on New Physical Design Techniques for the Next Generation of Integration Technology. ACM Trans. Design Autom. Electr. Syst. Evangeline F. Y. Young, Azadeh Davoodi
2015	—	`conf`	Automatic die placement and flexible I/O assignment in 2.5D IC design. ISQED Daniel P. Seemuth, Azadeh Davoodi, Katherine Morrow
2015	J	`jnl`	Guest Editorial: Special Section on Physical Design Techniques for Advanced Technology Nodes. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Azadeh Davoodi, Jiang Hu, Muhammet Mustafa Ozdal, Cliff C. N. Sze
2015	A*	`conf`	On using control signals for word-level identification in a gate-level netlist. DAC Edward Tashjian, Azadeh Davoodi
2015	—	`conf`	Online and Operand-Aware Detection of Failures Utilizing False Alarm Vectors. ACM Great Lakes Symposium on VLSI Amir Yazdanbakhsh, David J. Palframan, Azadeh Davoodi, Nam Sung Kim, Mikko H. Lipasti
2015	—	`ed.`	Proceedings of the 2015 Symposium on International Symposium on Physical Design, ISPD 2015, Monterey, CA, USA, March 29 - April 1, 2015 ISDP Azadeh Davoodi, Evangeline F. Y. Young
2014	J	`jnl`	A Hybrid Approach for Fast and Accurate Trace Signal Selection for Post-Silicon Debug. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Min Li, Azadeh Davoodi
2014	—	`ed.`	International Symposium on Physical Design, ISPD'14, Petaluma, CA, USA, March 30 - April 02, 2014 ISPD Cliff C. N. Sze, Azadeh Davoodi
2014	—	`conf`	Multi-mode trace signal selection for post-silicon debug. ASP-DAC Min Li, Azadeh Davoodi
2013	J	`jnl`	A Sensor-Assisted Self-Authentication Framework for Hardware Trojan Detection. IEEE Des. Test Azadeh Davoodi, Min Li, Mohammad Tehranipoor
2013	J	`jnl`	A fast and scalable multidimensional multiple-choice knapsack heuristic. ACM Trans. Design Autom. Electr. Syst. Hamid Shojaei, Twan Basten, Marc Geilen, Azadeh Davoodi
2013	A	`conf`	A hybrid approach for fast and accurate trace signal selection for post-silicon debug. DATE Min Li, Azadeh Davoodi
2013	J	`jnl`	Collaborative Multiobjective Global Routing. IEEE Trans. Very Large Scale Integr. Syst. Hamid Shojaei, Azadeh Davoodi, Twan Basten
2013	—	`conf`	Planning for local net congestion in global routing. ISPD Hamid Shojaei, Azadeh Davoodi, Jeffrey T. Linderoth
2013	J	`jnl`	Power-Driven Global Routing for Multisupply Voltage Domains. VLSI Design Tai-Hsuan Wu, Azadeh Davoodi, Jeffrey T. Linderoth
2012	A	`conf`	A sensor-assisted self-authentication framework for hardware trojan detection. DATE Min Li, Azadeh Davoodi, Mohammad Tehranipoor
2012	A*	`conf`	Confidentiality preserving integer programming for global routing. DAC Hamid Shojaei, Azadeh Davoodi, Parmeswaran Ramanathan
2012	A	`conf`	Custom on-chip sensors for post-silicon failing path isolation in the presence of process variations. DATE Min Li, Azadeh Davoodi, Lin Xie
2012	J	`jnl`	Post-Silicon Failing-Path Isolation Incorporating the Effects of Process Variations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Lin Xie, Azadeh Davoodi
2011	J	`jnl`	Bound-Based Statistically-Critical Path Extraction Under Process Variations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Lin Xie, Azadeh Davoodi
2011	A	`conf`	Congestion analysis for global routing via integer programming. ICCAD Hamid Shojaei, Azadeh Davoodi, Jeffrey T. Linderoth
2011	J	`jnl`	GRIP: Global Routing via Integer Programming. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Tai-Hsuan Wu, Azadeh Davoodi, Jeffrey T. Linderoth
2011	A	`conf`	Power-driven global routing for multi-supply voltage domains. DATE Tai-Hsuan Wu, Azadeh Davoodi, Jeff T. Linderoth
2010	A*	`conf`	A parallel integer programming approach to global routing. DAC Tai-Hsuan Wu, Azadeh Davoodi, Jeffrey T. Linderoth
2010	A	`conf`	A pareto-algebraic framework for signal power optimization in global routing. ISLPED Hamid Shojaei, Tai-Hsuan Wu, Azadeh Davoodi, Twan Basten
2010	A*	`conf`	Post-silicon diagnosis of segments of failing speedpaths due to manufacturing variations. DAC Lin Xie, Azadeh Davoodi, Kewal K. Saluja
2010	A*	`conf`	Representative path selection for post-silicon timing prediction under variability. DAC Lin Xie, Azadeh Davoodi
2010	—	`conf`	Runtime temperature-based power estimation for optimizing throughput of thermal-constrained multi-core processors. ASP-DAC Dongkeun Oh, Nam Sung Kim, Charlie Chung-Ping Chen, Azadeh Davoodi, Yu Hen Hu
2010	A	`conf`	Trace signal selection to enhance timing and logic visibility in post-silicon validation. ICCAD Hamid Shojaei, Azadeh Davoodi
2009	J	`jnl`	Adjustment-Based Modeling for Timing Analysis Under Variability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Lin Xie, Azadeh Davoodi, Jun Zhang, Tai-Hsuan Wu
2009	—	`conf`	Bound-based identification of timing-violating paths under variability. ASP-DAC Lin Xie, Azadeh Davoodi
2009	Misc	`conf`	False Path Aware Timing Yield Estimation under Variability. VTS Lin Xie, Azadeh Davoodi, Kewal K. Saluja, Abhishek A. Sinkar
2009	A*	`conf`	GRIP: scalable 3D global routing using integer programming. DAC Tai-Hsuan Wu, Azadeh Davoodi, Jeffrey T. Linderoth
2009	J	`jnl`	PaRS: Parallel and Near-Optimal Grid-Based Cell Sizing for Library-Based Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Tai-Hsuan Wu, Azadeh Davoodi
2009	A	`conf`	Statistical static timing analysis considering leakage variability in power gated designs. ISLPED Michael J. Anderson, Azadeh Davoodi, Jungseob Lee, Abhishek A. Sinkar, Nam Sung Kim
2008	C	`conf`	A Dual-Vt low leakage SRAM array robust to process variations. ISCAS Jungseob Lee, Lin Xie, Azadeh Davoodi
2008	J	`jnl`	A Parallel and Randomized Algorithm for Large-Scale Discrete Dual-Vt Assignment and Continuous Gate Sizing. J. Low Power Electron. Tai-Hsuan Wu, Lin Xie, Azadeh Davoodi
2008	A	`conf`	A parallel and randomized algorithm for large-scale discrete dual-Vt assignment and continuous gate sizing. ISLPED Tai-Hsuan Wu, Lin Xie, Azadeh Davoodi
2008	A	`conf`	Adjustment-based modeling for statistical static timing analysis with high dimension of variability. ICCAD Lin Xie, Azadeh Davoodi, Jun Zhang, Tai-Hsuan Wu
2008	—	`conf`	Fast and Accurate Statistical Static Timing Analysis with Skewed Process Parameter Variation. ISQED Lin Xie, Azadeh Davoodi
2008	J	`jnl`	Fast and accurate statistical static timing analysis with skewed process parameter variation. IET Circuits Devices Syst. Lin Xie, Azadeh Davoodi
2008	A	`conf`	PaRS: fast and near-optimal grid-based cell sizing for library-based design. ICCAD Tai-Hsuan Wu, Azadeh Davoodi
2008	J	`jnl`	Robust Estimation of Timing Yield With Partial Statistical Information on Process Variations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Lin Xie, Azadeh Davoodi
2008	—	`conf`	Robust Estimation of Timing Yield with Partial Statistical Information on Process Variations. ISQED Lin Xie, Azadeh Davoodi
2008	C	`conf`	SynECO: Incremental technology mapping with constrained placement and fast detail routing for predictable timing improvement. ICCD Anuj Kumar, Tai-Hsuan Wu, Azadeh Davoodi
2008	J	`jnl`	Variability Driven Gate Sizing for Binning Yield Optimization. IEEE Trans. Very Large Scale Integr. Syst. Azadeh Davoodi, Ankur Srivastava
2007	C	`conf`	Comparison of Dual-Vt Configurations of SRAM Cell Considering Process-Induced Vt Variations. ISCAS Jungseob Lee, Azadeh Davoodi
2007	C	`conf`	Statistical timing analysis using Kernel smoothing. ICCD Jennifer L. Wong, Azadeh Davoodi, Vishal Khandelwal, Ankur Srivastava, Miodrag Potkonjak
2007	Misc	`conf`	Variability Driven Joint Leakage-Delay Optimization Through Gate Sizing with Provabale Convergence. VLSI Design Ashish Dobhal, Vishal Khandelwal, Azadeh Davoodi, Ankur Srivastava
2006	J	`jnl`	A statistical methodology for wire-length prediction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jennifer L. Wong, Azadeh Davoodi, Vishal Khandelwal, Ankur Srivastava, Miodrag Potkonjak
2006	J	`jnl`	Effective techniques for the generalized low-power binding problem. ACM Trans. Design Autom. Electr. Syst. Azadeh Davoodi, Ankur Srivastava
2006	J	`jnl`	FPGA Dynamic Power Minimization through Placement and Routing Constraints. EURASIP J. Embed. Syst. Li Wang, Matthew French, Azadeh Davoodi, Deepak Agarwal
2006	—	`—`	Optimization Schemes for Variability-Driven VLSI Design Automation. Azadeh Davoodi
2006	J	`jnl`	Probabilistic Evaluation of Solutions in Variability-Driven Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Azadeh Davoodi, Vishal Khandelwal, Ankur Srivastava
2006	—	`conf`	Probabilistic evaluation of solutions in variability-driven optimization. ISPD Azadeh Davoodi, Ankur Srivastava
2006	A*	`conf`	Variability driven gate sizing for binning yield optimization. DAC Azadeh Davoodi, Ankur Srivastava
2005	J	`jnl`	Power-driven simultaneous resource binding and floorplanning: a probabilistic approach. IEEE Trans. Very Large Scale Integr. Syst. Azadeh Davoodi, Ankur Srivastava
2005	A	`conf`	Probabilistic dual-Vth leakage optimization under variability. ISLPED Azadeh Davoodi, Ankur Srivastava
2005	J	`jnl`	Simultaneous V IEEE Trans. Very Large Scale Integr. Syst. Vishal Khandelwal, Azadeh Davoodi, Ankur Srivastava
2005	—	`conf`	Simultaneous floorplanning and resource binding: a probabilistic approach. ASP-DAC Azadeh Davoodi, Ankur Srivastava
2005	C	`conf`	Variability-Driven Buffer Insertion Considering Correlations. ICCD Azadeh Davoodi, Ankur Srivastava
2005	J	`jnl`	Voltage scheduling under unpredictabilities: a risk management paradigm. ACM Trans. Design Autom. Electr. Syst. Azadeh Davoodi, Ankur Srivastava
2005	—	`conf`	Wake-up protocols for controlling current surges in MTCMOS-based technology. ASP-DAC Azadeh Davoodi, Ankur Srivastava
2004	A	`conf`	Efficient statistical timing analysis through error budgeting. ICCAD Vishal Khandelwal, Azadeh Davoodi, Ankur Srivastava
2004	J	`jnl`	Empirical models for net-length probability distribution and applications. IEEE Trans. Very Large Scale Integr. Syst. Azadeh Davoodi, Vishal Khandelwal, Ankur Srivastava
2004	—	`conf`	High level techniques for power-grid noise immunity. ACM Great Lakes Symposium on VLSI Azadeh Davoodi, Vishal Khandelwal, Ankur Srivastava
2004	A	`conf`	Variability inspired implementation selection problem. ICCAD Azadeh Davoodi, Vishal Khandelwal, Ankur Srivastava
2004	A	`conf`	Wire-length prediction using statistical techniques. ICCAD Jennifer L. Wong, Azadeh Davoodi, Vishal Khandelwal, Ankur Srivastava, Miodrag Potkonjak
2003	A	`conf`	A Probabilistic Approach to Buffer Insertion. ICCAD Vishal Khandelwal, Azadeh Davoodi, Akash Nanavati, Ankur Srivastava
2003	A	`conf`	Effective graph theoretic techniques for the generalized low power binding problem. ISLPED Azadeh Davoodi, Ankur Srivastava
2003	A	`conf`	Voltage scheduling under unpredictabilities: a risk management paradigm. ISLPED Azadeh Davoodi, Ankur Srivastava