Azadeh Alsadat Emrani Zarandi

16 papers C 1Journal 12Unranked 2
YearRankTypeTitle / Venue / Authors
2026 J jnl
Improving the network efficiency of IoT using embedded fault-resilient services.
Clust. Comput.
Mohana Farzin, Azadeh Alsadat Emrani Zarandi
2024 J jnl
An efficient multi-format low-precision floating-point multiplier.
Sustain. Comput. Informatics Syst.
Hadis Ahmadpour Kermani, Azadeh Alsadat Emrani Zarandi
2023 J jnl
uLog: a software-based approximate logarithmic number system for computations on SIMD processors.
J. Supercomput.
Saeedeh Jahanshahi, Amir Sabbagh Molahosseini, Azadeh Alsadat Emrani Zarandi
2022 J jnl
Effect of the Spectrum Sensing Period on the TCP Performance Over Cognitive Radio Ad-hoc Networks.
Wirel. Pers. Commun.
Mohammad Mehdi Hassani, Sanaz Pashmforoush, Azadeh Alsadat Emrani Zarandi
2022 — ch.
Low-Precision Floating-Point Formats: From General-Purpose to Application-Specific.
Approximate Computing
Amir Sabbagh Molahosseini, Leonel Sousa, Azadeh Alsadat Emrani Zarandi, Hans Vandierendonck
2021 J jnl
A Multifunctional Unit For Reverse Conversion and Sign Detection Based on The 5-Moduli Set.
Comput. Sci.
Mohsen Mojahed, Amir Sabbagh Molahosseini, Azadeh Alsadat Emrani Zarandi
2021 J jnl
Variable Latency Carry Speculative Adders with Input-based Dynamic Configuration.
Comput. Electr. Eng.
Hoda Ghabeli, Amir Sabbagh Molahosseini, Azadeh Alsadat Emrani Zarandi, Leonel Sousa
2019 J jnl
Efficient Modular Adder Designs Based on Thermometer and One-Hot Coding.
IEEE Trans. Very Large Scale Integr. Syst.
Fereshteh Jafarzadehpour, Amir Sabbagh Molahosseini, Azadeh Alsadat Emrani Zarandi, Leonel Sousa
2019 J jnl
New energy-efficient hybrid wide-operand adder architecture.
IET Circuits Devices Syst.
Fereshteh Jafarzadehpour, Amir Sabbagh Molahosseini, Azadeh Alsadat Emrani Zarandi, Leonel Sousa
2018 C conf
Towards Efficient Modular Adders based on Reversible Circuits.
ISCAS
Amir Sabbagh Molahosseini, Ailin Asadpoor, Azadeh Alsadat Emrani Zarandi, Leonel Sousa
2017 J jnl
A Multifunctional Unit for Designing Efficient RNS-Based Datapaths.
IEEE Access
Amir Sabbagh Molahosseini, Azadeh Alsadat Emrani Zarandi, Paulo Martins, Leonel Sousa
2017 J jnl
An Efficient Component for Designing Signed Reverse Converters for a Class of RNS Moduli Sets of Composite Form {2
IEEE Trans. Very Large Scale Integr. Syst.
Azadeh Alsadat Emrani Zarandi, Amir Sabbagh Molahosseini, Leonel Sousa, Mehdi Hosseinzadeh
2016 — conf
Area-delay-power-aware adder placement method for RNS reverse converter design.
LASCAS
Azadeh Alsadat Emrani Zarandi, Amir Sabbagh Molahosseini, Leonel Sousa, Mehdi Hosseinzadeh, Keivan Navi
2015 J jnl
Reverse Converter Design via Parallel-Prefix Adders: Novel Components, Methodology, and Implementations.
IEEE Trans. Very Large Scale Integr. Syst.
Azadeh Alsadat Emrani Zarandi, Amir Sabbagh Molahosseini, Mehdi Hosseinzadeh, Saeid Sorouri, Samuel Antão, Leonel Sousa
2014 — conf
Rethinking reverse converter design: From algorithms to hardware components.
ISIC
Amir Sabbagh Molahosseini, Azadeh Alsadat Emrani Zarandi, Seyed Mostafa Mirhosseini, Mehdi Hosseinzadeh
2012 J jnl
MSDP with ACO: A maximal SRLG disjoint routing algorithm based on ant colony optimization.
J. Netw. Comput. Appl.
Mohammad Javad Rostami, Azadeh Alsadat Emrani Zarandi, Seyed Mohamad Hoseininasab