Azad Naeemi - RankMe

52 papers A* 4A 5B 1C 2Journal 16Unranked 24

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	Content Addressable Memory Design with Reference Resistor for Improved Search Resolution. CoRR Siri Narla, Steven J. Koester, Rebecca A. Dawley, Ageeth A. Bol, Piyush Kumar, Azad Naeemi
2024	J	`jnl`	A 5T-2MTJ STT-assisted Spin Orbit Torque based Ternary Content Addressable Memory for Hardware Accelerators. CoRR Siri Narla, Piyush Kumar, Azad Naeemi
2024	J	`jnl`	Cross-layer Modeling and Design of Content Addressable Memories in Advanced Technology Nodes for Similarity Search. CoRR Siri Narla, Piyush Kumar, Mohammad Adnaan, Azad Naeemi
2024	C	`conf`	WIP: Towards a Georgia Tech Semiconductor Experience for Underclassmen. FIE William L. Schaffer, Ajeet Rohatgi, Azad Naeemi, A. Bruno Frazier
2023	J	`jnl`	Towards Area Efficient Logic Circuit: Exploring Potential of Reconfigurable Gate by Generic Exact Synthesis. IEEE Open J. Comput. Soc. Liuting Shang, Azad Naeemi, Chenyun Pan
2022	—	`conf`	Performance Benchmarking of Spin-Orbit Torque Magnetic RAM (SOT-MRAM) for Deep Neural Network (DNN) Accelerators. IMW Yandong Luo, Piyush Kumar, Yu-Ching Liao, William Hwang, Fen Xue, Wilman Tsai, Shan X. Wang, Azad Naeemi, Shimeng Yu
2021	J	`jnl`	Physics-Based Models for Magneto-Electric Spin-Orbit Logic Circuits. CoRR Hai Li, Dmitri E. Nikonov, Chia-Ching Lin, Kerem Yunus Çamsari, Yu-Ching Liao, Chia-Sheng Hsu, Azad Naeemi, Ian A. Young
2020	A	`conf`	Multiplier Architectures: Challenges and Opportunities with Plasmonic-based Logic : (Special Session Paper). DATE Eleonora Testa, Samantha Lubaba Noor, Odysseas Zografos, Mathias Soeken, Francky Catthoor, Azad Naeemi, Giovanni De Micheli
2019	J	`jnl`	A Mixed Signal Architecture for Convolutional Neural Networks. ACM J. Emerg. Technol. Comput. Syst. Qiuwen Lou, Chenyun Pan, John McGuinness, András Horváth, Azad Naeemi, Michael T. Niemier, Xiaobo Sharon Hu
2019	—	`conf`	Beyond Motivation and Memorization: Fostering Scientific Inquiry with Games. CHI PLAY (Companion) Aditya Anupam, Shubhangi Gupta, Azad Naeemi, Nassim Parvin
2018	J	`jnl`	A mixed signal architecture for convolutional neural networks. CoRR Qiuwen Lou, Chenyun Pan, John McGuinness, András Horváth, Azad Naeemi, Michael T. Niemier, Xiaobo Sharon Hu
2018	A*	`conf`	Accurate processor-level wirelength distribution model for technology pathfinding using a modernized interpretation of rent's rule. DAC Divya Prasad, Saurabh Sinha, Brian Cline, Steve Moore, Azad Naeemi
2018	—	`conf`	Generic system-level modeling and optimization for beyond CMOS device applications. ISQED Victor Huang, Chenyun Pan, Azad Naeemi
2018	—	`conf`	Hybrid piezoelectric-magnetic neurons: a proposal for energy-efficient machine learning. ACM Southeast Regional Conference William Scott, Jonathan Jeffrey, Blake Heard, Dmitri E. Nikonov, Ian A. Young, Sasikanth Manipatruni, Azad Naeemi, Rouhollah Mousavi Iraei
2018	J	`jnl`	Particle in a Box: An Experiential Environment for Learning Introductory Quantum Mechanics. IEEE Trans. Educ. Aditya Anupam, Ridhima Gupta, Azad Naeemi, Nassim Jafarinaimi
2017	A*	`conf`	A Pathway to Enable Exponential Scaling for the Beyond-CMOS Era: Invited. DAC Jianping Wang, Sachin S. Sapatnekar, Chris H. Kim, Paul A. Crowell, Steven J. Koester, Supriyo Datta, Kaushik Roy, Anand Raghunathan, Xiaobo Sharon Hu, Michael T. Niemier, Azad Naeemi, Chia-Ling Chien, Caroline A. Ross, Roland Kawakami
2017	J	`jnl`	Beyond-CMOS Device Benchmarking for Boolean and Non-Boolean Logic Applications. CoRR Chenyun Pan, Azad Naeemi
2017	A	`conf`	Beyond-CMOS non-Boolean logic benchmarking: Insights and future directions. DATE Chenyun Pan, Azad Naeemi
2017	J	`jnl`	Clocked Magnetostriction-Assisted Spintronic Device Design and Simulation. CoRR Rouhollah Mousavi Iraei, Nickvash Kani, Sourav Dutta, Dmitri E. Nikonov, Sasikanth Manipatruni, Ian A. Young, John T. Heron, Azad Naeemi
2016	J	`jnl`	A Proposal for Energy-Efficient Cellular Neural Network based on Spintronic Devices. CoRR Chenyun Pan, Azad Naeemi
2016	—	`conf`	Device/system performance modeling of stacked lateral NWFET logic. ISQED Victor Huang, Chenyun Pan, Dmitry Yakimets, Praveen Raghavan, Azad Naeemi
2016	—	`conf`	Impact of interconnect variability on circuit performance in advanced technology nodes. ISQED Divya Prasad, Chenyun Pan, Azad Naeemi
2016	J	`jnl`	Low-power Spin Valve Logic using Spin-transfer Torque with Automotion of Domain Walls. CoRR Sou-Chi Chang, Sasikanth Manipatruni, Dmitri E. Nikonov, Ian A. Young, Azad Naeemi
2016	J	`jnl`	Non-volatile spin wave majority gate at the nanoscale. CoRR Odysseas Zografos, Sourav Dutta, Mauricio Manfrini, Adrien Vaysset, Bart Sorée, Azad Naeemi, Praveen Raghavan, Rudy Lauwereins, Iuliana P. Radu
2016	—	`conf`	Performance modeling and optimization for on-chip interconnects in 3D memory arrays. ISQED Javaneh Mohseni, Chenyun Pan, Azad Naeemi
2015	J	`jnl`	A Fast System-Level Design Methodology for Heterogeneous Multi-Core Processors Using Emerging Technologies. IEEE J. Emerg. Sel. Topics Circuits Syst. Chenyun Pan, Azad Naeemi
2015	J	`jnl`	Smart Detector Cell: A Scalable All-Spin Circuit for Low Power Non-Boolean Pattern Recognition. CoRR Hamidreza Aghasi, Ruohollah Mousavi Iraei, Azad Naeemi, Ehsan Afshari
2015	—	`conf`	Technology/circuit co-optimization and benchmarking for graphene interconnects at Sub-10nm technology node. ISQED Chenyun Pan, Praveen Raghavan, Francky Catthoor, Zsolt Tokei, Azad Naeemi
2014	—	`conf`	An analytical approach to system-level variation analysis and optimization for multi-core processor. ISQED Chenyun Pan, Saibal Mukhopadhyay, Azad Naeemi
2014	A*	`conf`	BEOL Scaling Limits and Next Generation Technology Prospects. DAC Azad Naeemi, Ahmet Ceyhan, Vachan Kumar, Chenyun Pan, Rouhollah M. Iraei, Shaloo Rakheja
2014	C	`conf`	Interactive visualizations for teaching quantum mechanics and semiconductor physics. FIE Rose Peng, Bill Dorn, Azad Naeemi, Nassim Jafarinaimi
2014	A	`conf`	Performance modeling for emerging interconnect technologies in CMOS and beyond-CMOS circuits. ISLPED Sou-Chi Chang, Ahmet Ceyhan, Vachan Kumar, Azad Naeemi
2014	—	`conf`	Pipeline design in spintronic circuits. NANOARCH Nickvash Kani, Azad Naeemi
2014	—	`conf`	Wiring resource minimization for physically-complex Network-on-Chip architectures. SoCC Nickvash Kani, Azad Naeemi
2013	J	`jnl`	Evaluation of the Potential Performance of Graphene Nanoribbons as On-Chip Interconnects. Proc. IEEE Shaloo Rakheja, Vachan Kumar, Azad Naeemi
2013	—	`conf`	Impact of conventional and emerging interconnects on the circuit performance of various post-CMOS devices. ISQED Ahmet Ceyhan, Azad Naeemi
2013	—	`conf`	Performance modeling for interconnects for conventional and emerging switches. SLIP Shaloo Rakheja, Vachan Kumar, Azad Naeemi
2013	—	`conf`	System-level optimization and benchmarking for InAs nanowire based gate-all-around tunneling FETs. ISQED Chenyun Pan, Ahmet Ceyhan, Azad Naeemi
2012	—	`conf`	Device- and system-level performance modeling for graphene P-N junction logic. ISQED Chenyun Pan, Azad Naeemi
2012	—	`conf`	Interconnect analysis in spin-torque devices: Performance modeling, sptimal repeater insertion, and circuit-size limits. ISQED Shaloo Rakheja, Azad Naeemi
2012	—	`conf`	System-level design and performance modeling for multilevel interconnect networks for carbon nanotube field-effect transistors. ICICDT Ahmet Ceyhan, Azad Naeemi
2012	—	`conf`	System-level optimization and benchmarking of graphene PN junction logic system based on empirical CPI model. ICICDT Chenyun Pan, Azad Naeemi
2011	—	`conf`	Interconnection aspects of spin torque devices: Delay, energy-per-bit, and circuit size modeling. ISQED Shaloo Rakheja, Azad Naeemi
2011	B	`conf`	Power Aware Post-manufacture Tuning of Analog Nanocircuits. ETS Aritra Banerjee, Subho Chatterjee, Azad Naeemi, Abhijit Chatterjee
2010	—	`conf`	Nanoelectronics in retrospect, prospect and principle. ISSCC James D. Meindl, Azad Naeemi, Muhannad S. Bakir, R. Murali
2008	—	`conf`	3D heterogeneous integrated systems: Liquid cooling, power delivery, and implementation. CICC Muhannad S. Bakir, Calvin King, Deepak C. Sekar, Hiren D. Thacker, Bing Dang, Gang Huang, Azad Naeemi, James D. Meindl
2008	A	`conf`	Physical models for electron transport in graphene nanoribbons and their junctions. ICCAD Azad Naeemi, James D. Meindl
2007	—	`conf`	Carbon nanotube interconnects. ISPD Azad Naeemi, James D. Meindl
2007	A	`conf`	IntSim: A CAD tool for optimization of multilevel interconnect networks. ICCAD Deepak C. Sekar, Azad Naeemi, Reza Sarvari, Jeffrey A. Davis, James D. Meindl
2007	A*	`conf`	Performance Modeling and Optimization for Single- and Multi-Wall Carbon Nanotube Interconnects. DAC Azad Naeemi, Reza Sarvari, James D. Meindl
2007	—	`conf`	Physical Model for Power Supply Noise and Chip/Package Co-Design in Gigascale Systems with the Consideration of Hot Spots. CICC Gang Huang, Deepak C. Sekar, Azad Naeemi, Kaveh Shakeri, James D. Meindl
2006	—	`conf`	Chip-level and Input/Output Interconnects for Gigascale SOCs: Limits and Opportunities. SoCC Azad Naeemi, Muhannad S. Bakir