Ayan Palchaudhuri

29 papers A 1C 1Misc 10Journal 9Unranked 7

Year	Rank	Type	Title / Venue / Authors
2026	Misc	`conf`	FPGA Optimized Pipelined Modulo Computation Architecture Leveraging Primitive Instantiation and Placement Constraints for Efficient Logic Packing. VLSID Suprabhat Bhattacharjee, Ayan Palchaudhuri
2025	Misc	`conf`	Fast Bit-Sliced VLSI Architectures on FPGA for Montgomery Domain Modular Inversion. VLSID Soham Adhikary, Ayan Palchaudhuri
2025	Misc	`conf`	Leveraging Dual Output LUTs with Pipelining for Efficient BCD to Binary Converter on FPGA. VLSID Santosh Kumar, Ayan Palchaudhuri
2024	—	`conf`	Exploring Efficient BCD to Binary Conversion Architecture Alternatives on FPGA. HIPCW Santosh Kumar, Ayan Palchaudhuri
2024	Misc	`conf`	FPGA Specific Speed-Area Optimized Architectures of Arithmetic Cores with Scan Insertion for Carry Chain Based Multi-level Logic Implementation. VLSID Ayan Palchaudhuri, Anindya Sundar Dhar
2022	J	`jnl`	FPGA fabric conscious architecture design and automation of speed-area efficient Margolus neighborhood based cellular automata with variegated scan path insertion. J. Parallel Distributed Comput. Ayan Palchaudhuri, Digvijay Anand, Anindya Sundar Dhar
2021	J	`jnl`	Design Automation for Tree-based Nearest Neighborhood-aware Placement of High-speed Cellular Automata on FPGA with Scan Path Insertion. ACM Trans. Design Autom. Electr. Syst. Ayan Palchaudhuri, Sandeep Sharma, Anindya Sundar Dhar
2021	J	`jnl`	Speed-area optimized VLSI architecture of multi-bit cellular automaton cell based random number generator on FPGA with testable logic support. J. Parallel Distributed Comput. Ayan Palchaudhuri, Anindya Sundar Dhar
2020	A	`conf`	Placement Aware Design and Automation of High Speed Architectures for Tree-Structured Linear Cellular Automata on FPGAs with Scan Path Insertion. FPGA Ayan Palchaudhuri, Sandeep Sharma, Anindya Sundar Dhar
2020	Misc	`conf`	Primitive Instantiation for Speed-Area Efficient Architecture Design of Cellular Automata based Mageto Logic on FPGA with Built-In Testability. FCCM Ayan Palchaudhuri, Anindya Sundar Dhar
2020	J	`jnl`	Testable Architecture Design for Programmable Cellular Automata on FPGA Using Run-Time Dynamically Reconfigurable Look-Up Tables. J. Electron. Test. Ayan Palchaudhuri, Anindya Sundar Dhar
2019	J	`jnl`	Design and automation of VLSI architectures for bidirectional scan based fault localization approach in FPGA fabric aware cellular automata topologies. J. Parallel Distributed Comput. Ayan Palchaudhuri, Anindya Sundar Dhar
2019	Misc	`conf`	FPGA Fabric Conscious Design and Implementation of Speed-Area Efficient Signed Digit Add-Subtract Logic through Primitive Instantiation. ACSSC Ayan Palchaudhuri, Anindya Sundar Dhar
2019	J	`jnl`	Fault Localization and Testability Approaches for FPGA Fabric Aware Canonic Signed Digit Recoding Implementations. J. Electron. Test. Ayan Palchaudhuri, Anindya Sundar Dhar
2019	Misc	`conf`	VLSI Architectures for Jacobi Symbol Computation. VLSID Ayan Palchaudhuri, Anindya Sundar Dhar
2018	—	`conf`	Fast Carry Chain Based Architectures for Two's Complement to CSD Recoding on FPGAs. ARC Ayan Palchaudhuri, Anindya Sundar Dhar
2018	Misc	`conf`	High Speed FPGA Fabric Aware CSD Recoding with Run-Time Support for Fault Localization. VLSID Ayan Palchaudhuri, Anindya Sundar Dhar
2018	—	`conf`	Redundant Binary to Two's Complement Converter on FPGAs Through Fabric Aware Scan Based Encoding Approach for Fault Localization Support. IPDPS Workshops Ayan Palchaudhuri, Anindya Sundar Dhar
2017	J	`jnl`	Built-In Fault Localization Circuitry for High Performance FPGA Based Implementations. J. Electron. Test. Ayan Palchaudhuri, Anindya Sundar Dhar
2017	J	`jnl`	Efficient Automated Implementation of Testable Cellular Automata Based Pseudorandom Generator Circuits on FPGAs. J. Cell. Autom. Ayan Palchaudhuri, Amrit Anand Amresh, Anindya Sundar Dhar
2017	—	`conf`	Primitive Instantiation Based Fault Localization Circuitry for High Performance FPGA Designs. VDAT Ayan Palchaudhuri, Anindya Sundar Dhar
2017	Misc	`conf`	Redundant Arithmetic Based High Speed Carry Free Hybrid Adders with Built-In Scan Chain on FPGAs. HiPC Ayan Palchaudhuri, Anindya Sundar Dhar
2016	Misc	`conf`	Efficient Implementation of Scan Register Insertion on Integer Arithmetic Cores for FPGAs. VLSID Ayan Palchaudhuri, Anindya Sundar Dhar
2016	—	`conf`	High performance bit-sliced pipelined comparator tree for FPGAs. VDAT Ayan Palchaudhuri, Anindya Sundar Dhar
2015	—	`ch.`	A Fabric Component Based Approach to the Architecture and Design Automation of High-Performance Integer Arithmetic Circuits on FPGA. Computational Intelligence in Digital and Network Designs and Applications Ayan Palchaudhuri, Rajat Subhra Chakraborty
2015	C	`conf`	Automated Design of High Performance Integer Arithmetic Cores on FPGA. DSD Ayan Palchaudhuri, Rajat Subhra Chakraborty, Durga Prasad Sahoo
2014	—	`conf`	Highly Compact Automated Implementation of Linear CA on FPGAs. ACRI Ayan Palchaudhuri, Rajat Subhra Chakraborty, Mohammad Salman, Sreemukh Kardas, Debdeep Mukhopadhyay
2013	J	`jnl`	Hardware Trojan Insertion by Direct Modification of FPGA Configuration Bitstream. IEEE Des. Test Rajat Subhra Chakraborty, Indrasish Saha, Ayan Palchaudhuri, Gowtham Kumar Naik
2012	—	`conf`	Effect of Malicious Hardware Logic on Circuit Reliability. VDAT Sanjay Burman, Ayan Palchaudhuri, Rajat Subhra Chakraborty, Debdeep Mukhopadhyay, Pranav Singh