Avinoam Kolodny

103 papers A 3B 1C 9Journal 50Unranked 39

Year	Rank	Type	Title / Venue / Authors
2019	J	`jnl`	Links as a Service (LaaS): Guaranteed Tenant Isolation in the Shared Cloud. IEEE J. Sel. Areas Commun. Eitan Zahavi, Alexander Shpiner, Ori Rottenstreich, Avinoam Kolodny, Isaac Keslassy
2017	J	`jnl`	Optimizing Read-Once Data Flow in Big-Data Applications. IEEE Comput. Archit. Lett. Tomer Y. Morad, Gil Shomron, Mattan Erez, Avinoam Kolodny, Uri C. Weiser
2016	J	`jnl`	Design and dynamic management of hierarchical NoCs. Microprocess. Microsystems Ran Manevich, Israel Cidon, Avinoam Kolodny
2016	J	`jnl`	EFS: Energy-Friendly Scheduler for memory bandwidth constrained systems. J. Parallel Distributed Comput. Tomer Y. Morad, Noam Shalev, Idit Keidar, Avinoam Kolodny, Uri C. Weiser
2016	—	`conf`	Links as a Service (LaaS): Guaranteed Tenant Isolation in the Shared Cloud. ANCS Eitan Zahavi, Alexander Shpiner, Ori Rottenstreich, Avinoam Kolodny, Isaac Keslassy
2015	J	`jnl`	Average latency and link utilization analysis of heterogeneous wormhole NoCs. Integr. Yaniv Ben-Itzhak, Israel Cidon, Avinoam Kolodny
2015	J	`jnl`	Heterogeneous NoC Router Architecture. IEEE Trans. Parallel Distributed Syst. Yaniv Ben-Itzhak, Israel Cidon, Avinoam Kolodny, Michael Shabun, Nir Shmuel
2015	J	`jnl`	Links as a Service (LaaS): Feeling Alone in the Shared Cloud. CoRR Eitan Zahavi, Alexander Shpiner, Ori Rottenstreich, Avinoam Kolodny, Isaac Keslassy
2015	J	`jnl`	Memristor-Based Multilayer Neural Networks With Online Gradient Descent Training. IEEE Trans. Neural Networks Learn. Syst. Daniel Soudry, Dotan Di Castro, Asaf Gal, Avinoam Kolodny, Shahar Kvatinsky
2015	J	`jnl`	Multistate Register Based on Resistive RAM. IEEE Trans. Very Large Scale Integr. Syst. Ravi Patel, Shahar Kvatinsky, Eby G. Friedman, Avinoam Kolodny
2015	J	`jnl`	Timing-constrained power minimization in VLSI circuits by simultaneous multilayer wire spacing. Integr. Konstantin Moiseev, Shmuel Wimer, Avinoam Kolodny
2015	J	`jnl`	VTEAM: A General Model for Voltage-Controlled Memristors. IEEE Trans. Circuits Syst. II Express Briefs Shahar Kvatinsky, Misbah Ramadan, Eby G. Friedman, Avinoam Kolodny
2014	J	`jnl`	Designing single-cycle long links in hierarchical NoCs. Microprocess. Microsystems Ran Manevich, Leon Polishuk, Israel Cidon, Avinoam Kolodny
2014	J	`jnl`	Distributed Adaptive Routing Convergence to Non-Blocking DCN Routing Assignments. IEEE J. Sel. Areas Commun. Eitan Zahavi, Isaac Keslassy, Avinoam Kolodny
2014	J	`jnl`	Logic operations in memory using a memristive Akers array. Microelectron. J. Yifat Levy, Jehoshua Bruck, Yuval Cassuto, Eby G. Friedman, Avinoam Kolodny, Eitan Yaakobi, Shahar Kvatinsky
2014	J	`jnl`	MAGIC - Memristor-Aided Logic. IEEE Trans. Circuits Syst. II Express Briefs Shahar Kvatinsky, Dmitry Belousov, Slavik Liman, Guy Satat, Nimrod Wald, Eby G. Friedman, Avinoam Kolodny, Uri C. Weiser
2014	J	`jnl`	Memristor-Based Material Implication (IMPLY) Logic: Design Principles and Methodologies. IEEE Trans. Very Large Scale Integr. Syst. Shahar Kvatinsky, Guy Satat, Nimrod Wald, Eby G. Friedman, Avinoam Kolodny, Uri C. Weiser
2014	J	`jnl`	Memristor-Based Multithreading. IEEE Comput. Archit. Lett. Shahar Kvatinsky, Yuval H. Nacson, Yoav Etsion, Eby G. Friedman, Avinoam Kolodny, Uri C. Weiser
2014	—	`conf`	Quasi Fat Trees for HPC Clouds and Their Fault-Resilient Closed-Form Routing. Hot Interconnects Eitan Zahavi, Isaac Keslassy, Avinoam Kolodny
2013	C	`conf`	Design Tradeoffs of Long Links in Hierarchical Tiled Networks-on-Chip. DSD Ran Manevich, Leon Polishuk, Israel Cidon, Avinoam Kolodny
2013	—	`conf`	Dynamic traffic distribution among hierarchy levels in hierarchical Networks-on-Chip (NoCs). NOCS Ran Manevich, Israel Cidon, Avinoam Kolodny
2013	J	`jnl`	Gana: A novel low-cost conflict-free NoC architecture. ACM Trans. Embed. Comput. Syst. Eitan Zahavi, Israel Cidon, Avinoam Kolodny
2013	J	`jnl`	TEAM: ThrEshold Adaptive Memristor Model. IEEE Trans. Circuits Syst. I Regul. Pap. Shahar Kvatinsky, Eby G. Friedman, Avinoam Kolodny, Uri C. Weiser
2013	J	`jnl`	Timing-driven variation-aware synthesis of hybrid mesh/tree clock distribution networks. Integr. Ameer Abdelhadi, Ran Ginosar, Avinoam Kolodny, Eby G. Friedman
2013	—	`conf`	ViLoCoN - An ultra-lightweight lossless VLSI video codec. SoCC Shani Rehana, Or Turgeman, Ran Manevich, Avinoam Kolodny
2012	—	`conf`	Distributed adaptive routing for big-data applications running on data center networks. ANCS Eitan Zahavi, Isaac Keslassy, Avinoam Kolodny
2012	C	`conf`	Energy metrics for power efficient crosslink and mesh topologies. ISCAS Inna Vaisband, Eby G. Friedman, Ran Ginosar, Avinoam Kolodny
2012	J	`jnl`	Exploring the limits of GPGPU scheduling in control flow bound applications. ACM Trans. Archit. Code Optim. Roman Malits, Evgeny Bolotin, Avinoam Kolodny, Avi Mendelson
2012	—	`conf`	HNOCS: Modular open-source simulator for Heterogeneous NoCs. ICSAMOS Yaniv Ben-Itzhak, Eitan Zahavi, Israel Cidon, Avinoam Kolodny
2012	—	`conf`	Handling global traffic in future CMP NoCs. SLIP Ran Manevich, Israel Cidon, Avinoam Kolodny
2012	J	`jnl`	Multi-aggressor capacitive and inductive coupling noise modeling and mitigation. Microelectron. J. Victoria Vishnyakov, Eby G. Friedman, Avinoam Kolodny
2012	—	`conf`	Optimizing heterogeneous NoC design. SLIP Yaniv Ben-Itzhak, Israel Cidon, Avinoam Kolodny
2012	J	`jnl`	Task Scheduling Based On Thread Essence and Resource Limitations. J. Comput. Tomer Y. Morad, Avinoam Kolodny, Uri C. Weiser
2012	J	`jnl`	The complexity of VLSI power-delay optimization by interconnect resizing. J. Comb. Optim. Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer
2011	C	`conf`	A Cost Effective Centralized Adaptive Routing for Networks-on-Chip. DSD Ran Manevich, Israel Cidon, Avinoam Kolodny, Isask'har Walter, Shmuel Wimer
2011	C	`conf`	An on-chip metastability measurement circuit to characterize synchronization behavior in 65nm. ISCAS Salomon Beer, Ran Ginosar, Michael Priel, Rostislav (Reuven) Dobkin, Avinoam Kolodny
2011	—	`conf`	Delay analysis of wormhole based heterogeneous NoC. NOCS Yaniv Ben-Itzhak, Israel Cidon, Avinoam Kolodny
2011	J	`jnl`	Finding the Energy Efficient Curve: Gate Sizing for Minimum Power under Delay Constraints. VLSI Design Yoni Aizik, Avinoam Kolodny
2011	—	`ch.`	Latency-Constrained, Power-Optimized NoC Design for a 4G SoC: A Case Study. Low Power Networks-on-Chip Rudy Beraha, Isask'har Walter, Israel Cidon, Avinoam Kolodny
2011	C	`conf`	Memristor-based IMPLY logic design procedure. ICCD Shahar Kvatinsky, Avinoam Kolodny, Uri C. Weiser, Eby G. Friedman
2011	—	`conf`	NoCs simulation framework for OMNeT++. NOCS Yaniv Ben-Itzhak, Eitan Zahavi, Israel Cidon, Avinoam Kolodny
2011	J	`jnl`	Static timing analysis for modeling QoS in networks-on-chip. J. Parallel Distributed Comput. Evgeni Krimer, Isaac Keslassy, Avinoam Kolodny, Isask'har Walter, Mattan Erez
2010	J	`jnl`	Asynchronous Current Mode Serial Communication. IEEE Trans. Very Large Scale Integr. Syst. Rostislav (Reuven) Dobkin, Michael Moyal, Avinoam Kolodny, Ran Ginosar
2010	J	`jnl`	Centralized Adaptive Routing for NoCs. IEEE Comput. Archit. Lett. Ran Manevich, Israel Cidon, Avinoam Kolodny, Isask'har Walter
2010	J	`jnl`	Corrections to "Unified Logical Effort - A Method for Delay Evaluation and Minimization in Logic Paths With RC Interconnect" [May 10 689-696]. IEEE Trans. Very Large Scale Integr. Syst. Arkadiy Morgenshtein, Eby G. Friedman, Ran Ginosar, Avinoam Kolodny
2010	—	`conf`	Efficiency optimization of integrated DC-DC buck converters. ICECS Gregory Sizikov, Avinoam Kolodny, Eby G. Friedman, Michael Zelikson
2010	J	`jnl`	Interconnect Bundle Sizing Under Discrete Design Rules. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer
2010	—	`conf`	Interconnect power and delay optimization by dynamic programming in gridded design rules. ISPD Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer
2010	A	`conf`	Leveraging application-level requirements in the design of a NoC for a 4G SoC - a case study. DATE Rudy Beraha, Isask'har Walter, Israel Cidon, Avinoam Kolodny
2010	—	`conf`	Performance and Power Aware CMP Thread Allocation Modeling. HiPEAC Yaniv Ben-Itzhak, Israel Cidon, Avinoam Kolodny
2010	—	`conf`	Scheduling Multiple Multithreaded Applications on Asymmetric and Symmetric Chip Multiprocessors. PAAP Tomer Y. Morad, Avinoam Kolodny, Uri C. Weiser
2010	—	`conf`	The Devolution of Synchronizers. ASYNC Salomon Beer, Ran Ginosar, Michael Priel, Rostislav (Reuven) Dobkin, Avinoam Kolodny
2010	C	`conf`	Threads vs. caches: Modeling the behavior of parallel workloads. ICCD Zvika Guz, Oved Itzhak, Idit Keidar, Avinoam Kolodny, Avi Mendelson, Uri C. Weiser
2010	—	`conf`	Timing-driven variation-aware nonuniform clock mesh synthesis. ACM Great Lakes Symposium on VLSI Ameer Abdelhadi, Ran Ginosar, Avinoam Kolodny, Eby G. Friedman
2010	J	`jnl`	Unified Logical Effort - A Method for Delay Evaluation and Minimization in Logic Paths With RC Interconnect. IEEE Trans. Very Large Scale Integr. Syst. Arkadiy Morgenshtein, Eby G. Friedman, Ran Ginosar, Avinoam Kolodny
2009	—	`conf`	Best of both worlds: A bus enhanced NoC (BENoC). NOCS Ran Manevich, Isask'har Walter, Israel Cidon, Avinoam Kolodny
2009	J	`jnl`	Many-Core vs. Many-Thread Machines: Stay Away From the Valley. IEEE Comput. Archit. Lett. Zvika Guz, Evgeny Bolotin, Idit Keidar, Avinoam Kolodny, Avi Mendelson, Uri C. Weiser
2009	—	`conf`	Packet-level static timing analysis for NoCs. NOCS Evgeni Krimer, Mattan Erez, Isaac Keslassy, Avinoam Kolodny, Isask'har Walter
2009	—	`conf`	Power efficient tree-based crosslinks for skew reduction. ACM Great Lakes Symposium on VLSI Inna Vaisband, Ran Ginosar, Avinoam Kolodny, Eby G. Friedman
2009	J	`jnl`	Power-delay optimization in VLSI microprocessors by wire spacing. ACM Trans. Design Autom. Electr. Syst. Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer
2009	J	`jnl`	QNoC asynchronous router. Integr. Rostislav (Reuven) Dobkin, Ran Ginosar, Avinoam Kolodny
2009	J	`jnl`	Special Section on International Symposium on Networks-on-Chip (NOCS). IEEE Trans. Very Large Scale Integr. Syst. Avinoam Kolodny, Li-Shiuan Peh
2009	—	`conf`	The design of a latency constrained, power optimized NoC for a 4G SoC. NOCS Rudy Beraha, Isask'har Walter, Israel Cidon, Avinoam Kolodny
2009	—	`conf`	The era of many-modules SoC: revisiting the NoC mapping problem. NoCArc@MICRO Isask'har Walter, Israel Cidon, Avinoam Kolodny, Daniel Sigalov
2008	J	`jnl`	BENoC: A Bus-Enhanced Network on-Chip for a Power Efficient CMP. IEEE Comput. Archit. Lett. Isask'har Walter, Israel Cidon, Avinoam Kolodny
2008	J	`jnl`	Effective Radii of On-Chip Decoupling Capacitors. IEEE Trans. Very Large Scale Integr. Syst. Mikhail Popovich, Michael Sotman, Avinoam Kolodny, Eby G. Friedman
2008	J	`jnl`	On optimal ordering of signals in parallel wire bundles. Integr. Konstantin Moiseev, Shmuel Wimer, Avinoam Kolodny
2008	J	`jnl`	On-Chip Power Distribution Grids With Multiple Supply Voltages for High-Performance Integrated Circuits. IEEE Trans. Very Large Scale Integr. Syst. Mikhail Popovich, Eby G. Friedman, Michael Sotman, Avinoam Kolodny
2008	—	`conf`	Parallel vs. serial on-chip communication. SLIP Rostislav (Reuven) Dobkin, Arkadiy Morgenshtein, Avinoam Kolodny, Ran Ginosar
2008	—	`conf`	Timing optimization in logic with interconnect. SLIP Arkadiy Morgenshtein, Eby G. Friedman, Ran Ginosar, Avinoam Kolodny
2008	J	`jnl`	Timing-aware power-optimal ordering of signals. ACM Trans. Design Autom. Electr. Syst. Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer
2008	B	`conf`	Utilizing shared data in chip multiprocessors with the nahalal architecture. SPAA Zvika Guz, Idit Keidar, Avinoam Kolodny, Uri C. Weiser
2007	—	`conf`	Access Regulation to Hot-Modules in Wormhole NoCs. NOCS Isask'har Walter, Israel Cidon, Ran Ginosar, Avinoam Kolodny
2007	—	`conf`	High Rate Wave-pipelined Asynchronous On-chip Bit-serial Data Link. ASYNC Rostislav (Reuven) Dobkin, Yevgeny Perelman, Tuvia Liran, Ran Ginosar, Avinoam Kolodny
2007	J	`jnl`	Nahalal: Cache Organization for Chip Multiprocessors. IEEE Comput. Archit. Lett. Zvika Guz, Idit Keidar, Avinoam Kolodny, Uri C. Weiser
2007	J	`jnl`	Network Delays and Link Capacities in Application-Specific Wormhole NoCs. VLSI Design Zvika Guz, Isask'har Walter, Evgeny Bolotin, Israel Cidon, Ran Ginosar, Avinoam Kolodny
2007	—	`conf`	Networks on chips: keeping up with Rent's rule and Moore's law. SLIP Avinoam Kolodny
2007	A	`conf`	Routing table minimization for irregular mesh NoCs. DATE Evgeny Bolotin, Israel Cidon, Ran Ginosar, Avinoam Kolodny
2007	—	`conf`	The Power of Priority: NoC Based Distributed Cache Coherency. NOCS Evgeny Bolotin, Zvika Guz, Israel Cidon, Ran Ginosar, Avinoam Kolodny
2007	J	`jnl`	Trace cache sampling filter. ACM Trans. Comput. Syst. Michael Behar, Avi Mendelson, Avinoam Kolodny
2006	A	`conf`	Efficient link capacity and QoS design for network-on-chip. DATE Zvika Guz, Isask'har Walter, Evgeny Bolotin, Israel Cidon, Ran Ginosar, Avinoam Kolodny
2006	—	`conf`	Fast Asynchronous Shift Register for Bit-Serial Communication. ASYNC Rostislav (Reuven) Dobkin, Ran Ginosar, Avinoam Kolodny
2006	J	`jnl`	Logic Gates as Repeaters (LGR) for Area-Efficient Timing Optimization. IEEE Trans. Very Large Scale Integr. Syst. Michael Moreinis, Arkadiy Morgenshtein, Israel A. Wagner, Avinoam Kolodny
2006	—	`conf`	Maximum effective distance of on-chip decoupling capacitors in power distribution grids. ACM Great Lakes Symposium on VLSI Mikhail Popovich, Eby G. Friedman, Michael Sotman, Avinoam Kolodny, Radu M. Secareanu
2006	C	`conf`	On-die decoupling capacitance: frequency domain analysis of activity radius. ISCAS Michael Sotman, Avinoam Kolodny, Mikhail Popovich, Eby G. Friedman
2006	J	`jnl`	Optimal bus sizing in migration of processor design. IEEE Trans. Circuits Syst. I Regul. Pap. Shmuel Wimer, Shay Michaely, Konstantin Moiseev, Avinoam Kolodny
2006	C	`conf`	Timing optimization of interconnect by simultaneous net-ordering, wire sizing and spacing. ISCAS Konstantin Moiseev, Shmuel Wimer, Avinoam Kolodny
2005	J	`jnl`	Comparison of Sigma-delta Converter Circuit Architectures in Digital Cmos Technology. J. Circuits Syst. Comput. Noam Dolev, Avner Kornfeld, Avinoam Kolodny
2005	—	`conf`	Low-leakage repeaters for NoC interconnects. ISCAS (1) Arkadiy Morgenshtein, Israel Cidon, Ran Ginosar, Avinoam Kolodny
2005	—	`conf`	On-chip power distribution grids with multiple supply voltages for high performance integrated circuits. ACM Great Lakes Symposium on VLSI Mikhail Popovich, Eby G. Friedman, Michael Sotman, Avinoam Kolodny
2005	—	`conf`	Trace Cache Sampling Filter. IEEE PACT Michael Behar, Avi Mendelson, Avinoam Kolodny
2004	—	`conf`	Automatic hardware-efficient SoC integration by QoS network on chip. ICECS Evgeny Bolotin, Arkadiy Morgenshtein, Israel Cidon, Ran Ginosar, Avinoam Kolodny
2004	—	`conf`	Comparative analysis of serial vs parallel links in NoC. SoC Arkadiy Morgenshtein, Israel Cidon, Avinoam Kolodny, Ran Ginosar
2004	J	`jnl`	Cost considerations in network on chip. Integr. Evgeny Bolotin, Israel Cidon, Ran Ginosar, Avinoam Kolodny
2004	—	`conf`	Design and modelling of network on chip interconnects using transmission lines. ICECS Anastasia Barger, David Goren, Avinoam Kolodny
2004	—	`conf`	Interconnect-power dissipation in a microprocessor. SLIP Nir Magen, Avinoam Kolodny, Uri C. Weiser, Nachum Shamir
2004	—	`conf`	Micro-modem - reliability solution for NoC communications. ICECS Arkadiy Morgenshtein, Evgeny Bolotin, Israel Cidon, Avinoam Kolodny, Ran Ginosar
2004	—	`conf`	Optimal resizing of bus wires in layout migration. ICECS Shay Michaely, Shmuel Wimer, Avinoam Kolodny
2004	J	`jnl`	QNoC: QoS architecture and design process for network on chip. J. Syst. Archit. Evgeny Bolotin, Israel Cidon, Ran Ginosar, Avinoam Kolodny
2004	—	`conf`	Repeater insertion combined with LGR methodology for on-chip interconnect timing optimization. ICECS Michael Moreinis, Arkadiy Morgenshtein, Israel A. Wagner, Avinoam Kolodny
2003	J	`jnl`	A clock-tuning circuit for system-on-chip. IEEE Trans. Very Large Scale Integr. Syst. Y. Elboim, Avinoam Kolodny, Ran Ginosar
2003	J	`jnl`	Crosstalk noise reduction in synthesized digital logic circuits. IEEE Trans. Very Large Scale Integr. Syst. O. Milter, Avinoam Kolodny
2003	C	`conf`	Logic Gates as Repeaters (LGR) for Timing Optimization of SoC Interconnects. VLSI-SOC Arkadiy Morgenshtein, Michael Moreinis, Israel A. Wagner, Avinoam Kolodny