Aurangozeb

17 papers Journal 9Unranked 8
YearRankTypeTitle / Venue / Authors
2021 J jnl
Low-Latency Burst Error Detection and Correction in Decision-Feedback Equalization.
IEEE Open J. Circuits Syst.
Shovon Dey, Aurangozeb, Masum Hossain
2020 J jnl
Sequence-Coded Multilevel Signaling for High-Speed Interface.
IEEE J. Solid State Circuits
Aurangozeb, Carson R. Dick, Maruf Mohammad, Masum Hossain
2019 — conf
A 32Gb/s 2.9pJ/b Transceiver for Sequence-Coded PAM-4 Signalling with 4-to-6dB SNR Gain in 28nm FDSOI CMOS.
ISSCC
Aurangozeb, Carson R. Dick, Maruf Mohammad, Masum Hossain
2019 — conf
Affordable Sequence Decoding Techniques for High Speed SerDes.
MWSCAS
Zarraf Huda, Shovon Dey, Aaron Monai, Aurangozeb, Masum Hossain
2019 — conf
Broadband-Tunable Cascaded Vernier Silicon Photonic Microring Filter with Temperature Tracking.
OFC
Yang Ren, David Perron, Aurangozeb, Zhiping Jiang, Masum Hossain, Vien Van
2019 J jnl
DDJ-Adaptive SAR TDC-Based Timing Recovery for Multilevel Signaling.
IEEE J. Solid State Circuits
Masum Hossain, Aurangozeb, Nhat Nguyen
2018 — conf
A Bimodal (NRZ/PAM-4) ISI Tolerant Timing Recovery with Adaptive DDJ Equalization.
A-SSCC
Masum Hossain, Aurangozeb, Nhat Nguyen
2018 J jnl
Analog to Sequence Converter-Based PAM-4 Receiver With Built-In Error Correction.
IEEE J. Solid State Circuits
Aurangozeb, Maruf Mohammad, Masum Hossain
2018 J jnl
Burst Mode Optical Receiver With 10 ns Lock Time Based on Concurrent DC Offset and Timing Recovery Technique.
JOCN
A. K. M. Delwar Hossain, Aurangozeb, Masum Hossain
2018 J jnl
Channel-Adaptive ADC and TDC for 28 Gb/s PAM-4 Digital Receiver.
IEEE J. Solid State Circuits
Aurangozeb, A. K. M. Delwar Hossain, Maruf Mohammad, Masum Hossain
2017 — conf
A 82 mW 28 Gb/s PAM-4 digital sequence decoder with built-in error correction in 28nm FDSOI.
A-SSCC
Masum Hossain, Aurangozeb, A. K. M. Delwar Hossain, Maruf Mohammad
2017 — conf
Channel adaptive ADC and TDC for 28 Gb/s PAM-4 digital receiver.
CICC
Aurangozeb, A. K. M. Delwar Hossain, Masum Hossain
2017 J jnl
Fractional-N DPLL-Based Low-Power Clocking Architecture for 1-14 Gb/s Multi-Standard Transmitter.
IEEE J. Solid State Circuits
Masum Hossain, Waleed El-Halwagy, A. K. M. Delwar Hossain, Aurangozeb
2017 J jnl
Time-Domain Arithmetic Logic Unit With Built-In Interconnect.
IEEE Trans. Very Large Scale Integr. Syst.
Aurangozeb, A. K. M. Delwar Hossain, Can Ni, Quazi Sharar, Masum Hossain
2016 — conf
A 35 mW 10 Gb/s ADC-DSP less direct digital sequence detector and equalizer in 65nm CMOS.
VLSI Circuits
A. K. M. Delwar Hossain, Aurangozeb, Maruf Mohammad, Masum Hossain
2016 — conf
Fractional-N DPLL based low power clocking architecture for 1-14 Gb/s multi-standard transmitter.
A-SSCC
Masum Hossain, Amlan Nag, Waleed El-Halwagy, A. K. M. Delwar Hossain, Aurangozeb
2015 J jnl
A 6-bit 2.5-GS/s Time-Interleaved Analog-to-Digital Converter Using Resistor-Array Sharing Digital-to-Analog Converter.
IEEE Trans. Very Large Scale Integr. Syst.
Hokyu Lee, Aurangozeb, Sejin Park, Jintae Kim, Chulwoo Kim