Atsushi Takahashi

95 papers A* 1A 5B 1C 7Misc 1Journal 50Unranked 29
YearRankTypeTitle / Venue / Authors
2025 J jnl
A Fast Three-Layer One-Side Bottleneck Channel Routing with Layout Constraints Using ILP.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Kazuya Taniguchi, Satoshi Tayu, Atsushi Takahashi, Mathieu Molongo, Makoto Minami, Katsuya Nishioka
2025 J jnl
Fast Mask Optimization Under Process Variation Using Guided Local Search on Quadratic Programming.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Naoki Nonaka, Masaki Kuramochi, Yukihide Kohira, Rina Azuma, Tomomi Matsui, Atsushi Takahashi, Chikaaki Kodama
2025 C conf
Gap Channel Routing with Fixed Wires.
ISCAS
Masayuki Shimoda, Atsushi Takahashi, Kosuke Yanagidaira, Mikiko Hirai, Toshikazu Watanabe, Toshimitsu Iwasawa, Chikaaki Kodama
2025 J jnl
Gridless Gap Channel Routing to Minimize Wirelength.
IPSJ Trans. Syst. LSI Des. Methodol.
Masayuki Shimoda, Atsushi Takahashi
2025 J jnl
Gridless Gap Channel Routing with Variable-Width Wires.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Masayuki Shimoda, Atsushi Takahashi
2025 J jnl
SDG Channel Routing to Minimize Wirelength for Generalized Channel.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Zezhong Wang, Masayuki Shimoda, Atsushi Takahashi
2025 J jnl
UEO Channel Routing Algorithm to Alleviate Local Congestion for Generalized Channels.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Zezhong Wang, Hiroto Nakayama, Masayuki Shimoda, Atsushi Takahashi, Kosuke Yanagidaira, Chikaaki Kodama
2024 C conf
BCA Channel Routing to Minimize Wirelength for Generalized Channel Problem.
ISCAS
Zezhong Wang, Masayuki Shimoda, Atsushi Takahashi
2024 J jnl
Two-layer Bottleneck Channel Track Assignment for Analog VLSI.
IPSJ Trans. Syst. LSI Des. Methodol.
Kazuya Taniguchi, Satoshi Tayu, Atsushi Takahashi, Mathieu Molongo, Makoto Minami, Katsuya Nishioka
2024 — conf
Wirelength Minimization by Gap Swap-Flip in Gridless Gap Channel Routing.
ISOCC
Masayuki Shimoda, Atsushi Takahashi
2023 J jnl
Message from the Editor-in-Chief.
IPSJ Trans. Syst. LSI Des. Methodol.
Atsushi Takahashi
2023 — ed.
Proceedings of the 28th Asia and South Pacific Design Automation Conference, ASPDAC 2023, Tokyo, Japan, January 16-19, 2023
ASPDAC
Atsushi Takahashi
2023 J jnl
Report on the 28th Asia and South Pacific Design Automation Conference.
IEEE Des. Test
Atsushi Takahashi
2022 J jnl
Message from the Editor-in-Chief.
IPSJ Trans. Syst. LSI Des. Methodol.
Atsushi Takahashi
2021 J jnl
Message from the Editor-in-Chief.
IPSJ Trans. Syst. LSI Des. Methodol.
Atsushi Takahashi
2020 J jnl
A Fast Length Matching Routing Pattern Generation Method for Set-Pair Routing Problem Using Selective Pin-Pair Connections.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Shimpei Sato, Kano Akagi, Atsushi Takahashi
2020 J jnl
Message from the Editor-in-Chief.
IPSJ Trans. Syst. LSI Des. Methodol.
Atsushi Takahashi
2019 J jnl
A Low Area Overhead Design Method for High-Performance General-Synchronous Circuits with Speculative Execution.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Shimpei Sato, Eijiro Sassa, Yuta Ukon, Atsushi Takahashi
2019 C conf
A Low Area Overhead Design for High-Performance General-Synchronous Circuits with Speculative Execution.
ISCAS
Shimpei Sato, Eijiro Sassa, Yuta Ukon, Atsushi Takahashi
2018 — conf
Pattern Similarity Metrics for Layout Pattern Classification and Their Validity Analysis by Lithographic Responses.
ISVLSI
Atsushi Takahashi, Shimpei Sato, Hiroki Ogura, Yu-Min Sung, Ting-Chi Wang
2017 J jnl
A Fast Process-Variation-Aware Mask Optimization Algorithm With a Novel Intensity Modeling.
IEEE Trans. Very Large Scale Integr. Syst.
Ahmed Awad, Atsushi Takahashi, Satoshi Tanaka, Chikaaki Kodama
2017 J jnl
A Routing Method Using Directed Grid-Graph for Self-Aligned Quadruple Patterning.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Takeshi Ihara, Toshiyuki Hongo, Atsushi Takahashi, Chikaaki Kodama
2017 J jnl
Intensity Difference Map (IDM) Accuracy Analysis for OPC Efficiency Verification and Further Enhancement.
IPSJ Trans. Syst. LSI Des. Methodol.
Ahmed Awad, Atsushi Takahashi, Satoshi Tanaka, Chikaaki Kodama
2016 J jnl
A Fast Mask Manufacturability and Process Variation Aware OPC Algorithm with Exploiting a Novel Intensity Estimation Model.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Ahmed Awad, Atsushi Takahashi, Chikaaki Kodama
2016 A conf
A fast manufacturability aware Optical Proximity Correction (OPC) algorithm with adaptive wafer image estimation.
DATE
Ahmed Awad, Atsushi Takahashi, Chikaaki Kodama
2016 A conf
Grid-based Self-Aligned Quadruple Patterning aware two dimensional routing pattern.
DATE
Takeshi Ihara, Toshiyuki Hongo, Atsushi Takahashi, Chikaaki Kodama
2016 — conf
Manufacturability-aware mask assignment in multiple patterning lithography.
APCCAS
Yukihide Kohira, Atsushi Takahashi, Tomomi Matsui, Chikaaki Kodama, Shigeki Nojima, Satoshi Tanaka
2015 J jnl
A Length Matching Routing Algorithm for Set-Pair Routing Problem.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Yuta Nakatani, Atsushi Takahashi
2015 C conf
Effective two-dimensional pattern generation for self-aligned double patterning.
ISCAS
Takeshi Ihara, Atsushi Takahashi, Chikaaki Kodama
2015 — conf
Fast mask assignment using positive semidefinite relaxation in LELECUT triple patterning lithography.
ASP-DAC
Yukihide Kohira, Tomomi Matsui, Yoko Yokoyama, Chikaaki Kodama, Atsushi Takahashi, Shigeki Nojima, Satoshi Tanaka
2015 J jnl
Self-Aligned Double and Quadruple Patterning Aware Grid Routing Methods.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chikaaki Kodama, Hirotaka Ichikawa, Koichi Nakayama, Fumiharu Nakajima, Shigeki Nojima, Toshiya Kotani, Takeshi Ihara, Atsushi Takahashi
2014 J jnl
2-SAT Based Linear Time Optimum Two-Domain Clock Skew Scheduling in General-Synchronous Framework.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Yukihide Kohira, Atsushi Takahashi
2014 — conf
2-SAT based linear time optimum two-domain clock skew scheduling.
ASP-DAC
Yukihide Kohira, Atsushi Takahashi
2014 J jnl
A Novel High-Performance Heuristic Algorithm with Application to Physical Design Optimization.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Yiqiang Sheng, Atsushi Takahashi
2014 A conf
A fast process variation and pattern fidelity aware mask optimization algorithm.
ICCAD
Ahmed Awad, Atsushi Takahashi, Satoshi Tanaka, Chikaaki Kodama
2014 B conf
Positive Semidefinite Relaxation and Approximation Algorithm for Triple Patterning Lithography.
ISAAC
Tomomi Matsui, Yukihide Kohira, Chikaaki Kodama, Atsushi Takahashi
2013 J jnl
A New Variation of Adaptive Simulated Annealing for 2D/3D Packing Optimization.
Inf. Media Technol.
Yiqiang Sheng, Atsushi Takahashi
2013 J jnl
A New Variation of Adaptive Simulated Annealing for 2D/3D Packing Optimization.
IPSJ Trans. Syst. LSI Des. Methodol.
Yiqiang Sheng, Atsushi Takahashi
2013 — conf
Dawn of computer-aided design: from graph-theory to place and route.
ISPD
Atsushi Takahashi
2013 — conf
Self-Aligned Double and Quadruple Patterning-aware grid routing with hotspots control.
ASP-DAC
Chikaaki Kodama, Hirotaka Ichikawa, Koichi Nakayama, Toshiya Kotani, Shigeki Nojima, Shoji Mimotogi, Shinji Miyamoto, Atsushi Takahashi
2012 — conf
An any-angle routing method using quasi-Newton method.
ASP-DAC
Yukihide Kohira, Atsushi Takahashi
2011 J jnl
Foreword.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Atsushi Takahashi
2011 — conf
RRA-based multi-objective optimization to mitigate the worst cases of placement.
ASICON
Yiqiang Sheng, Atsushi Takahashi, Shuichi Ueno
2011 — conf
Relay-Race Algorithm: A Novel Heuristic Approach to VLSI/PCB Placement.
ISVLSI
Yiqiang Sheng, Atsushi Takahashi, Shuichi Ueno
2011 J jnl
Single-Layer Trunk Routing Using Minimal 45-Degree Lines.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Kyosuke Shinoda, Yukihide Kohira, Atsushi Takahashi
2010 J jnl
CAFE Router: A Fast Connectivity Aware Multiple Nets Routing Algorithm for Routing Grid with Obstacles.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Yukihide Kohira, Atsushi Takahashi
2010 — conf
CAFE router: a fast connectivity aware multiple nets routing algorithm for routing grid with obstacles.
ASP-DAC
Yukihide Kohira, Atsushi Takahashi
2009 J jnl
A Fast Longer Path Algorithm for Routing Grid with Obstacles Using Biconnectivity Based Length Upper Bound.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Yukihide Kohira, Suguru Suehiro, Atsushi Takahashi
2009 — conf
A fast longer path algorithm for routing grid with obstacles using biconnectivity based length upper bound.
ASP-DAC
Yukihide Kohira, Suguru Suehiro, Atsushi Takahashi
2009 J jnl
MILP-Based Efficient Routing Method with Restricted Route Structure for 2-Layer Ball Grid Array Packages.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Yoichi Tomioka, Yoshiaki Kurata, Yukihide Kohira, Atsushi Takahashi
2009 J jnl
Minimization of Delay Insertion in Clock Period Improvement in General-Synchronous Framework.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Yukihide Kohira, Shuhei Tani, Atsushi Takahashi
2009 J jnl
Routability Driven Via Assignment Method for 2-Layer Ball Grid Array Packages.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Yoichi Tomioka, Atsushi Takahashi
2008 J jnl
A Fast Clock Scheduling for Peak Power Reduction in LSI.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Yosuke Takahashi, Yukihide Kohira, Atsushi Takahashi
2008 J jnl
A Fast Gate-Level Register Relocation Method for Circuit Size Reduction in General-Synchronous Framework.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Yukihide Kohira, Atsushi Takahashi
2008 — conf
A semi-monotonic routing method for fanin type Ball Grid Array packages.
APCCAS
Yoichi Tomioka, Atsushi Takahashi
2008 C conf
ILP-based optimization of time-multiplexed I/O assignment for multi-FPGA systems.
ISCAS
Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura, Atsushi Takahashi
2008 — conf
Minimization of delay insertion in clock period improvement in general-synchronous framework.
APCCAS
Yukihide Kohira, Shuhei Tani, Atsushi Takahashi
2008 J jnl
Optimal Time-Multiplexing in Inter-FPGA Connections for Accelerating Multi-FPGA Prototyping Systems.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura, Atsushi Takahashi
2008 — conf
Routability driven modification method of monotonic via assignment for 2-layer Ball Grid Array packages.
ASP-DAC
Yoichi Tomioka, Atsushi Takahashi
2007 C conf
A Fast Register Relocation Method for Circuit Size Reduction in Generalized-Synchronous Framework.
ISCAS
Yukihide Kohira, Atsushi Takahashi
2007 — conf
A fast clock scheduling for peak power reduction in LSI.
ACM Great Lakes Symposium on VLSI
Yosuke Takahashi, Yukihide Kohira, Atsushi Takahashi
2007 J jnl
Gate-Level Register Relocation in Generalized Synchronous Framework for Clock Period Minimization.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Yukihide Kohira, Atsushi Takahashi
2007 J jnl
Low Area Pipelined Circuits by the Replacement of Registers with Delay Elements.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Bakhtiar Affendi Rosdi, Atsushi Takahashi
2006 C conf
Evaluation of 3D-packing representations for scheduling of dynamically reconfigurable systems.
ISCAS
Yukihide Kohira, Chikaaki Kodama, Kunihiro Fujiyoshi, Atsushi Takahashi
2006 J jnl
Global Routing by Iterative Improvements for Two-Layer Ball Grid Array Packages.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yukiko Kubo, Atsushi Takahashi
2006 — conf
Low area pipelined circuits by multi-clock cycle paths and clock scheduling.
ASP-DAC
Bakhtiar Affendi Rosdi, Atsushi Takahashi
2006 — conf
Monotonic parallel and orthogonal routing for single-layer ball grid array packages.
ASP-DAC
Yoichi Tomioka, Atsushi Takahashi
2006 J jnl
Multi-Clock Cycle Paths and Clock Scheduling for Reducing the Area of Pipelined Circuits.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Bakhtiar Affendi Rosdi, Atsushi Takahashi
2006 J jnl
Practical Fast Clock-Schedule Design Algorithms.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Atsushi Takahashi
2006 — conf
Replacement of Register with Delay Element for Reducing the Area of Pipelined Circuits.
APCCAS
Bakhtiar Affendi Rosdi, Atsushi Takahashi
2006 J jnl
Routing of Monotonic Parallel and Orthogonal Netlists for Single-Layer Ball Grid Array Packages.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Yoichi Tomioka, Atsushi Takahashi
2005 J jnl
A Via Assignment and Global Routing Method for 2-Layer Ball Grid Array Packages.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Yukiko Kubo, Atsushi Takahashi
2005 — conf
A global routing method for 2-layer ball grid array packages.
ISPD
Yukiko Kubo, Atsushi Takahashi
2005 J jnl
Clock Period Minimization Method of Semi-Synchronous Circuits by Delay Insertion.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Yukihide Kohira, Atsushi Takahashi
2004 — conf
Incremental Timing Budget Management in Programmable Systems.
ERSA
Elaheh Bozorgzadeh, Soheil Ghiasi, Atsushi Takahashi, Majid Sarrafzadeh
2004 J jnl
Optimal integer delay-budget assignment on directed acyclic graphs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Elaheh Bozorgzadeh, Soheil Ghiasi, Atsushi Takahashi, Majid Sarrafzadeh
2003 A* conf
Optimal integer delay budgeting on directed acyclic graphs.
DAC
Elaheh Bozorgzadeh, Soheil Ghiasi, Atsushi Takahashi, Majid Sarrafzadeh
2002 J jnl
A Clustering Based Fast Clock Schedule Algorithm for Light Clock-Trees.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Makoto Saitoh, Masaaki Azuma, Atsushi Takahashi
2002 J jnl
A High-Speed and Low-Power Clock Tree Synthesis by Dynamic Clock Scheduling.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Keiichi Kurokawa, Takuya Yasui, Yoichi Matsumura, Masahiko Toyonaga, Atsushi Takahashi
2002 J jnl
A Semi-Synchronous Circuit Design Method by Clock Tree Modification.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Seiichiro Ishijima, Tetsuaki Utsumi, Tomohiro Oto, Atsushi Takahashi
2002 J jnl
An Improvement of Network-Flow Based Multi-Way Circuit Partitioning Algorithm.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Kengo R. Azegami, Masato Inagi, Atsushi Takahashi, Yoji Kajitani
2002 — conf
Delay variation tolerant clock scheduling for semi-synchronous circuits.
APCCAS (1)
Hidetoshi Matsumura, Atsushi Takahashi
2001 A conf
Clustering based fast clock scheduling for light clock-tree.
DATE
Makoto Saitoh, Masaaki Azuma, Atsushi Takahashi
2000 — conf
A practical clock tree synthesis for semi-synchronous circuits.
ISPD
Masahiko Toyonaga, Keiichi Kurokawa, Takuya Yasui, Atsushi Takahashi
2000 Misc conf
Partition, Packing and Clock Distribution-A New Paradigm of Physical Design.
VLSI Design
Yoji Kajitani, Atsushi Takahashi, Kengo R. Azegami, Shigetoshi Nakatake
1999 — conf
Clock Period Minimization of Semi-Synchronous Circuits by Gate-Level Delay Insertion.
ASP-DAC
Tomoyuki Yoda, Atsushi Takahashi, Yoji Kajitani
1999 — conf
Enumerating the min-cuts for applications to graph extraction under size constraints.
ISCAS (6)
Kengo R. Azegami, Atsushi Takahashi, Y. Kajitan
1998 — conf
Air-Pressure-Model-Based Fast Algorithms for General Floorplan.
ASP-DAC
Tomonori Izumi, Atsushi Takahashi, Yoji Kajitani
1997 A conf
Clock-tree routing realizing a clock-schedule for semi-synchronous circuits.
ICCAD
Atsushi Takahashi, Kazunori Inoue, Yoji Kajitani
1997 — conf
Performance and reliability driven clock scheduling of sequential logic circuits.
ASP-DAC
Atsushi Takahashi, Yoji Kajitani
1996 — conf
Detailed-Routability of FPGAs with Extremal Switch-Block Structures.
ED&TC
Yasuhiro Takashima, Atsushi Takahashi, Yoji Kajitani
1995 J jnl
Mixed Searching and Proper-Path-Width.
Theor. Comput. Sci.
Atsushi Takahashi, Shuichi Ueno, Yoji Kajitani
1994 J jnl
Minimal acyclic forbidden minors for the family of graphs with bounded path-width.
Discret. Math.
Atsushi Takahashi, Shuichi Ueno, Yoji Kajitani
1992 J jnl
Peel-the-box: a concept of switch-box routing and tractable problems.
Integr.
Atsushi Takahashi, Yoji Kajitani
1991 — conf
Mixed-Searching and Proper-Path-Width.
ISA
Atsushi Takahashi, Shuichi Ueno, Yoji Kajitani