Atsushi Iwata - RankMe

88 papers B 9C 2Misc 4Journal 42Unranked 31

Year	Rank	Type	Title / Venue / Authors
2020	J	`jnl`	CMOS Gaussian Monocycle Pulse Transceiver for Radar-Based Microwave Imaging. IEEE Trans. Biomed. Circuits Syst. Takamaro Kikkawa, Yoshihiro Masui, Akihiro Toya, Hiroyuki Ito, Takuichi Hirano, Tomoaki Maeda, Masahiro Ono, Yoshitaka Murasaka, Toshifumi Imamura, Tsuyoshi Matsumaru, Michimasa Yamaguchi, Mitsutoshi Sugawara, Afreen Azhari, Hang Song, Shinsuke Sasada, Atsushi Iwata
2019	—	`conf`	Shifting Clock Jitter and Phase Interval for Impulse-Radar-Based Breast Cancer Detection. BioCAS Akihiro Toya, Takamaro Kikkawa, Yoshihiro Masui, Mitsutoshi Sugawara, Hiroyuki Ito, Tomoaki Maeda, Masahiro Ono, Yoshitaka Murasaka, Toshifumi Imamura, Atsushi Iwata
2018	—	`conf`	Gaussian Monocycle Pulse Generator with Calibration Circuit for Breast Cancer Detection. BioCAS Yoshihiro Masui, Akihiro Toya, Mitsutoshi Sugawara, Tomoaki Maeda, Masahiro Ono, Yoshitaka Murasaka, Atsushi Iwata, Takamaro Kikkawa
2017	—	`conf`	Differential equivalent time sampling receiver for breast cancer detection. BioCAS Yoshihiro Masui, Akihiro Toya, Mitsutoshi Sugawara, Tomoaki Maeda, Masahiro Ono, Yoshitaka Murasaka, Atsushi Iwata, Takamaro Kikkawa
2017	—	`conf`	Investigation of phase noise and jitter in CMOS sampling clock generation circuits for time-domain breast cancer detection system. BioCAS Akihiro Toya, Yoshihiro Masui, Mitsutoshi Sugawara, Tomoaki Maeda, Masahiro Ono, Yoshitaka Murasaka, Atsushi Iwata, Takamaro Kikkawa
2014	—	`conf`	An Operation Scenario Model for Energy Harvesting Embedded Systems and an Algorithm to Maximize the Operation Quality. HPCC/CSS/ICESS Kazumi Aono, Atsushi Iwata, Hideki Takase, Kazuyoshi Takagi, Naofumi Takagi
2011	J	`jnl`	A New Multi-Path Routing Methodology Based on Logit-Type Probability Assignment. IEICE Trans. Commun. Yudai Honma, Masaki Aida, Hideyuki Shimonishi, Atsushi Iwata
2011	J	`jnl`	Background Calibration Techniques for Low-Power and High-Speed Data Conversion. IEICE Trans. Electron. Atsushi Iwata, Yoshitaka Murasaka, Tomoaki Maeda, Takafumi Ohmoto
2011	J	`jnl`	Wide-Dynamic-Range APS-Based Silicon Retina With Brightness Constancy. IEEE Trans. Neural Networks Kazuhiro Shimonomura, Seiji Kameda, Atsushi Iwata, Tetsuya Yagi
2010	J	`jnl`	A Neural Recording Amplifier with Low-Frequency Noise Suppression. IEICE Trans. Electron. Takeshi Yoshida, Yoshihiro Masui, Ryoji Eki, Atsushi Iwata, Masayuki Yoshida, Kazumasa Uematsu
2009	J	`jnl`	A 1.0-V 10-b 30-MS/s 3.4-mW rail-to-rail pipelined ADC using a new front-end MDAC. IEICE Electron. Express Kunihiko Gotoh, Hiroshi Ando, Atsushi Iwata
2009	J	`jnl`	A 2.0 Vpp Input, 0.5 V Supply Delta Amplifier with A-to-D Conversion. IEICE Trans. Electron. Yoshihiro Masui, Takeshi Yoshida, Atsushi Iwata
2009	C	`conf`	A Neural Signal Detection Amplifier with Low-frequency Noise Suppression. ISCAS Takeshi Yoshida, Yoshihiro Masui, Ryoji Eki, Atsushi Iwata, Masayuki Yoshida, Kazumasa Uematsu
2009	—	`conf`	Building Hierarchical Switch Network Using OpenFlow. INCoS Hideyuki Shimonishi, Hideya Ochiai, Nobuyuki Enomoto, Atsushi Iwata
2008	—	`conf`	High-Speed, Short-Latency Multipath Ethernet Transport for Interconnections. Hot Interconnects Nobuyuki Enomoto, Hideyuki Shimonishi, Junichi Higuchi, Takashi Yoshikawa, Atsushi Iwata
2008	B	`conf`	High-Speed, Short-Latency Multipath Ethernet for Data Center Area Communications. GLOBECOM Nobuyuki Enomoto, Hideyuki Shimonishi, Junichi Higuchi, Takashi Yoshikawa, Atsushi Iwata
2008	J	`jnl`	Low power and low voltage chopper amplifier without LPF. IEICE Electron. Express Yoshihiro Masui, Takeshi Yoshida, Atsushi Iwata
2008	—	`conf`	Off-the-path flow handling mechanism forhigh-speed and programmable traffic management. PRESTO Hideyuki Shimonishi, Takashi Yoshikawa, Atsushi Iwata
2007	—	`conf`	12GHz Low-Area-Overhead Standing-Wave Clock Distribution with Inductively-Loaded and Coupled Technique. ISSCC Mamoru Sasaki, Mitsuru Shiozaki, Atsushi Mori, Atsushi Iwata, Hiroaki Ikeda
2007	J	`jnl`	Chip-Level Substrate Coupling Analysis with Reference Structures for Verification. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Daisuke Kosaka, Makoto Nagata, Yoshitaka Murasaka, Atsushi Iwata
2007	—	`conf`	Chip-Level Substrate Noise Analysis with Emphasis of Vertical Impurity Profile for Isolation. CICC Daisuke Kosaka, Makoto Nagata, Yoshitaka Murasaka, Atsushi Iwata
2007	J	`jnl`	Crankback Signaling Extensions for MPLS and GMPLS RSVP-TE. RFC Adrian Farrel, Arun Satyanarayana, Atsushi Iwata, Norihito Fujita, Gerald R. Ash
2007	J	`jnl`	Evaluation of Isolation Structures against High-Frequency Substrate Coupling in Analog/Mixed-Signal Integrated Circuits. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Daisuke Kosaka, Makoto Nagata, Yoshitaka Murasaka, Atsushi Iwata
2007	J	`jnl`	Low-Voltage and Low-Noise CMOS Analog Circuits Using Scaled Devices. IEICE Trans. Electron. Atsushi Iwata, Takeshi Yoshida, Mamoru Sasaki
2007	B	`conf`	Multilayer In-service Reconfiguration for Network Computing Systems. NCA Nobuharu Kami, Jun Suzuki, Yoichi Hidaka, Takashi Yoshikawa, Atsushi Iwata
2007	—	`conf`	NAT Traversal Technology of Reducing Load on Relaying Server for P2P Connections. CCNC Hideo Yoshimi, Nobuyuki Enomoto, Zhenlong Cui, Kazuo Takagi, Atsushi Iwata
2007	—	`conf`	On-Die Supply-Voltage Noise Sensor with Real-Time Sampling Mode for Low-Power Processor Applications. ISSCC Tomio Sato, Atsuki Inoue, Tetsuyoshi Shiota, Tomoko Inoue, Yukihito Kawabe, Tetsutaro Hashimoto, Toshifumi Imamura, Yoshitaka Murasaka, Makoto Nagata, Atsushi Iwata
2006	J	`jnl`	20GHz uniform-phase uniform-amplitude standing-wave clock distribution. IEICE Electron. Express Mitsuru Shiozaki, Mamoru Sasaki, Atsushi Mori, Atsushi Iwata, Hiroaki Ikeda
2006	J	`jnl`	A 1 V Low-Noise CMOS Amplifier Using Autozeroing and Chopper Stabilization Technique. IEICE Trans. Electron. Takeshi Yoshida, Yoshihiro Masui, Takayuki Mashimo, Mamoru Sasaki, Atsushi Iwata
2006	J	`jnl`	A VLSI Spiking Feedback Neural Network with Negative Thresholding and Its Application to Associative Memory. IEICE Trans. Electron. Kan'ya Sasaki, Takashi Morie, Atsushi Iwata
2006	J	`jnl`	A study of interference in synchronous systems. IEEE Trans. Circuits Syst. I Regul. Pap. Tsutomu Yoshimura, Atsushi Iwata
2006	J	`jnl`	An Image-Filtering LSI Processor Architecture for Face/Object Recognition Using a Sorted Projection-Field Model Based on a Merged/Mixed Analog-Digital Architecture. IEICE Trans. Electron. Osamu Nomura, Takashi Morie, Keisuke Korekado, Teppei Nakano, Masakazu Matsugu, Atsushi Iwata
2006	J	`jnl`	Carrier-Grade Ethernet Technologies for Next Generation Wide Area Ethernet. IEICE Trans. Commun. Atsushi Iwata
2006	—	`conf`	ExpressEther - Ethernet-Based Virtualization Technology for Reconfigurable Hardware Platform. Hot Interconnects Jun Suzuki, Yoichi Hidaka, Junichi Higuchi, Takashi Yoshikawa, Atsushi Iwata
2006	J	`jnl`	FPGA Implementation of Resistive-Fuse Networks for Coarse Image-Region Segmentation. Intell. Autom. Soft Comput. Teppei Nakano, Takashi Morie, Hideaki Ishizu, Hiroshi Ando, Atsushi Iwata
2006	J	`jnl`	Improving Ethernet Reliability and Stability Using Global Open Ethernet Technology. IEICE Trans. Commun. Masaki Umayabashi, Yoichi Hidaka, Nobuyuki Enomoto, Daisaku Ogasahara, Kazuo Takagi, Atsushi Iwata, Akira Arutaki
2006	—	`conf`	Proposal & demonstration of a new remote home-access system, softwire. CCNC Hideo Yoshimi, Nobuyuki Enomoto, Chinryu Sai, Kazuo Takagi, Atsushi Iwata
2006	—	`conf`	Stereo Matching Algorithm Using a Weighted Average of Costs Aggregated by Various Window Sizes. ACCV (2) Kan'ya Sasaki, Seiji Kameda, Atsushi Iwata
2005	—	`conf`	A 1V supply successive approximation ADC with rail-to-rail input voltage range. ISCAS (1) Takeshi Yoshida, Miho Akagi, Mamoru Sasaki, Atsushi Iwata
2005	J	`jnl`	A 2.7 Gcps and 7-Multiplexing CDMA Serial Communication Chip Using Two-Step Synchronization Technique. IEICE Trans. Electron. Mitsuru Shiozaki, Toru Mukai, Masahiro Ono, Mamoru Sasaki, Atsushi Iwata
2005	J	`jnl`	A 2.7 Gcps and 7-Multiplexing CDMA Serial Communication Chip for Real-Time Robot Control with Multiprocessors. J. Robotics Mechatronics Mitsuru Shiozaki, Toru Mukai, Masahiro Ono, Mamoru Sasaki, Atsushi Iwata
2005	J	`jnl`	A Cellular-Automaton-Type Region Extraction Algorithm and its FPGA Implementation. J. Robotics Mechatronics Teppei Nakano, Takashi Morie, Makoto Nagata, Atsushi Iwata
2005	—	`conf`	A Convolutional Neural Network VLSI Architecture Using Sorting Model for Reducing Multiply-and-Accumulation Operations. ICNC (3) Osamu Nomura, Takashi Morie, Masakazu Matsugu, Atsushi Iwata
2004	B	`conf`	A Convolutional Neural Network VLSI Architecture Using Thresholding and Weight Decomposition. KES Osamu Nomura, Takashi Morie, Keisuke Korekado, Masakazu Matsugu, Atsushi Iwata
2004	J	`jnl`	A VLSI convolutional neural network for image recognition using merged/mixed analog-digital architecture. J. Intell. Fuzzy Syst. Keisuke Korekado, Takashi Morie, Osamu Nomura, Hiroshi Ando, Teppei Nakano, Masakazu Matsugu, Atsushi Iwata
2004	J	`jnl`	An analysis of interference in synchronous systems. IEICE Electron. Express Tsutomu Yoshimura, Atsushi Iwata
2004	J	`jnl`	Coarse-grain replica management strategies for dynamic replication of Web contents. Comput. Networks Norihito Fujita, Yuichi Ishikawa, Atsushi Iwata, Rauf Izmailov
2004	B	`conf`	Design of multiple reverse spanning trees in next generation of Ethernet-VPNs. GLOBECOM Aleksandar Kolarov, Bhaskar Sengupta, Atsushi Iwata
2004	J	`jnl`	Gabor-Type Filtering using Transient States of Cellular Neural Networks. Intell. Autom. Soft Comput. Takashi Morie, Jun Umezawa, Atsushi Iwata
2004	J	`jnl`	Global open ethernet (GOE) system and its performance evaluation. IEEE J. Sel. Areas Commun. Atsushi Iwata, Yoichi Hidaka, Masaki Umayabashi, Nobuyuki Enomoto, Akira Arutaki
2003	B	`conf`	A Convolutional Neural Network VLSI for Image Recognition Using Merged/Mixed Analog-Digital Architecture. KES Keisuke Korekado, Takashi Morie, Osamu Nomura, Hiroshi Ando, Teppei Nakano, Masakazu Matsugu, Atsushi Iwata
2003	J	`jnl`	A High-Resolution CMOS Image Sensor with Hadamard Transform Function. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Kousuke Katayama, Atsushi Iwata
2003	—	`conf`	A substrate noise analysis methodology for large-scale mixed-signal ICs. CICC Wen Kung Chu, Nishath K. Verghese, Heayn-Jun Chol, Kenji Shimazaki, Hiroyuki Tsujikawa, Shouzou Hirano, Shirou Doushoh, Makoto Nagata, Atsushi Iwata, Takafumi Ohmoto
2002	—	`conf`	A cellular-automaton-type image extraction algorithm and its implementation using an FPGA. APCCAS (2) Teppei Nakano, Takashi Morie, Makoto Nagata, Atsushi Iwata
2002	B	`conf`	Coarse-grain dynamic replication schemes for scalable content delivery networks. GLOBECOM Norihito Fujita, Nobuyuki Enomoto, Atsushi Iwata, Rauf Izmailov
2002	J	`jnl`	Image Segmentation/Extraction Using Nonlinear Cellular Networks and Their VLSI Implementation Using Pulse-Modulation Techniques. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Hiroshi Ando, Takashi Morie, Makoto Miyake, Makoto Nagata, Atsushi Iwata
2002	—	`conf`	Modeling substrate noise generation in CMOS digital integrated circuits. CICC Makoto Nagata, Takashi Morie, Atsushi Iwata
2002	—	`conf`	Substrate Noise Analysis with Compact Digital Noise Injection and Substrate Models. ASP-DAC/VLSI Design Makoto Nagata, Yoshitaka Murasaka, Youichi Nishimori, Takashi Morie, Atsushi Iwata
2001	J	`jnl`	A PWM analog memory programming circuit for floating-gate MOSFETs with 75-μs programming time and 11-bit updating resolution. IEEE J. Solid State Circuits Shigeo Kinoshita, Takashi Morie, Makoto Nagata, Atsushi Iwata
2001	B	`conf`	Adaptive and efficient multiple path pre-computation for QoS routing protocols. GLOBECOM Norihito Fujita, Atsushi Iwata
2001	—	`conf`	An Efficient Clustering Algorithm Using Stochastic Association Model and Its Implementation Using Nanostructures. NIPS Takashi Morie, Tomohiro Matsuura, Makoto Nagata, Atsushi Iwata
2001	—	`conf`	Chip-Level Substrate Noise Analysis with Network Reduction by Fundamental Matrix Computation. ISQED Yoshitaka Murasaka, Makoto Nagata, Takafumi Ohmoto, Takashi Morie, Atsushi Iwata
2001	J	`jnl`	Physical design guides for substrate noise reduction in CMOS digital circuits. IEEE J. Solid State Circuits Makoto Nagata, Jin Nagai, Katsumasa Hijikata, Takashi Morie, Atsushi Iwata
2001	—	`conf`	Test circuits for substrate noise evaluation in CMOS digital ICs. ASP-DAC Makoto Nagata, Takafumi Ohmoto, Jin Nagai, Takashi Morie, Atsushi Iwata
2000	J	`jnl`	A hierarchical multilayer QoS routing system with dynamic SLA management. IEEE J. Sel. Areas Commun. Atsushi Iwata, Norihito Fujita
2000	—	`conf`	A smart imager for the vision processing front-END. ASP-DAC Noriaki Takeda, Mitsuru Homma, Makoto Nagata, Takashi Morie, Atsushi Iwata
2000	J	`jnl`	ATM Routing Algorithms for Multimedia Traffic in Private ATM Networks. J. Heuristics Rauf Izmailov, Atsushi Iwata, Bhaskar Sengupta
2000	—	`conf`	An arbitrary chaos generator core curcuit using PWM/PPM signals. ASP-DAC Kenichi Murakoshi, Takashi Morie, Makoto Nagata, Atsushi Iwata
2000	J	`jnl`	Measurements and analyses of substrate noise waveform inmixed-signal IC environment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Makoto Nagata, Jin Nagai, Takashi Morie, Atsushi Iwata
2000	C	`conf`	Pulse modulation circuit architecture and its application to functional image sensors. ISCAS Atsushi Iwata, Makoto Nagata, Noriaki Takeda, Mitsuru Homma, Takashi Morie
2000	—	`conf`	Quantitative characterization of substrate noise for physical design guides in digital circuits. CICC Makoto Nagata, Jin Nagai, Takashi Morie, Atsushi Iwata
2000	—	`conf`	Substrate crosstalk analysis in mixed signal CMOS integrated circuits: embedded tutorial. ASP-DAC Makoto Nagata, Atsushi Iwata
1999	—	`conf`	A Feature Associative Processor for Image Recognition Based on A-D merged Architecture. VLSI Atsushi Iwata, Makoto Nagata, Hiroyuki Nakamoto, Noriaki Takeda, Mitsuru Homma, Hiroto Higashi, Takashi Morie
1999	—	`conf`	Measurements and analyses of substrate noise waveform in mixed signal IC environment. CICC Makoto Nagata, Yoji Kashima, Daisuke Tamura, Takashi Morie, Atsushi Iwata
1999	J	`jnl`	Scalable routing strategies for ad hoc wireless networks. IEEE J. Sel. Areas Commun. Atsushi Iwata, Ching-Chuan Chiang, Guangyu Pei, Mario Gerla, Tsu-Wei Chen
1998	J	`jnl`	A PWM signal processing core circuit based on a switched current integration technique. IEEE J. Solid State Circuits Makoto Nagata, Jun Funakoshi, Atsushi Iwata
1998	B	`conf`	Nonlinear Function Generators and Chaotic Signal Generators Based on Pulse-Phase Modulation. ICONIP Souta Sakabayashi, Takashi Morie, Makoto Nagata, Atsushi Iwata
1998	B	`conf`	Oscillator Networks for Image Segmentation and Their Circuits Using Pulse Modulation Method. ICONIP Hiroshi Ando, Takashi Morie, Makoto Nagata, Atsushi Iwata
1998	—	`conf`	QOS aggregation algorithms in hierarchical ATM networks. ICC Atsushi Iwata, Hiroshi Suzuki, Rauf Izmailov, Bhaskar Sengupta
1995	J	`jnl`	ATM Connection and Traffic Management Schemes for Multimedia Internetworking. Commun. ACM Atsushi Iwata, N. Mori, Chinatsu Ikeda, Hiroshi Suzuki, Maximilian Ott
1989	J	`jnl`	A 17 bit oversampling D-A conversion technology using multistage noise shaping. IEEE J. Solid State Circuits Yasuyuki Matsuya, Kuniharu Uchimura, Atsushi Iwata, Takao Kaneko
1988	J	`jnl`	Oversampling A-to-D and D-to-A converters with multistage noise shaping modulators. IEEE Trans. Acoust. Speech Signal Process. Kuniharu Uchimura, Toshio Hayashi, Tadakatsu Kimura, Atsushi Iwata
1988	J	`jnl`	Performance limits of mixed analog/digital circuits with scaled MOSFETs. IEEE J. Solid State Circuits Eiichi Sano, Tsuneo Tsukahara, Atsushi Iwata
1986	Misc	`conf`	A 50ns floating-point signal processor VLSI. ICASSP Takao Kaneko, Hironori Yamauchi, Atsushi Iwata
1986	J	`jnl`	A ring array processor architecture for highly parallel dynamic time warping. IEEE Trans. Acoust. Speech Signal Process. Junichi Takahashi, Takashi Kimura, Sanshiro Hattori, Atsushi Iwata
1986	Misc	`conf`	VLSI- A to D and D to A converters with multi-stage noise shaping modulators. ICASSP Kuniharu Uchimura, Toshio Hayashi, Tadakatsu Kimura, Atsushi Iwata
1985	Misc	`conf`	An 18-bit floating-point signal processor VLSI with an on-chip 512W dual-port RAM. ICASSP Hironori Yamauchi, Takao Kaneko, Tsutomu Kobayashi, Atsushi Iwata, Sadayasu Ono
1982	Misc	`conf`	A high quality ADM LSI codec at 32 kbit/s for digital speech communications. ICASSP Naohisa Ohta, Kazunari Irie, Takehiko Uno, Atsushi Iwata, Tomonori Aoyama