Asit K. Mishra

49 papers A* 18A 6B 6Misc 2Journal 12Unranked 5

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	Recipes for Pre-training LLMs with MXFP8. CoRR Asit K. Mishra, Dusan Stosic, Simon Layton
2021	J	`jnl`	Accelerating Sparse Deep Neural Networks. CoRR Asit K. Mishra, Jorge Albericio Latorre, Jeff Pool, Darko Stosic, Dusan Stosic, Ganesh Venkatesh, Chong Yu, Paulius Micikevicius
2021	J	`jnl`	Exploiting Activation based Gradient Output Sparsity to Accelerate Backpropagation in CNNs. CoRR Anup Sarma, Sonali Singh, Huaipan Jiang, Ashutosh Pattnaik, Asit K. Mishra, Vijaykrishnan Narayanan, Mahmut T. Kandemir, Chita R. Das
2019	A*	`conf`	Opportunistic computing in GPU architectures. ISCA Ashutosh Pattnaik, Xulong Tang, Onur Kayiran, Adwait Jog, Asit K. Mishra, Mahmut T. Kandemir, Anand Sivasubramaniam, Chita R. Das
2018	A	`conf`	A Customizable Matrix Multiplication Framework for the Intel HARPv2 Xeon+FPGA Platform: A Deep Learning Case Study. FPGA Duncan J. M. Moss, Krishnan Srivatsan, Eriko Nurvitadhi, Piotr Ratuszniak, Chris Johnson, Jaewoong Sim, Asit K. Mishra, Debbie Marr, Suchit Subhaschandra, Philip Heng Wai Leong
2018	—	`conf`	Apprentice: Using Knowledge Distillation Techniques To Improve Low-Precision Network Accuracy. ICLR (Poster) Asit K. Mishra, Debbie Marr
2018	J	`jnl`	Exploration of Low Numeric Precision Deep Learning Inference Using Intel FPGAs. CoRR Philip Colangelo, Nasibeh Nasiri, Asit K. Mishra, Eriko Nurvitadhi, Martin Margala, Kevin Nealis
2018	Misc	`conf`	Exploration of Low Numeric Precision Deep Learning Inference Using Intel® FPGAs. FCCM Philip Colangelo, Nasibeh Nasiri, Eriko Nurvitadhi, Asit K. Mishra, Martin Margala, Kevin Nealis
2018	A	`conf`	Exploration of Low Numeric Precision Deep Learning Inference Using Intel® FPGAs: (Abstract Only). FPGA Philip Colangelo, Nasibeh Nasiri, Eriko Nurvitadhi, Asit K. Mishra, Martin Margala, Kevin Nealis
2018	A	`conf`	In-Package Domain-Specific ASICs for Intel® Stratix® 10 FPGAs: A Case Study of Accelerating Deep Learning Using TensorTile ASIC(Abstract Only). FPGA Eriko Nurvitadhi, Jeffrey J. Cook, Asit K. Mishra, Debbie Marr, Kevin Nealis, Philip Colangelo, Andrew C. Ling, Davor Capalija, Utku Aydonat, Sergey Y. Shumarayev, Aravind Dasu
2018	B	`conf`	In-Package Domain-Specific ASICs for Intel® Stratix® 10 FPGAs: A Case Study of Accelerating Deep Learning Using TensorTile ASIC. FPL Eriko Nurvitadhi, Jeffrey J. Cook, Asit K. Mishra, Debbie Marr, Kevin Nealis, Philip Colangelo, Andrew C. Ling, Davor Capalija, Utku Aydonat, Aravind Dasu, Sergey Y. Shumarayev
2018	J	`jnl`	WRPN & Apprentice: Methods for Training and Inference using Low-Precision Numerics. CoRR Asit K. Mishra, Debbie Marr
2018	—	`conf`	WRPN: Wide Reduced-Precision Networks. ICLR (Poster) Asit K. Mishra, Eriko Nurvitadhi, Jeffrey J. Cook, Debbie Marr
2017	J	`jnl`	Apprentice: Using Knowledge Distillation Techniques To Improve Low-Precision Network Accuracy. CoRR Asit K. Mishra, Debbie Marr
2017	—	`conf`	Fine-grained accelerators for sparse machine learning workloads. ASP-DAC Asit K. Mishra, Eriko Nurvitadhi, Ganesh Venkatesh, Jonathan Pearce, Debbie Marr
2017	B	`conf`	High performance binary neural networks on the Xeon+FPGA™ platform. FPL Duncan J. M. Moss, Eriko Nurvitadhi, Jaewoong Sim, Asit K. Mishra, Debbie Marr, Suchit Subhaschandra, Philip Heng Wai Leong
2017	J	`jnl`	Low Precision RNNs: Quantizing RNNs Without Losing Accuracy. CoRR Supriya Kapur, Asit K. Mishra, Debbie Marr
2017	J	`jnl`	WRPN: Training and Inference using Wide Reduced-Precision Networks. CoRR Asit K. Mishra, Jeffrey J. Cook, Eriko Nurvitadhi, Debbie Marr
2017	J	`jnl`	WRPN: Wide Reduced-Precision Networks. CoRR Asit K. Mishra, Eriko Nurvitadhi, Jeffrey J. Cook, Debbie Marr
2016	—	`conf`	Accelerating Binarized Neural Networks: Comparison of FPGA, CPU, GPU, and ASIC. FPT Eriko Nurvitadhi, David Sheffield, Jaewoong Sim, Asit K. Mishra, Ganesh Venkatesh, Debbie Marr
2016	B	`conf`	Accelerating recurrent neural networks in analytics servers: Comparison of FPGA, CPU, GPU, and ASIC. FPL Eriko Nurvitadhi, Jaewoong Sim, David Sheffield, Asit K. Mishra, Krishnan Srivatsan, Debbie Marr
2016	A	`conf`	Hardware accelerator for analytics of sparse data. DATE Eriko Nurvitadhi, Asit K. Mishra, Yu Wang, Ganesh Venkatesh, Debbie Marr
2016	A*	`conf`	ScalCore: Designing a core for voltage scalability. HPCA Bhargava Gopireddy, Choungki Song, Josep Torrellas, Nam Sung Kim, Aditya Agrawal, Asit K. Mishra
2016	B	`conf`	Scheduling Techniques for GPU Architectures with Processing-In-Memory Capabilities. PACT Ashutosh Pattnaik, Xulong Tang, Adwait Jog, Onur Kayiran, Asit K. Mishra, Mahmut T. Kandemir, Onur Mutlu, Chita R. Das
2015	Misc	`conf`	A sparse matrix vector multiply accelerator for support vector machine. CASES Eriko Nurvitadhi, Asit K. Mishra, Debbie Marr
2014	A*	`conf`	Tangle: Route-oriented dynamic voltage minimization for variation-afflicted, energy-efficient on-chip networks. HPCA Amin Ansari, Asit K. Mishra, Jianping Xu, Josep Torrellas
2013	A*	`conf`	A heterogeneous multiple network-on-chip design: an application-aware approach. DAC Asit K. Mishra, Onur Mutlu, Chita R. Das
2013	A*	`conf`	OWL: cooperative thread array aware scheduling techniques for improving GPGPU performance. ASPLOS Adwait Jog, Onur Kayiran, Nachiappan Chidambaram Nachiappan, Asit K. Mishra, Mahmut T. Kandemir, Onur Mutlu, Ravishankar R. Iyer, Chita R. Das
2013	A*	`conf`	Orchestrated scheduling and prefetching for GPGPUs. ISCA Adwait Jog, Onur Kayiran, Asit K. Mishra, Mahmut T. Kandemir, Onur Mutlu, Ravishankar R. Iyer, Chita R. Das
2013	A*	`conf`	Runnemede: An architecture for Ubiquitous High-Performance Computing. HPCA Nicholas P. Carter, Aditya Agrawal, Shekhar Borkar, Romain Cledat, Howard David, Dave Dunning, Joshua B. Fryman, Ivan Ganev, Roger A. Golliver, Rob C. Knauerhase, Richard Lethin, Benoît Meister, Asit K. Mishra, Wilfred R. Pinfold, Justin Teller, Josep Torrellas, Nicolas Vasilache, Ganesh Venkatesh, Jianping Xu
2012	B	`conf`	Application-aware prefetch prioritization in on-chip networks. PACT Nachiappan Chidambaram Nachiappan, Asit K. Mishra, Mahmut T. Kandemir, Anand Sivasubramaniam, Onur Mutlu, Chita R. Das
2012	A*	`conf`	Cache revive: architecting volatile STT-RAM caches for enhanced performance in CMPs. DAC Adwait Jog, Asit K. Mishra, Cong Xu, Yuan Xie, Vijaykrishnan Narayanan, Ravishankar R. Iyer, Chita R. Das
2012	B	`conf`	PEPON: performance-aware hierarchical power budgeting for NoC based multicores. PACT Akbar Sharifi, Asit K. Mishra, Shekhar Srikantaiah, Mahmut T. Kandemir, Chita R. Das
2011	A*	`conf`	A case for heterogeneous on-chip interconnects for CMPs. ISCA Asit K. Mishra, Narayanan Vijaykrishnan, Chita R. Das
2011	A*	`conf`	ACCESS: Smart scheduling for asymmetric cache CMPs. HPCA Xiaowei Jiang, Asit K. Mishra, Li Zhao, Ravishankar R. Iyer, Zhen Fang, Sadagopan Srinivasan, Srihari Makineni, Paul Brett, Chita R. Das
2011	A*	`conf`	An energy-efficient heterogeneous CMP based on hybrid TFET-CMOS cores. DAC Vinay Saripalli, Asit K. Mishra, Suman Datta, Vijaykrishnan Narayanan
2011	A*	`conf`	Architecting on-chip interconnects for stacked 3D STT-RAM caches in CMPs. ISCA Asit K. Mishra, Xiangyu Dong, Guangyu Sun, Yuan Xie, Narayanan Vijaykrishnan, Chita R. Das
2011	J	`jnl`	Exploiting Heterogeneity for Energy Efficiency in Chip Multiprocessors. IEEE J. Emerg. Sel. Topics Circuits Syst. Vinay Saripalli, Guangyu Sun, Asit K. Mishra, Yuan Xie, Suman Datta, Vijaykrishnan Narayanan
2011	A*	`conf`	METE: meeting end-to-end QoS in multicores through system-wide resource management. SIGMETRICS Akbar Sharifi, Shekhar Srikantaiah, Asit K. Mishra, Mahmut T. Kandemir, Chita R. Das
2011	J	`jnl`	RAFT: A router architecture with frequency tuning for on-chip networks. J. Parallel Distributed Comput. Asit K. Mishra, Aditya Yanamandra, Reetuparna Das, Soumya Eachempati, Ravi R. Iyer, Narayanan Vijaykrishnan, Chita R. Das
2010	A	`conf`	CPM in CMPs: Coordinated Power Management in Chip-Multiprocessors. SC Asit K. Mishra, Shekhar Srikantaiah, Mahmut T. Kandemir, Chita R. Das
2010	A*	`conf`	Coordinated power management of voltage islands in CMPs. SIGMETRICS Asit K. Mishra, Shekhar Srikantaiah, Mahmut T. Kandemir, Chita R. Das
2010	J	`jnl`	Towards characterizing cloud backend workloads: insights from Google compute clusters. SIGMETRICS Perform. Evaluation Rev. Asit K. Mishra, Joseph L. Hellerstein, Walfredo Cirne, Chita R. Das
2009	A*	`conf`	A case for dynamic frequency tuning in on-chip networks. MICRO Asit K. Mishra, Reetuparna Das, Soumya Eachempati, Ravishankar R. Iyer, Narayanan Vijaykrishnan, Chita R. Das
2009	A	`conf`	A case for integrated processor-cache partitioning in chip multiprocessors. SC Shekhar Srikantaiah, Reetuparna Das, Asit K. Mishra, Chita R. Das, Mahmut T. Kandemir
2009	A*	`conf`	Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs. HPCA Reetuparna Das, Soumya Eachempati, Asit K. Mishra, Narayanan Vijaykrishnan, Chita R. Das
2008	—	`conf`	Detection of Arcing in Low Voltage Distribution Systems. ICIIS Asit K. Mishra, Aurobinda Routray, Ashok Kumar Pradhan
2008	A*	`conf`	MIRA: A Multi-layered On-Chip Interconnect Router Architecture. ISCA Dongkook Park, Soumya Eachempati, Reetuparna Das, Asit K. Mishra, Yuan Xie, Narayanan Vijaykrishnan, Chita R. Das
2008	A*	`conf`	Performance and power optimization through data compression in Network-on-Chip architectures. HPCA Reetuparna Das, Asit K. Mishra, Chrysostomos Nicopoulos, Dongkook Park, Vijaykrishnan Narayanan, Ravishankar R. Iyer, Mazin S. Yousif, Chita R. Das