Ashwini K. Nanda

32 papers A* 6A 3C 1Journal 15Unranked 7
YearRankTypeTitle / Venue / Authors
2024 J jnl
Comparative Analysis of Machine Learning and Deep Learning Models for Classifying Squamous Epithelial Cells of the Cervix.
CoRR
Subhasish Das, Satish K. Panda, Madhusmita Sethy, Prajna Paramita Giri, Ashwini K. Nanda
2007 J jnl
Cell/B.E. blades: Building blocks for scalable, real-time, interactive, and digital media servers.
IBM J. Res. Dev.
Ashwini K. Nanda, J. Randal Moulic, Robert E. Hanson, Gottfried Goldrian, Michael N. Day, Bruce D. D'Amora, Sreeni Kesavarapu
2007 J jnl
Preface.
IBM J. Res. Dev.
H. Peter Hofstee, Ashwini K. Nanda, John J. Ritsko
2007 J jnl
Speech recognition systems on the Cell Broadband Engine processor.
IBM J. Res. Dev.
Yang Liu, Holger Jones, Sheila Vaidya, Michael Perrone, Borivoj Tydlitát, Ashwini K. Nanda
2006 J jnl
High-performance server systems and the next generation of online games.
IBM Syst. J.
Bruce D'Amora, Ashwini K. Nanda, Karen A. Magerlein, Atman Binstock, Bernard Yee
2003 J jnl
Guest Editors' Introduction: Evaluating Servers with Commercial Workloads.
Computer
Kimberly Keeton, Russell M. Clapp, Ashwini K. Nanda
2002 J jnl
Shared cache architectures for decision support systems.
Perform. Evaluation
Michel Dubois, Jaeheon Jeong, Ashwini K. Nanda
2001 J jnl
High-throughout coherence control and hardware messaging in Everest.
IBM J. Res. Dev.
Ashwini K. Nanda, Anthony-Trung Nguyen, Maged M. Michael, Douglas J. Joseph
2001 J jnl
Measurement, Analysis and Performance Improvement of the Apache Web Server.
Int. J. Comput. Their Appl.
Yiming Hu, Ashwini K. Nanda, Qing Yang
2000 A* conf
High-Throughput Coherence Controllers.
HPCA
Ashwini K. Nanda, Anthony-Trung Nguyen, Maged M. Michael, Douglas J. Joseph
2000 A* conf
MemorIES: A Programmable, Real-Time Hardware Emulation Tool for Multiprocessor Server Design.
ASPLOS
Ashwini K. Nanda, Kwok-Ken Mak, Krishnan Sugavanam, Ramendra K. Sahoo, Vijayaraghavan Soundararajan, T. Basil Smith
2000 A conf
Using Switch Directories to Speed Up Cache-to-Cache Transfers in CC-NUMA Multiprocessors.
IPDPS
Ravi R. Iyer, Laxmi N. Bhuyan, Ashwini K. Nanda
1999 J jnl
Coherence Controller Architectures for Scalable Shared-Memory Multiprocessors.
IEEE Trans. Computers
Maged M. Michael, Ashwini K. Nanda, Beng-Hong Lim
1999 A* conf
Design and Performance of Directory Caches for Scalable Shared Memory Multiprocessors.
HPCA
Maged M. Michael, Ashwini K. Nanda
1999 C conf
Measurement, analysis and performance improvement of the Apache Web server.
IPCCC
Yiming Hu, Ashwini K. Nanda, Qing Yang
1999 A* conf
Second Workshop on Computer Architecture Evaluation Using Commercial Workloads.
HPCA
Russell M. Clapp, Ashwini K. Nanda, Josep Torrellas
1998 J jnl
Energy optimization of multilevel cache architectures for RISC and CISC processors.
IEEE Trans. Very Large Scale Integr. Syst.
Uming Ko, Poras T. Balsara, Ashwini K. Nanda
1998 — conf
The Design of COMPASS: An Execution Driven Simulator for Commercial Applications Running on Shared Memory Multiprocessors.
IPPS/SPDP
Ashwini K. Nanda, Yiming Hu, Moriyoshi Ohara, Caroline Benveniste, Mark Giampapa, Maged M. Michael
1998 J jnl
The Misprediction Recovery Cache.
Int. J. Parallel Program.
Ashwini K. Nanda, James O. Bondi, Simonjit Dutta
1997 — conf
Accuracy and Speedup of Parallel Trace-Driven Architectural Simulation.
IPPS
Anthony-Trung Nguyen, Pradip Bose, Kattamuri Ekanadham, Ashwini K. Nanda, Maged M. Michael
1997 A* conf
Coherence Controller Architectures for SMP-Based CC-NUMA Multiprocessors.
ISCA
Maged M. Michael, Ashwini K. Nanda, Beng-Hong Lim, Michael L. Scott
1997 J jnl
Performance of Multistage Bus Networks for a Distributed Shared Memory Multiprocessor.
IEEE Trans. Parallel Distributed Syst.
Laxmi N. Bhuyan, Ravi R. Iyer, Tahsin Askar, Ashwini K. Nanda, Mohan Kumar
1996 A* conf
Integrating a Misprediction Recovery Cache (MRC) into a Superscalar Pipeline.
MICRO
James O. Bondi, Ashwini K. Nanda, Simonjit Dutta
1995 — conf
Energy optimization of multi-level processor cache architectures.
ISLPD
Uming Ko, Poras T. Balsara, Ashwini K. Nanda
1994 — conf
Performance and Reliability of the Multistage Bus Network.
ICPP (1)
Laxmi N. Bhuyan, Ashwini K. Nanda, Tahsin Askar
1993 J jnl
Design and Analysis of Cache Coherent Multistage Interconnection Networks.
IEEE Trans. Computers
Ashwini K. Nanda, Laxmi N. Bhuyan
1993 J jnl
Efficient Mapping of Applications on Cache Based Multiprocessors.
J. Parallel Distributed Comput.
Ashwini K. Nanda, Laxmi N. Bhuyan
1992 — conf
A Formal Specification and Verification Technique for Cache Coherence Protocols.
ICPP (1)
Ashwini K. Nanda, Laxmi N. Bhuyan
1992 — conf
Analysis of Directory Based Cache Coherence Schemes with Multistage Networks.
ACM Conference on Computer Science
Ashwini K. Nanda, Hong Jiang
1992 A conf
Mapping Applications onto a Cache Coherent Multiprocessor.
SC
Ashwini K. Nanda, Laxmi N. Bhuyan
1992 A conf
Scheduling Directed Task Graphs on Multiprocessors Using Simulated Annealing.
ICDCS
Ashwini K. Nanda, Doug DeGroot, Daniel L. Stenger
1991 — conf
Multistage bus network (MBN): an interconnection network for cache coherent multiprocessors.
SPDP
Laxmi N. Bhuyan, Ashwini K. Nanda