Ashwin Ramachandran

14 papers A* 2A 1Journal 8Unranked 3
YearRankTypeTitle / Venue / Authors
2025 A* conf
Charting the Design Space of Neural Graph Representations for Subgraph Matching.
ICLR
Vaibhav Raj, Indradyumna Roy, Ashwin Ramachandran, Soumen Chakrabarti, Abir De
2025 J jnl
Charting the Design Space of Neural Graph Representations for Subgraph Matching.
CoRR
Vaibhav Raj, Indradyumna Roy, Ashwin Ramachandran, Soumen Chakrabarti, Abir De
2025 J jnl
Iteratively Refined Early Interaction Alignment for Subgraph Matching based Graph Retrieval.
CoRR
Ashwin Ramachandran, Vaibhav Raj, Indrayumna Roy, Soumen Chakrabarti, Abir De
2025 J jnl
ReFoRCE: A Text-to-SQL Agent with Self-Refinement, Format Restriction, and Column Exploration.
CoRR
Minghang Deng, Ashwin Ramachandran, Canwen Xu, Lanxiang Hu, Zhewei Yao, Anupam Datta, Hao Zhang
2024 A* conf
Iteratively Refined Early Interaction Alignment for Subgraph Matching based Graph Retrieval.
NeurIPS
Ashwin Ramachandran, Vaibhav Raj, Indradyumna Roy, Soumen Chakrabarti, Abir De
2024 J jnl
Text-to-SQL Calibration: No Need to Ask - Just Rescale Model Probabilities.
CoRR
Ashwin Ramachandran, Sunita Sarawagi
2022 J jnl
A PAM-8 Wireline Transceiver With Linearity Improvement Technique and a Time-Domain Receiver Side FFE in 65 nm CMOS.
IEEE J. Solid State Circuits
Yusang Chun, Mohamed Megahed, Ashwin Ramachandran, Tejasvi Anand
2020 J jnl
An iPWM Line-Coding-Based Wireline Transceiver With Clock -Domain Encoding for Compensating Up To 27-dB Loss While Operating at 0.5-to-0.9 V and 3-to-16 Gb/s in 65-nm CMOS.
IEEE J. Solid State Circuits
Ashwin Ramachandran, Yusang Chun, Mohamed Megahed, Tejasvi Anand
2019 — conf
A PAM-8 Wireline Transceiver with Receiver Side PWM (Time-Domain) Feed Forward Equalization Operating from 12-to-39.6Gb/s in 65nm CMOS.
ESSCIRC
Yusang Chun, Ashwin Ramachandran, Tejasvi Anand
2019 J jnl
A Switched Capacitor Multiple Input Single Output Energy Harvester (Solar + Piezo) Achieving 74.6% Efficiency With Simultaneous MPPT.
IEEE Trans. Circuits Syst. I Regul. Pap.
Abhishekh Devaraj, Mohamed Megahed, Yutao Liu, Ashwin Ramachandran, Tejasvi Anand
2019 J jnl
Line Coding Techniques for Channel Equalization: Integrated Pulse-Width Modulation and Consecutive Digit Chopping.
IEEE Trans. Circuits Syst. I Regul. Pap.
Ashwin Ramachandran, Arun Natarajan, Tejasvi Anand
2018 — conf
A 0.5-to-0.9V, 3-to-16Gb/s, 1.6-to-3.1pJ/b wireline transceiver equalizing 27dB loss at 10Gb/s with clock-domain encoding using integrated pulse-width modulation (iPWM) in 65nm CMOS.
ISSCC
Ashwin Ramachandran, Tejasvi Anand
2017 — conf
29.4 A 16Gb/s 3.6pJ/b wireline transceiver with phase domain equalization scheme: Integrated pulse width modulation (iPWM) in 65nm CMOS.
ISSCC
Ashwin Ramachandran, Arun Natarajan, Tejasvi Anand
2005 A conf
Providing intelligent help across applications in dynamic user and environment contexts.
IUI
Ashwin Ramachandran, R. Michael Young