Ashutosh Chakraborty

24 papers A* 2A 7C 1Journal 6Unranked 8

Year	Rank	Type	Title / Venue / Authors
2013	J	`jnl`	Cell transformations and physical design techniques for 3D monolithic integrated circuits. ACM J. Emerg. Technol. Comput. Syst. Shashikanth Bobba, Ashutosh Chakraborty, Olivier Thomas, Perrine Batude, Giovanni De Micheli
2013	J	`jnl`	Skew Management of NBTI Impacted Gated Clock Trees. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ashutosh Chakraborty, David Z. Pan
2012	A	`conf`	Reclaiming over-the-IP-block routing resources with buffering-aware rectilinear Steiner minimum tree construction. ICCAD Yilin Zhang, Ashutosh Chakraborty, Salim Chowdhury, David Z. Pan
2011	—	`conf`	CELONCEL: Effective design technique for 3-D monolithic integration targeting high performance integrated circuits. ASP-DAC Shashikanth Bobba, Ashutosh Chakraborty, Olivier Thomas, Perrine Batude, Thomas Ernst, Olivier Faynot, David Z. Pan, Giovanni De Micheli
2011	—	`conf`	Controlling NBTI degradation during static burn-in testing. ASP-DAC Ashutosh Chakraborty, David Z. Pan
2010	A	`conf`	PASAP: power aware structured ASIC placement. ISLPED Ashutosh Chakraborty, David Z. Pan
2010	—	`conf`	Performance analysis of 3-D monolithic integrated circuits. 3DIC Shashikanth Bobba, Ashutosh Chakraborty, Olivier Thomas, Perrine Batude, Vasilis F. Pavlidis, Giovanni De Micheli
2010	—	`conf`	Skew management of NBTI impacted gated clock trees. ISPD Ashutosh Chakraborty, David Z. Pan
2010	J	`jnl`	Stress Aware Layout Optimization Leveraging Active Area Dependent Mobility Enhancement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ashutosh Chakraborty, Sean X. Shi, David Z. Pan
2010	A	`conf`	Stress-driven 3D-IC placement with TSV keep-out zone and regularity study. ICCAD Krit Athikulwongse, Ashutosh Chakraborty, Jae-Seok Yang, David Z. Pan, Sung Kyu Lim
2010	J	`jnl`	Thermal-Aware Clock Tree Design to Increase Timing Reliability of Embedded SoCs. IEEE Trans. Circuits Syst. I Regul. Pap. Ashutosh Chakraborty, Karthik Duraisami, Prassanna Sithambaram, Alberto Macii, Enrico Macii, Massimo Poncino
2009	A	`conf`	Analysis and optimization of NBTI induced clock skew in gated clock trees. DATE Ashutosh Chakraborty, Gokul Ganesan, Anand Rajaram, David Z. Pan
2009	—	`conf`	On stress aware active area sizing, gate sizing, and repeater insertion. ISPD Ashutosh Chakraborty, David Z. Pan
2009	A*	`conf`	RegPlace: a high quality open-source placement framework for structured ASICs. DAC Ashutosh Chakraborty, Anurag Kumar, David Z. Pan
2008	A*	`conf`	An integrated nonlinear placement framework with congestion and porosity aware buffer planning. DAC Tung-Chieh Chen, Ashutosh Chakraborty, David Z. Pan
2008	J	`jnl`	Dynamic Thermal Clock Skew Compensation Using Tunable Delay Buffers. IEEE Trans. Very Large Scale Integr. Syst. Ashutosh Chakraborty, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino
2008	J	`jnl`	Implementation of a thermal management unit for canceling temperature-dependent clock skew variations. Integr. Ashutosh Chakraborty, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Alberto Macii, Enrico Macii, Massimo Poncino
2008	A	`conf`	Layout Level Timing Optimization by Leveraging Active Area Dependent Mobility of Strained-Silicon Devices. DATE Ashutosh Chakraborty, Sean X. Shi, David Z. Pan
2006	—	`conf`	Dynamic Management of Thermally-Induced Clock Skew: An Implementation Perspective. PATMOS Ashutosh Chakraborty, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Alberto Macii, Enrico Macii, Massimo Poncino
2006	A	`conf`	Dynamic thermal clock skew compensation using tunable delay buffers. ISLPED Ashutosh Chakraborty, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino
2006	C	`conf`	Implications of ultra low-voltage devices on design techniques for controlling leakage in NanoCMOS circuits. ISCAS Ashutosh Chakraborty, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Alberto Macii, Enrico Macii, Massimo Poncino
2006	A	`conf`	Thermal resilient bounded-skew clock tree optimization methodology. DATE Ashutosh Chakraborty, Prassanna Sithambaram, Karthik Duraisami, Alberto Macii, Enrico Macii, Massimo Poncino
2005	—	`conf`	Exploiting Cross-Channel Correlation for Energy-Efficient LCD Bus Encoding. PATMOS Ashutosh Chakraborty, Enrico Macii, Massimo Poncino
2003	—	`conf`	Low-Voltage, Double-Edge-Triggered Flip Flop. PATMOS Pradeep Varma, Ashutosh Chakraborty