Ashok K. Saxena

15 papers Journal 12Unranked 3
YearRankTypeTitle / Venue / Authors
2016 J jnl
Oxide thickness and S/D junction depth based variation aware OTA design using underlap FinFET.
Microelectron. J.
Ashutosh Nandi, Ashok K. Saxena, Sudeb Dasgupta
2012 — conf
Analog Performance Analysis of Dual-k Spacer Based Underlap FinFET.
VDAT
Ashutosh Nandi, Ashok K. Saxena, Sudeb Dasgupta
2012 J jnl
Analysis of double-gate FinFET-based address decoder for radiation-induced single-event-transients.
IET Circuits Devices Syst.
Surendra S. Rathod, Ashok K. Saxena, Sudeb Dasgupta
2012 J jnl
Dg-FinFET-Based SRAM Configurations for Increased SEU Immunity.
J. Circuits Syst. Comput.
Surendra S. Rathod, Ashok K. Saxena, Sudeb Dasgupta
2012 J jnl
Impact of dual-k spacer on analog performance of underlap FinFET.
Microelectron. J.
Ashutosh Nandi, Ashok K. Saxena, Sudeb Dasgupta
2011 J jnl
A low-noise, process-variation-tolerant double-gate FinFET based sense amplifier.
Microelectron. Reliab.
Surendra S. Rathod, Ashok K. Saxena, Sudeb Dasgupta
2011 J jnl
Alpha-particle-induced effects in partially depleted silicon on insulator device: With and without body contact.
IET Circuits Devices Syst.
Surendra S. Rathod, Ashok K. Saxena, Sudeb Dasgupta
2011 J jnl
Electrical performance study of 25 nm Omega-FinFET under the influence of gamma radiation: A 3D simulation.
Microelectron. J.
Surendra S. Rathod, Ashok K. Saxena, Sudeb Dasgupta
2011 J jnl
Modeling and estimation of edge direct tunneling current for nanoscale metal gate (Hf/AlN
Microelectron. J.
Santosh Kumar Vishvakarma, V. Komal Kumar, Ashok K. Saxena, Sudeb Dasgupta
2011 J jnl
Process Variation Tolerant FinFET Based Robust Low Power SRAM Cell Design at 32 nm Technology.
J. Low Power Electron.
Balwinder Raj, Jatin Mitra, Deepak Kumar Bihani, V. Rangharajan, Ashok K. Saxena, Sudeb Dasgupta
2011 — conf
Quantum Mechanical Analytical Drain Current Modeling and Simulation for Double Gate FinFET Device Using Quasi Fermi Potential Approach.
SocProS (2)
Balwinder Raj, Ashok K. Saxena, Sudeb Dasgupta
2010 J jnl
A proposed DG-FinFET based SRAM cell design with RadHard capabilities.
Microelectron. Reliab.
Surendra S. Rathod, Ashok K. Saxena, Sudeb Dasgupta
2010 — conf
Quantum Inversion Charge and Drain Current Analysis for Double Gate FinFET Device: Analytical Modeling and TCAD Simulation Approach.
EMS
Balwinder Raj, Ashok K. Saxena, Sudeb Dasgupta
2010 J jnl
Robust Double Gate FinFET Based Sense Amplifier Design Using Independent Gate Control.
J. Low Power Electron.
Surendra S. Rathod, Ashok K. Saxena, Sudeb Dasgupta
2009 J jnl
Design of Low Power Adiabatic SRAM Using DTGAL, CPAL and ACPL: A Comparative Study.
J. Low Power Electron.
Y. K. Sudharshan, D. Sreenu, Ashok K. Saxena, Sudeb Dasgupta