Ashok K. Murugavel

12 papers A* 1A 1C 1Misc 5Journal 3Unranked 1
YearRankTypeTitle / Venue / Authors
2004 Misc conf
Game Theoretic Modeling of Voltage and Frequency Scaling during Behavioral Synthesis.
VLSI Design
Ashok K. Murugavel, N. Ranganathan
2004 Misc conf
Gate Sizing and Buffer Insertion using Economic Models for Power Optimization.
VLSI Design
Ashok K. Murugavel, N. Ranganathan
2003 Misc conf
A Game-Theoretic Approach for Binding in Behavioral Synthesis.
VLSI Design
Ashok K. Murugavel, N. Ranganathan
2003 C conf
A Microeconomic Model for Simultaneous Gate Sizing and Voltage Scaling for Power Optimization.
ICCD
N. Ranganathan, Ashok K. Murugavel
2003 J jnl
A game theoretic approach for power optimization during behavioral synthesis.
IEEE Trans. Very Large Scale Integr. Syst.
Ashok K. Murugavel, N. Ranganathan
2003 Misc conf
A low power scheduler using game theory.
CODES+ISSS
N. Ranganathan, Ashok K. Murugavel
2003 J jnl
Petri net modeling of gate and interconnect delays for power estimation.
IEEE Trans. Very Large Scale Integr. Syst.
Ashok K. Murugavel, N. Ranganathan
2002 — conf
A Real Delay Switching Activity Simulator Based on Petri Net Modeling.
ASP-DAC/VLSI Design
Ashok K. Murugavel, N. Ranganathan
2002 J jnl
Least-square estimation of average power in digital CMOS circuits.
IEEE Trans. Very Large Scale Integr. Syst.
Ashok K. Murugavel, N. Ranganathan, Ramamurti Chandramouli, Srinath Chavali
2002 A* conf
Petri net modeling of gate and interconnect delays for power estimation.
DAC
Ashok K. Murugavel, N. Ranganathan
2002 A conf
Power estimation of sequential circuits using hierarchical colored hardware petri net modeling.
ISLPED
Ashok K. Murugavel, N. Ranganathan
2001 Misc conf
Average Power in Digital CMOS Circuits using Least Square Estimation.
VLSI Design
Ashok K. Murugavel, N. Ranganathan, Ramamurti Chandramouli, Srinath Chavali