Ashish Sachdeva

15 papers Journal 14Unranked 1
YearRankTypeTitle / Venue / Authors
2025 J jnl
A FinFET-Based Low Leakage 10T Static Random Access Memory Cell.
J. Circuits Syst. Comput.
Anandita Srivastav, Usha Tiwari, Sushanta K. Mandal, Ashish Sachdeva
2025 J jnl
One-Sided Schmitt-Trigger-Based Low Power Read Decoupled 11T CNTFET SRAM with Improved Stability.
Circuits Syst. Signal Process.
M. Elangovan, Kulbhushan Sharma, Ashish Sachdeva, Abdolreza Darabi
2025 J jnl
Plundervolt attack: A novel simulation-based fault injection attack against embedded systems for accelerating dependability analysis process.
J. Supercomput.
Shaminder Kaur, Ashish Sachdeva, J. Chinna Babu
2025 J jnl
Schmitt Trigger-Based Low Leakage and Half-Select Free Near-Threshold 10T SRAM Architecture.
J. Circuits Syst. Comput.
Appikatla Phani Kumar, Rohit Lorenzo, Erfan Abbasian, Ashish Sachdeva
2024 J jnl
A Novel Simulation Approach for Fault Injection Mechanism Assessing Dependability of Cybersecurity Attacks.
J. Circuits Syst. Comput.
Shaminder Kaur, Ashish Sachdeva
2024 J jnl
Read Improved and Low Leakage Power CNTFET Based Hybrid 10t SRAM Cell for Low Power Applications.
Circuits Syst. Signal Process.
M. Elangovan, Kulbhushan Sharma, Ashish Sachdeva, Lipika Gupta
2023 J jnl
Low Power Static Random-Access Memory Cell Design for Mobile Opportunistic Networks Sensor Nodes.
J. Circuits Syst. Comput.
Ashish Sachdeva
2022 J jnl
Characterization of Stable 12T SRAM with Improved Critical Charge.
J. Circuits Syst. Comput.
Ashish Sachdeva, V. K. Tomar
2022 J jnl
Design of a soft error hardened SRAM cell with improved access time for embedded systems.
Microprocess. Microsystems
V. K. Tomar, Ashish Sachdeva
2021 J jnl
A Multi-bit Error Upset Immune 12T SRAM Cell for 5G Satellite Communications.
Wirel. Pers. Commun.
Ashish Sachdeva, V. K. Tomar
2021 J jnl
Design of 10T SRAM cell with improved read performance and expanded write margin.
IET Circuits Devices Syst.
Ashish Sachdeva, V. K. Tomar
2021 J jnl
Design of Low Power Half Select Free 10T Static Random-Access Memory Cell.
J. Circuits Syst. Comput.
Ashish Sachdeva, V. K. Tomar
2020 J jnl
Design of a Stable Low Power 11-T Static Random Access Memory Cell.
J. Circuits Syst. Comput.
Ashish Sachdeva, V. K. Tomar
2018 J jnl
The path to equilibrium in sequential and simultaneous games: A mousetracking study.
J. Econ. Theory
Isabelle Brocas, Juan D. Carrillo, Ashish Sachdeva
2012 — conf
Analog Textual Entailment and Spectral Clustering (ATESC) Based Summarization.
BDA
Anand Gupta, Manpreet Kathuria, Arjun Singh, Ashish Sachdeva, Shruti Bhati