Ashis Kumar Mal

31 papers Misc 4Journal 17Unranked 10
YearRankTypeTitle / Venue / Authors
2024 J jnl
A Survey on Hardware Accelerator Design of Deep Learning for Edge Devices.
Wirel. Pers. Commun.
Anu Samanta, Indranil Hatai, Ashis Kumar Mal
2023 J jnl
Performance of Novel Adaptive Schemes for Cognitive Full-Duplex Relaying-Based Downlink Cooperative NOMA.
IEEE Trans. Wirel. Commun.
Amrita Mukherjee, Pratik Chakraborty, Shankar Prakriya, Ashis Kumar Mal
2022 J jnl
Cooperative Mode Switching-Based Cognitive NOMA With Transmit Antenna and User Selection.
IEEE Trans. Signal Inf. Process. over Networks
Amrita Mukherjee, Pratik Chakraborty, Shankar Prakriya, Ashis Kumar Mal
2022 J jnl
Fuzzy Logic-Based Energy-Optimal Collinear DF Relay Placement in Two-Hop η -μ Fading Channel.
Int. J. Wirel. Inf. Networks
Biswajit Ghosh, Aniruddha Chandra, Ashis Kumar Mal
2021 J jnl
A cost-effective alertness-rating tool to enable situational awareness among on-duty static security guards in Covid-19 pandemic.
J. Reliab. Intell. Environ.
Debabrata Bej, Shubhranil Chakraborty, Sekh Arif Mahammad, Ashis Kumar Mal
2021 — conf
Performance of an Adaptive Cooperative NOMA Scheme with Transmit Antenna Selection.
ANTS
Amrita Mukherjee, Pratik Chakraborty, Shankar Prakriya, Ashis Kumar Mal
2020 — conf
An Efficient NoC-based ANN Framework for Epileptic Seizure Recognition.
iSES
Ayut Ghosh, Arka Prava Roy, Ramapati Patra, Ashis Kumar Mal, Hemanta Kumar Mondal
2020 J jnl
Optimal Design of Ultra-Low-Power 2.4 GHz LNA for IEEE 802.15.4/Bluetooth Applications.
J. Circuits Syst. Comput.
Sumalya Ghosh, Bishnu Prasad De, Kanchan Baran Maji, Rajib Kar, Durbadal Mandal, Ashis Kumar Mal
2020 J jnl
Time-Domain Smart Temperature Sensor Using Current Starved Inverters and Switched Ring Oscillator-Based Time-to-Digital Converter.
Circuits Syst. Signal Process.
R. S. S. M. R. Krishna, Ashis Kumar Mal, Rajat Mahapatra
2019 J jnl
A cost-effective system for triggering alarm to distracted drivers/ nurses.
Comput. Electr. Eng.
Debabrata Bej, Subhajit Rakshit, Ashis Kumar Mal, Rajat Mahapatra
2019 J jnl
All MOS noise-shaped time-mode temperature sensor.
Integr.
R. S. S. M. R. Krishna, Ashis Kumar Mal, Rajat Mahapatra
2019 J jnl
Fast and optimised design of a differential VCO using symbolic technique and multi objective algorithms.
IET Circuits Devices Syst.
Madhusmita Panda, Santosh Kumar Patnaik, Ashis Kumar Mal, Sumalya Ghosh
2019 J jnl
Optimal design of complementary metal-oxide-semiconductor analogue circuits: An evolutionary approach.
Comput. Electr. Eng.
Sumalya Ghosh, Bishnu Prasad De, Rajib Kar, Durbadal Mandal, Ashis Kumar Mal
2019 J jnl
Symbiotic organisms search algorithm for optimal design of CMOS two-stage op-amp with nulling resistor and robust bias circuit.
IET Circuits Devices Syst.
Sumalya Ghosh, Bishnu Prasad De, Rajib Kar, Ashis Kumar Mal
2018 J jnl
Performance enhancement of a VCO using symbolic modelling and optimisation.
IET Circuits Devices Syst.
Madhusmita Panda, Santosh Kumar Patnaik, Ashis Kumar Mal
2017 J jnl
Optimal Location of Energy Efficient DF Relay Node in κ - μ Fading Channel.
Wirel. Pers. Commun.
Biswajit Ghosh, Aniruddha Chandra, Ashis Kumar Mal
2015 Misc conf
An integrated routing and offset-time adaptation scheme for OBS network.
ICDCN
Subhrabrata Choudhury, Vivek Nair, Jaydeep Howlader, B. Choudhury, Ashis Kumar Mal
2015 — conf
Analysis of resistive load ring oscillator.
ReTIS
Saurav Mandal, Ashis Kumar Mal
2015 J jnl
Sealed-bid auction: a cryptographic solution to bid-rigging attack in the collusive environment.
Secur. Commun. Networks
Jaydeep Howlader, Ashis Kumar Mal
2014 J jnl
Practical Receipt-Free Sealed-Bid Auction in the Coercive Environment.
IACR Cryptol. ePrint Arch.
Jaydeep Howlader, Sanjit Kumar Roy, Ashis Kumar Mal
2013 — conf
A power efficient and digitally assisted CMOS complementary telescopic amplifier with wide input common mode range.
ISQED
Rishi Todani, Ashis Kumar Mal
2013 Misc conf
Practical Receipt-Free Sealed-Bid Auction in the Coercive Environment.
ICISC
Jaydeep Howlader, Sanjit Kumar Roy, Ashis Kumar Mal
2012 Misc conf
Coercion Resistant MIX for Electronic Auction.
ICISS
Jaydeep Howlader, Jayanta Kar, Ashis Kumar Mal
2012 J jnl
Routing Scheme for OBS Networks.
JOCN
Subhrabrata Choudhury, Vivek Nair, Ashis Kumar Mal
2010 — conf
Design of DXT architecture using current switched integrator.
APCCAS
Ashis Kumar Mal, Om Prakash Hari, Rishi Todani, Anindya Sundar Dhar
2008 — conf
Delay Estimation for On-Chip VLSI Interconnect using Weibull Distribution Function.
ICIIS
Rajib Kar, Anuran Chattaraj, Aniruddha Chandra, Ashis Kumar Mal, A. K. Bhattacharjee
2004 — conf
A generalized analog architecture for DCT, DST and its inverse.
ICASSP (5)
Ashis Kumar Mal, Arindam Basu
2004 Misc conf
Analog VLSI Architecture for Discrete Cosine Transform using Dynamic Switched Capacitors.
VLSI Design
Ashis Kumar Mal, Anindya Sundar Dhar
2004 — conf
Digital controlled analog architecture for DCT and DST using capacitor switching.
ISCAS (2)
Arindam Basu, Ashis Kumar Mal, Anindya Sundar Dhar
2004 — conf
Sampled analog architecture for DCT and DST.
ISCAS (2)
Ashis Kumar Mal, Arindam Basu, Anindya Sundar Dhar
2003 — conf
Analog sampled data architecture for discrete Hartley transform for prime N.
ICECS
Ashis Kumar Mal, Anindya Sundar Dhar