Artur Jutman - RankMe

61 papers A 9B 7C 8Misc 2Journal 10Unranked 24

Year	Rank	Type	Title / Venue / Authors
2025	B	`conf`	European Test Symposium Teams: an Anniversary Snapshot. ETS Maksim Jenihhin, Jaan Raik, Artur Jutman, Natalia Cherezova, Raimund Ubar, Liviu Miclea, Szilárd Enyedi, I. Stefan, Ovidiu Stan, Cosmina Corches, Z. Peng, Petru Eles, Rolf Drechsler, S. Eggersglüß, Görschwin Fey, Andreas Glowatz, Daniel Tille, Georges G. E. Gielen, Anthony Coyette, Wim Dobbelaere, Ronny Vanhooren, P.-Y. Chuang, Erik Jan Marinissen, Giorgio Di Natale, M. Barragan, Paolo Maistri, S. Mir, Vatajelu I. Vatajelu, Paolo Bernardi, S. Di Carlo, Paolo Prinetto, Matteo Sonza Reorda, Massimo Violante, Haralampos-G. Stratigopoulos, M. K. Michael, Stelios Neophytou, Stavros Hadjitheophanous, Kyriakos Christou, M. Skitsas, Alberto Bosio, Bastien Deveautour, P. Girard, Marcello Traiola, Arnaud Virazel, F. Fernandes Dos Santos, Angeliki Kritikakou, Gioele Casagranda, Marzio Vallero, Flavio Vella, Paolo Rech, Letícia Maria Bolzani Poehls, Milos Krstic, Marko S. Andjelkovic, F. Vargas, Grigor Tshagharyan, Gurgen Harutyunyan, Valery A. Vardanian, Samvel K. Shoukourian, Yervant Zorian, Jennifer Dworak, Kundan Nepal, Theodore W. Manikas, Mottaqiallah Taouil, Moritz Fieback, Anteneh Gebregiorgis, Rajendra Bishnoi, Said Hamdioui, Abhijit Chatterjee, A. Saha, Suhasini Komarraju, K. Ma, Chandramouli N. Amarnath, Mehdi Baradaran Tahoori, Mahta Mayahinia, Maryam Rajabalipanah, Katayoon Basharkhah, N. Nosrati, Zahra Jahanpeima, Zain Navabi, Hans-Joachim Wunderlich, Sybille Hellebrand
2025	J	`jnl`	FORTALESA: Fault-Tolerant Reconfigurable Systolic Array for DNN Inference. CoRR Natalia Cherezova, Artur Jutman, Maksim Jenihhin
2024	—	`conf`	IJTAG-compatible Symptom-based SEU Monitors for FPGA DNN Accelerators. DTTIS Natalia Cherezova, Maksim Jenihhin, Artur Jutman
2024	—	`conf`	Keynote: Cost-Efficient Reliability for Edge-AI Chips. LATS Maksim Jenihhin, Mahdi Taheri, Natalia Cherezova, Mohammad Hasan Ahmadilivani, Hardi Selg, Artur Jutman, Konstantin Shibin, Anton Tsertov, Sergei Devadze, Rama Mounika Kodamanchili, Ahsan Rafiq, Jaan Raik, Masoud Daneshtalab
2024	—	`book`	Structural Decision Diagrams in Digital Test - Theory and Applications Raimund Ubar, Jaan Raik, Maksim Jenihhin, Artur Jutman
2023	—	`conf`	On-Chip Sensors Data Collection and Analysis for SoC Health Management. DFT Konstantin Shibin, Maksim Jenihhin, Artur Jutman, Sergei Devadze, Anton Tsertov
2023	J	`jnl`	On-Chip Sensors Data Collection and Analysis for SoC Health Management. CoRR Konstantin Shibin, Maksim Jenihhin, Artur Jutman, Sergei Devadze, Anton Tsertov
2022	J	`jnl`	HLS-based Optimization of Tau Triggering Algorithm for LHC: a case study. CoRR Natalia Cherezova, Dmitri Mihhailov, Sergei Devadze, Artur Jutman
2019	C	`conf`	A new FPGA-based Detection Method for Spurious Variations in PCBA Power Distribution Network. DDECS Sergei Odintsov, Ludovica Bozzoli, Corrado De Sio, Luca Sterpone, Artur Jutman
2019	A	`conf`	IEEE European Test Symposium (ETS). ITC Stephan Eggersglüß, Said Hamdioui, Artur Jutman, Maria K. Michael, Jaan Raik, Matteo Sonza Reorda, Mehdi Baradaran Tahoori, Elena-Ioana Vatajelu
2019	B	`conf`	Post-Silicon Validation of IEEE 1687 Reconfigurable Scan Networks. ETS Aleksa Damljanovic, Artur Jutman, Giovanni Squillero, Anton Tsertov
2019	A	`conf`	Simulation-based Equivalence Checking between IEEE 1687 ICL and RTL. ITC Aleksa Damljanovic, Artur Jutman, Michele Portolan, Ernesto Sánchez, Giovanni Squillero, Anton Tsertov
2017	A	`conf`	BASTION: Board and SoC test instrumentation for ageing and no failure found. DATE Artur Jutman, Christophe Lotz, Erik Larsson, Matteo Sonza Reorda, Maksim Jenihhin, Jaan Raik, Hans G. Kerkhoff, Rene Krenz-Baath, Piet Engelke
2017	J	`jnl`	Health Management for Self-Aware SoCs Based on IEEE 1687 Infrastructure. IEEE Des. Test Konstantin Shibin, Sergei Devadze, Artur Jutman, Martin Grabmann, Robin Pricken
2017	A	`conf`	Marginal PCB assembly defect detection on DDR3/4 memory bus. ITC Sergei Odintsov, Artur Jutman, Sergei Devadze
2017	J	`jnl`	Run-time reconfigurable instruments for advanced board-level testing. IEEE Instrum. Meas. Mag. Igor Aleksejev, Artur Jutman, Sergei Devadze
2016	A	`conf`	A suite of IEEE 1687 benchmark networks. ITC Anton Tsertov, Artur Jutman, Sergei Devadze, Matteo Sonza Reorda, Erik Larsson, Farrokh Ghani Zadegan, Riccardo Cantoro, Mehrdad Montazeri, Rene Krenz-Baath
2016	C	`conf`	Designing reliable cyber-physical systems overview associated to the special session at FDL'16. FDL Gadi Aleksandrowicz, Eli Arbel, Roderick Bloem, Timon D. ter Braak, Sergei Devadze, Görschwin Fey, Maksim Jenihhin, Artur Jutman, Hans G. Kerkhoff, Robert Könighofer, Jan Malburg, Shiri Moran, Jaan Raik, Gerard K. Rauwerda, Heinz Riener, Franz Röck, Konstantin Shibin, Kim Sunesen, Jinbo Wan, Yong Zhao
2016	B	`conf`	On coverage of timing related faults at board level. ETS Artur Jutman, Igor Aleksejev, Sergei Devadze
2016	—	`conf`	On-line fault classification and handling in IEEE1687 based fault management system for complex SoCs. LATS Konstantin Shibin, Sergei Devadze, Artur Jutman
2016	J	`jnl`	Optimization of Boundary Scan Tests Using FPGA-Based Efficient Scan Architectures. J. Electron. Test. Igor Aleksejev, Sergei Devadze, Artur Jutman, Konstantin Shibin
2015	Misc	`conf`	No Fault Found: The root cause. VTS Erik Larsson, Bill Eklow, Scott Davidsson, Rob Aitken, Artur Jutman, Christophe Lotz
2015	—	`conf`	Virtual reconfigurable scan-chains on FPGAs for optimized board test. LATS Igor Aleksejev, Sergei Devadze, Artur Jutman, Konstantin Shibin
2014	—	`conf`	Asynchronous Fault Detection in IEEE P1687 Instrument Network. NATW Konstantin Shibin, Sergei Devadze, Artur Jutman
2014	—	`conf`	Design, Verification, and Application of IEEE 1687. ATS Farrokh Ghani Zadegan, Erik Larsson, Artur Jutman, Sergei Devadze, Rene Krenz-Baath
2014	—	`conf`	High Quality System Level Test and Diagnosis. ATS Artur Jutman, Matteo Sonza Reorda, Hans-Joachim Wunderlich
2013	J	`jnl`	Effective Scalable IEEE 1687 Instrumentation Network for Fault Management. IEEE Des. Test Artur Jutman, Sergei Devadze, Konstantin Shibin
2013	—	`conf`	On in-system programming of non-volatile memories. MIXDES Anton Tsertov, Sergei Devadze, Artur Jutman, Artjom Jasnetski
2012	B	`conf`	Embedded synthetic instruments for Board-Level testing. ETS Artur Jutman, Sergei Devadze, Igor Aleksejev, Thomas Wenzel
2012	A	`conf`	FPGA-based synthetic instrumentation for board test. ITC Igor Aleksejev, Artur Jutman, Sergei Devadze, Sergei Odintsov, Thomas Wenzel
2012	B	`conf`	Re-using chip level DFT at board level. ETS Xinli Gu, Jeff Rearick, Bill Eklow, Martin Keim, Jun Qian, Artur Jutman, Krishnendu Chakrabarty, Erik Larsson
2011	—	`conf`	Automatic SoC Level Test Path Synthesis Based on Partial Functional Models. Asian Test Symposium Anton Tsertov, Raimund Ubar, Artur Jutman, Sergei Devadze
2011	—	`conf`	Invited paper: System-wide fault management based on IEEE P1687 IJTAG. ReCoSoC Artur Jutman, Sergei Devadze, Igor Aleksejev
2011	C	`conf`	SoC and Board Modeling for Processor-Centric Board Testing. DSD Anton Tsertov, Raimund Ubar, Artur Jutman, Sergei Devadze
2010	—	`conf`	Fast Fault Simulation for Extended Class of Faults in Scan Path Circuits. DELTA Raimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman
2010	C	`conf`	Fault collapsing with linear complexity in digital circuits. ISCAS Raimund Ubar, Dmitri Mironov, Jaan Raik, Artur Jutman
2010	A	`conf`	Parallel X-fault simulation with critical path tracing technique. DATE Raimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman
2010	—	`conf`	Structural fault collapsing by superposition of BDDs for test generation in digital circuits. ISQED Raimund Ubar, Dmitri Mironov, Jaan Raik, Artur Jutman
2010	C	`conf`	Structurally Synthesized Multiple Input BDDs for Speeding Up Logic-Level Simulation of Digital Circuits. DSD Dmitri Mironov, Raimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman
2010	—	`conf`	Testing beyond the SoCs in a lego style. EWDTS Anton Tsertov, Artur Jutman, Sergei Devadze
2009	—	`conf`	Diagnozer: A laboratory tool for teaching research in diagnosis of electronic systems. MSE Raimund Ubar, Artur Jutman, Jaan Raik, Sergei Kostin, Heinz-Dietrich Wuttke
2009	A	`conf`	Fast extended test access via JTAG and FPGAs. ITC Sergei Devadze, Artur Jutman, Igor Aleksejev, Raimund Ubar
2009	—	`conf`	Structurally synthesized multiple input BDDs for simulation of digital circuits. ICECS Raimund Ubar, Dmitri Mironov, Jaan Raik, Artur Jutman
2009	—	`conf`	Turning JTAG inside out for fast extended test access. LATW Sergei Devadze, Artur Jutman, Igor Aleksejev, Raimund Ubar
2008	C	`conf`	Calculation of LFSR Seed and Polynomial Pair for BIST Applications. DDECS Artur Jutman, Anton Tsertov, Raimund Ubar
2008	J	`jnl`	DefSim: A Remote Laboratory for Studying Physical Defects in CMOS Digital Circuits. IEEE Trans. Ind. Electron. Witold A. Pleskacz, Viera Stopjaková, Tomasz Borejko, Artur Jutman, Andrzej Walkanis
2008	—	`conf`	Parallel fault backtracing for calculation of fault coverage. ASP-DAC Raimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman
2008	—	`conf`	Reseeding using compaction of pre-generated LFSR sub-sequences. ICECS Artur Jutman, Igor Aleksejev, Jaan Raik, Raimund Ubar
2008	J	`jnl`	Test methods for crosstalk-induced delay and glitch faults in network-on-chip interconnects implementing asynchronous communication protocols. IET Comput. Digit. Tech. Tomas Bengtsson, Shashi Kumar, Raimund Ubar, Artur Jutman, Zebo Peng
2007	J	`jnl`	Learning Digital Test and Diagnostics via Internet. Int. J. Online Eng. Raimund Ubar, Artur Jutman, Margus Kruus, Elmet Orasson, Sergei Devadze, Heinz-Dietrich Wuttke
2007	B	`conf`	Ultra Fast Parallel Fault Analysis on Structurally Synthesized BDDs. ETS Raimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman
2006	—	`conf`	DefSim: CMOS Defects on Chip for Research and Education. LATW Witold A. Pleskacz, Tomasz Borejko, Andrzej Walkanis, Viera Stopjaková, Artur Jutman, Raimund Ubar
2006	—	`conf`	Fault Simulation with Parallel Critical Path Tracing for Combinatorial Circuits Using Structurally Synthesized BDDs. LATW Sergei Devadze, Jaan Raik, Artur Jutman, Raimund Ubar
2006	C	`conf`	Off-Line Testing of Delay Faults in NoC Interconnects. DSD Tomas Bengtsson, Artur Jutman, Shashi Kumar, Raimund Ubar, Zebo Peng
2005	C	`conf`	An Educational Environment for Digital Testing: Hardware, Tools, and Web-Based Runtime Platform. DSD Artur Jutman, Jaan Raik, Raimund Ubar, V. Vislogubov
2005	Misc	`conf`	Efficient Single-Pattern Fault Simulation on Structurally Synthesized BDDs. EDCC Jaan Raik, Raimund Ubar, Sergei Devadze, Artur Jutman
2004	—	`conf`	Asynchronous e-learning resources for hardware design issues. CompSysTech Artur Jutman, Alexander Sudnitson, Raimund Ubar, Heinz-Dietrich Wuttke
2004	B	`conf`	At-speed on-chip diagnosis of board-level interconnect faults. ETS Artur Jutman
2002	—	`conf`	Fast static compaction of tests composed of independent sequences: basic properties and comparison of methods. ICECS Jaan Raik, Artur Jutman, Raimund Ubar
2002	—	`conf`	Practical works for on-line teaching design and test of digital circuits. ICECS Artur Jutman, Raimund Ubar, Vladimir Hahanov, O. Skvortsova
2001	A	`conf`	Timing simulation of digital circuits with binary decision diagrams. DATE Raimund Ubar, Artur Jutman, Zebo Peng