Arnaud Virazel

199 papers A* 2A 26B 29C 33Misc 12Journal 37Unranked 59

Year	Rank	Type	Title / Venue / Authors
2025	C	`conf`	A Digital SRAM Modeling for Cell-Aware Testing and Test Algorithms Evaluation. IOLTS D. Ronga, Xhesila Xhafa, Eric Faehn, Patrick Girard, T. Vayssade, Arnaud Virazel
2025	C	`conf`	A Runtime Efficient Graph-Based Cell-Aware Model Generation for Structural SRAM Testing. IOLTS Gianmarco Mongelli, Xhesila Xhafa, Eric Faehn, Dylan Robins, Patrick Girard, Arnaud Virazel
2025	A	`conf`	Accelerating Cell-Aware Model Generation for Sequential Cells using Graph Theory. DATE Gianmarco Mongelli, Eric Faehn, Dylan Robins, Patrick Girard, Arnaud Virazel
2025	B	`conf`	European Test Symposium Teams: an Anniversary Snapshot. ETS Maksim Jenihhin, Jaan Raik, Artur Jutman, Natalia Cherezova, Raimund Ubar, Liviu Miclea, Szilárd Enyedi, I. Stefan, Ovidiu Stan, Cosmina Corches, Z. Peng, Petru Eles, Rolf Drechsler, S. Eggersglüß, Görschwin Fey, Andreas Glowatz, Daniel Tille, Georges G. E. Gielen, Anthony Coyette, Wim Dobbelaere, Ronny Vanhooren, P.-Y. Chuang, Erik Jan Marinissen, Giorgio Di Natale, M. Barragan, Paolo Maistri, S. Mir, Vatajelu I. Vatajelu, Paolo Bernardi, S. Di Carlo, Paolo Prinetto, Matteo Sonza Reorda, Massimo Violante, Haralampos-G. Stratigopoulos, M. K. Michael, Stelios Neophytou, Stavros Hadjitheophanous, Kyriakos Christou, M. Skitsas, Alberto Bosio, Bastien Deveautour, P. Girard, Marcello Traiola, Arnaud Virazel, F. Fernandes Dos Santos, Angeliki Kritikakou, Gioele Casagranda, Marzio Vallero, Flavio Vella, Paolo Rech, Letícia Maria Bolzani Poehls, Milos Krstic, Marko S. Andjelkovic, F. Vargas, Grigor Tshagharyan, Gurgen Harutyunyan, Valery A. Vardanian, Samvel K. Shoukourian, Yervant Zorian, Jennifer Dworak, Kundan Nepal, Theodore W. Manikas, Mottaqiallah Taouil, Moritz Fieback, Anteneh Gebregiorgis, Rajendra Bishnoi, Said Hamdioui, Abhijit Chatterjee, A. Saha, Suhasini Komarraju, K. Ma, Chandramouli N. Amarnath, Mehdi Baradaran Tahoori, Mahta Mayahinia, Maryam Rajabalipanah, Katayoon Basharkhah, N. Nosrati, Zahra Jahanpeima, Zain Navabi, Hans-Joachim Wunderlich, Sybille Hellebrand
2025	—	`conf`	Memory Dynamic Faults and Array-Level Faults Detector in Digital Test Environment. DFT D. Ronga, Eric Faehn, Patrick Girard, Arnaud Virazel
2025	J	`jnl`	SRAM Periphery Testing Using the Cell-Aware Test Methodology. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Xhesila Xhafa, Eric Faehn, Patrick Girard, Arnaud Virazel
2024	A	`conf`	A Fast and Efficient Graph-Based Methodology for Cell-Aware Model Generation. ITC Gianmarco Mongelli, Eric Faehn, Dylan Robins, Patrick Girard, Arnaud Virazel
2024	C	`conf`	A Graph-Based Methodology for Speeding up Cell-Aware Model Generation. IOLTS Gianmarco Mongelli, Xhesila Xhafa, Eric Faehn, Dylan Robins, Patrick Girard, Arnaud Virazel
2024	A	`conf`	A Novel March Test Algorithm for Testing 8T SRAM-Based IMC Architectures. DATE Lila Ammoura, Marie-Lise Flottes, Patrick Girard, Jean-Philippe Noel, Arnaud Virazel
2024	—	`conf`	A Structural Testing Approach for SRAM Address Decoders Using Cell-Aware Methodology. DFT Xhesila Xhafa, Eric Faehn, Patrick Girard, Arnaud Virazel
2024	—	`conf`	Producing a Bidirectional ATPG Compliant Verilog-HDL Memory Model of SRAM. DTTIS D. Ronga, Xhesila Xhafa, Eric Faehn, Patrick Girard, Thibault Vayssade, Arnaud Virazel
2023	B	`conf`	Intra-cell Resistive-Open Defect Analysis on a Foundry 8T SRAM-based IMC Architecture. ETS Lila Ammoura, Marie-Lise Flottes, Patrick Girard, Jean-Philippe Noel, Arnaud Virazel
2023	B	`conf`	Learning-Based Characterization Models for Quality Assurance of Emerging Memory Technologies. ETS Xhesila Xhafa, Patrick Girard, Arnaud Virazel
2023	B	`conf`	On Using Cell-Aware Methodology for SRAM Bit Cell Testing. ETS Xhesila Xhafa, Aymen Ladhar, Eric Faehn, Lorena Anghel, Gregory di Pendina, Patrick Girard, Arnaud Virazel
2023	A	`conf`	Predictor BIST: An "All-in-One" Optical Test Solution for CMOS Image Sensors. ITC Julia Lefevre, P. Debaud, Patrick Girard, Arnaud Virazel
2022	A	`conf`	A Comprehensive Learning-Based Flow for Cell-Aware Model Generation. ITC P. D'Hondt, Aymen Ladhar, Patrick Girard, Arnaud Virazel
2022	B	`conf`	A Generic Fast and Low Cost BIST Solution for CMOS Image Sensors. ETS Julia Lefevre, P. Debaud, Patrick Girard, Arnaud Virazel
2022	B	`conf`	A Lightweight, Plug-and-Play and Autonomous JTAG Authentication IP for Secure Device Testing. ETS S. Lapeyre, Nicolas Valette, Marc Merandat, Marie-Lise Flottes, Bruno Rouzeyre, Arnaud Virazel
2022	B	`conf`	Effective techniques for automatically improving the transition delay fault coverage of Self-Test Libraries. ETS Riccardo Cantoro, Francesco Garau, Patrick Girard, Nima Kolahimahmoudi, Sandro Sartoni, Matteo Sonza Reorda, Arnaud Virazel
2022	—	`ch.`	Test and Reliability of Approximate Hardware. Approximate Computing Marcello Traiola, Bastien Deveautour, Alberto Bosio, Patrick Girard, Arnaud Virazel
2021	A	`conf`	A Fast and Low Cost Embedded Test Solution for CMOS Image Sensors. ITC Julia Lefevre, Philippe Debaud, Patrick Girard, Arnaud Virazel
2021	A	`conf`	A Learning-Based Methodology for Accelerating Cell-Aware Model Generation. DATE P. D'Hondt, Aymen Ladhar, Patrick Girard, Arnaud Virazel
2021	B	`conf`	A Plug and Play Digital ABIST Controller for Analog Sensors in Secure Devices. ETS S. Lapeyre, Nicolas Valette, Marc Merandat, Marie-Lise Flottes, Bruno Rouzeyre, Arnaud Virazel
2021	J	`jnl`	A Survey of Test and Reliability Solutions for Magnetic Random Access Memories. Proc. IEEE Patrick Girard, Yuanqing Cheng, Arnaud Virazel, Wei Zhao, Rajendra Bishnoi, Mehdi B. Tahoori
2021	—	`conf`	Cell-Aware Diagnosis of Customer Returns Using Bayesian Inference. ISQED Safa Mhamdi, Patrick Girard, Arnaud Virazel, Alberto Bosio, Aymen Ladhar
2021	B	`conf`	Emerging Computing Devices: Challenges and Opportunities for Test and Reliability ETS Alberto Bosio, Ian O'Connor, Marcello Traiola, Jorge Echavarria, Jürgen Teich, Muhammad Abdullah Hanif, Muhammad Shafique, Said Hamdioui, Bastien Deveautour, Patrick Girard, Arnaud Virazel, Koen Bertels
2021	J	`jnl`	Improving TID Radiation Robustness of a CMOS OxRAM-Based Neuron Circuit by Using Enclosed Layout Transistors. IEEE Trans. Very Large Scale Integr. Syst. Pablo Ilha Vaz, Patrick Girard, Arnaud Virazel, Hassen Aziza
2021	—	`conf`	Preliminary Defect Analysis of 8T SRAM Cells for In-Memory Computing Architectures. DTIS Lila Ammoura, Marie-Lise Flottes, Patrick Girard, Arnaud Virazel
2021	C	`conf`	Reducing Overprovision of Triple Modular Reduncancy Owing to Approximate Computing. IOLTS Bastien Deveautour, Marcello Traiola, Arnaud Virazel, Patrick Girard
2021	C	`conf`	Self-Test Libraries Analysis for Pipelined Processors Transition Fault Coverage Improvement. IOLTS Riccardo Cantoro, Patrick Girard, Riccardo Masante, Sandro Sartoni, Matteo Sonza Reorda, Arnaud Virazel
2020	C	`conf`	A CMOS OxRAM-Based Neuron Circuit Hardened with Enclosed Layout Transistors for Aerospace Applications. IOLTS Pablo Ilha Vaz, Patrick Girard, Arnaud Virazel, Hassen Aziza
2020	A	`conf`	A Learning-Based Cell-Aware Diagnosis Flow for Industrial Customer Returns. ITC Safa Mhamdi, Patrick Girard, Arnaud Virazel, Alberto Bosio, Aymen Ladhar
2020	J	`jnl`	A Survey of Testing Techniques for Approximate Integrated Circuits. Proc. IEEE Marcello Traiola, Arnaud Virazel, Patrick Girard, Mario Barbareschi, Alberto Bosio
2020	B	`conf`	Design, Verification, Test and In-Field Implications of Approximate Computing Systems. ETS Alberto Bosio, Stefano Di Carlo, Patrick Girard, Ernesto Sánchez, Alessandro Savino, Lukás Sekanina, Marcello Traiola, Zdenek Vasícek, Arnaud Virazel
2020	C	`conf`	Development and Application of Embedded Test Instruments to Digital, Analog/RFs and Secure ICs. IOLTS Florence Azaïs, Serge Bernard, Mariane Comte, Bastien Deveautour, Sophie Dupuis, Hassan El Badawi, Marie-Lise Flottes, Patrick Girard, Vincent Kerzèrho, Laurent Latorre, François Lefèvre, Bruno Rouzeyre, Emanuele Valea, T. Vayssade, Arnaud Virazel
2020	B	`conf`	Learning-Based Cell-Aware Defect Diagnosis of Customer Returns. ETS Safa Mhamdi, Patrick Girard, Arnaud Virazel, Alberto Bosio, Aymen Ladhar
2020	A	`conf`	Maximizing Yield for Approximate Integrated Circuits. DATE Marcello Traiola, Arnaud Virazel, Patrick Girard, Mario Barbareschi, Alberto Bosio
2020	J	`jnl`	On Using Approximate Computing to Build an Error Detection Scheme for Arithmetic Circuits. J. Electron. Test. Bastien Deveautour, Arnaud Virazel, Patrick Girard, Valentin Gherman
2020	B	`conf`	QAMR: an Approximation-Based Fully Reliable TMR Alternative for Area Overhead Reduction. ETS Bastien Deveautour, Marcello Traiola, Arnaud Virazel, Patrick Girard
2019	—	`conf`	A Capacitor-Less CMOS Neuron Circuit for Neuromemristive Networks. NEWCAS Hassen Aziza, Mathieu Moreau, Annie Pérez, Arnaud Virazel, Patrick Girard
2019	C	`conf`	Towards Improvement of Mission Mode Failure Diagnosis for System-on-Chip. IOLTS Safa Mhamdi, Arnaud Virazel, Patrick Girard, Alberto Bosio, Etienne Auvray, Eric Faehn, Aymen Ladhar
2018	A	`conf`	An Effective Intra-Cell Diagnosis Flow for Industrial SRAMs. ITC Tien-Phu Ho, Eric Faehn, Arnaud Virazel, Alberto Bosio, Patrick Girard
2018	—	`conf`	Investigation of Mean-Error Metrics for Testing Approximate Integrated Circuits. DFT Marcello Traiola, Arnaud Virazel, Patrick Girard, Mario Barbareschi, Alberto Bosio
2018	—	`conf`	Is aproximate computing suitable for selective hardening of arithmetic circuits? DTIS Bastien Deveautour, Arnaud Virazel, Patrick Girard, Serge Pravossoudovitch, Valentin Gherman
2018	C	`conf`	On the Comparison of Different ATPG Approaches for Approximate Integrated Circuits. DDECS Marcello Traiola, Arnaud Virazel, Patrick Girard, Mario Barbareschi, Alberto Bosio
2018	J	`jnl`	Scan-Chain Intra-Cell Aware Testing. IEEE Trans. Emerg. Top. Comput. Aymen Touati, Alberto Bosio, Patrick Girard, Arnaud Virazel, Paolo Bernardi, Matteo Sonza Reorda, Etienne Auvray
2018	—	`conf`	Testing approximate digital circuits: Challenges and opportunities. LATS Marcello Traiola, Arnaud Virazel, Patrick Girard, Mario Barbareschi, Alberto Bosio
2017	J	`jnl`	A Cross-Level Power Estimation Technique to Enhance High-Level Power Models Quality. J. Low Power Electron. Alejandro Nocua, Arnaud Virazel, Alberto Bosio, Patrick Girard, Cyril Chevalier
2017	J	`jnl`	A Low-Cost Reliability vs. Cost Trade-Off Methodology to Selectively Harden Logic Circuits. J. Electron. Test. Imran Wali, Bastien Deveautour, Arnaud Virazel, Alberto Bosio, Patrick Girard, Matteo Sonza Reorda
2017	—	`conf`	An effective fault-injection framework for memory reliability enhancement perspectives. DTIS G. Harcha, Alberto Bosio, Patrick Girard, Arnaud Virazel, Paolo Bernardi
2017	—	`conf`	Approximate computing: Design & test for integrated circuits. LATS Alberto Bosio, Arnaud Virazel, Patrick Girard, Mario Barbareschi
2017	J	`jnl`	HPET: An Efficient Hybrid Power Estimation Technique to Improve High-Level Power Characterization. J. Circuits Syst. Comput. Alejandro Nocua, Arnaud Virazel, Alberto Bosio, Patrick Girard, Cyril Chevalier
2017	J	`jnl`	Microprocessor Testing: Functional Meets Structural Test. J. Circuits Syst. Comput. Aymen Touati, Alberto Bosio, Patrick Girard, Arnaud Virazel, Paolo Bernardi, Matteo Sonza Reorda
2017	C	`conf`	Towards approximation during test of Integrated Circuits. DDECS Imran Wali, Marcello Traiola, Arnaud Virazel, Patrick Girard, Mario Barbareschi, Alberto Bosio
2017	—	`conf`	Towards digital circuit approximation by exploiting fault simulation. EWDTS Marcello Traiola, Arnaud Virazel, Patrick Girard, Mario Barbareschi, Alberto Bosio
2016	J	`jnl`	A Hybrid Fault-Tolerant Architecture for Highly Reliable Processing Cores. J. Electron. Test. Imran Wali, Arnaud Virazel, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Matteo Sonza Reorda
2016	C	`conf`	A Hybrid Power Estimation Technique to improve IP power models quality. VLSI-SoC Alejandro Nocua, Arnaud Virazel, Alberto Bosio, Patrick Girard, Cyril Chevalier
2016	C	`conf`	A hybrid power modeling approach to enhance high-level power models. DDECS Alejandro Nocua, Arnaud Virazel, Alberto Bosio, Patrick Girard, Cyril Chevalier
2016	B	`conf`	A low-cost susceptibility analysis methodology to selectively harden logic circuits. ETS Imran Wali, Bastien Deveautour, Arnaud Virazel, Alberto Bosio, Patrick Girard, Matteo Sonza Reorda
2016	J	`jnl`	An Effective Power-Aware At-Speed Test Methodology for IP Qualification and Characterization. J. Electron. Test. Kapil Juneja, Darayus Adil Patel, Rajesh Kumar Immadi, Balwant Singh, Sylvie Naudet, Pankaj Agarwal, Arnaud Virazel, Patrick Girard
2016	—	`conf`	An effective BIST architecture for power-gating mechanisms in low-power SRAMs. ISQED Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Leonardo Bonet Zordan
2016	C	`conf`	An effective approach for functional test programs compaction. DDECS Aymen Touati, Alberto Bosio, Patrick Girard, Arnaud Virazel, Paolo Bernardi, Matteo Sonza Reorda
2016	—	`conf`	Analysis of setup and hold margins inside silicon for advanced technology nodes. ISQED Deepak-Kumar Arora, Darayus Adil Patel, Shahabuddin, Sanjay Kumar, Navin Kumar Dayani, Balwant Singh, Sylvie Naudet, Arnaud Virazel, Alberto Bosio
2016	—	`conf`	Auto-adaptive ultra-low power IC. DTIS Alberto Bosio, Philippe Debaud, Patrick Girard, Stephane Guilhot, Miroslav Valka, Arnaud Virazel
2016	J	`jnl`	Design for Test and Diagnosis of Power Switches. J. Circuits Syst. Comput. Miroslav Valka, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Philippe Debaud, Stephane Guilhot
2016	—	`conf`	Improving the Functional Test Delay Fault Coverage: A Microprocessor Case Study. ISVLSI Aymen Touati, Alberto Bosio, Patrick Girard, Arnaud Virazel, Paolo Bernardi, Matteo Sonza Reorda
2016	—	`conf`	Test of low power circuits: Issues and industrial practices. ICECS Alberto Bosio, Patrick Girard, Arnaud Virazel
2015	—	`conf`	An ATPG Flow to Generate Crosstalk-Aware Path Delay Pattern. ISVLSI Anu Asokan, Alberto Bosio, Arnaud Virazel, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch
2015	—	`conf`	An effective ATPG flow for Gate Delay Faults. DTIS Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Paolo Bernardi, Matteo Sonza Reorda
2015	B	`conf`	An effective hybrid fault-tolerant architecture for pipelined cores. ETS Imran Wali, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard
2015	—	`conf`	An efficient hybrid power modeling approach for accurate gate-level power estimation. ICM Alejandro Nocua, Arnaud Virazel, Alberto Bosio, Patrick Girard, Cyril Chevalier
2015	—	`conf`	Design and performance parameters of an ultra-low voltage, single supply 32bit processor implemented in 28nm FDSOI technology. ISQED Sylvain Clerc, Fady Abouzeid, Darayus Adil Patel, Jean-Marc Daveau, Cyril Bottoni, Lorenzo Ciampolini, Fabien Giner, David Meyer, Robin Wilson, Philippe Roche, Sylvie Naudet, Arnaud Virazel, Alberto Bosio, Patrick Girard
2015	C	`conf`	Design space exploration and optimization of a Hybrid Fault-Tolerant Architecture. IOLTS Imran Wali, Arnaud Virazel, Alberto Bosio, Patrick Girard, Matteo Sonza Reorda
2015	C	`conf`	Design-for-Diagnosis Architecture for Power Switches. DDECS Miroslav Valka, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, P. Debaud, S. Guilhot
2015	A	`conf`	Exploring the impact of functional test programs re-used for power-aware testing. DATE Aymen Touati, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Paolo Bernardi, Matteo Sonza Reorda
2015	—	`conf`	Scan-chain intra-cell defects grading. DTIS Aymen Touati, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Paolo Bernardi, Matteo Sonza Reorda
2014	J	`jnl`	A Complete Resistive-Open Defect Analysis for Thermally Assisted Switching MRAMs. IEEE Trans. Very Large Scale Integr. Syst. Joao Azevedo, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial, Jérémy Alvarez-Herault, Ken Mackay
2014	—	`conf`	A Comprehensive Evaluation of Functional Programs for Power-Aware Test. NATW Aymen Touati, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial, Arnaud Virazel, Paolo Bernardi
2014	—	`conf`	A Delay Probability Metric for Input Pattern Ranking Under Process Variation and Supply Noise. ISVLSI Anu Asokan, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel
2014	J	`jnl`	A New Hybrid Fault-Tolerant Architecture for Digital CMOS Circuits and Systems. J. Electron. Test. D. A. Tran, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Hans-Joachim Wunderlich
2014	C	`conf`	An intra-cell defect grading tool. DDECS Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial, Arnaud Virazel, S. Bernabovi, Paolo Bernardi
2014	J	`jnl`	Globally Constrained Locally Optimized 3-D Power Delivery Networks. IEEE Trans. Very Large Scale Integr. Syst. Aida Todri-Sanial, Sandip Kundu, Patrick Girard, Alberto Bosio, Luigi Dilillo, Arnaud Virazel
2014	J	`jnl`	Intra-Cell Defects Diagnosis. J. Electron. Test. Zhenzhou Sun, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Etienne Auvray
2014	—	`conf`	On the Generation of Diagnostic Test Set for Intra-cell Defects. ATS Zhenzhou Sun, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Etienne Auvray
2014	J	`jnl`	On the Test and Mitigation of Malfunctions in Low-Power SRAMs. J. Electron. Test. Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Nabil Badereddine
2014	C	`conf`	Path delay test in the presence of multi-aggressor crosstalk, power supply noise and ground bounce. DDECS Anu Asokan, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel
2014	—	`conf`	Power supply noise-aware workload assignments for homogeneous 3D MPSoCs with thermal consideration. ASP-DAC Yuanqing Cheng, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel
2014	C	`conf`	Protecting combinational logic in pipelined microprocessor cores against transient and permanent faults. DDECS Imran Wali, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri
2014	Misc	`conf`	TSV aware timing analysis and diagnosis in paths with multiple TSVs. VTS Carolina Metzler, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel
2014	C	`conf`	Test and diagnosis of power switches. DDECS Miroslav Valka, Alberto Bosio, Luigi Dilillo, Aida Todri, Arnaud Virazel, Patrick Girard, P. Debaud, S. Guilhot
2014	C	`conf`	Timing-aware ATPG for critical paths with multiple TSVs. DDECS Carolina Metzler, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel
2014	B	`conf`	iBoX - Jitter based Power Supply Noise sensor. ETS Miroslav Valka, Alberto Bosio, Luigi Dilillo, Aida Todri, Arnaud Virazel, Patrick Girard, P. Debaud, S. Guilhot
2013	J	`jnl`	A Study of Tapered 3-D TSVs for Power and Thermal Integrity. IEEE Trans. Very Large Scale Integr. Syst. Aida Todri, Sandip Kundu, Patrick Girard, Alberto Bosio, Luigi Dilillo, Arnaud Virazel
2013	Misc	`conf`	A built-in scheme for testing and repairing voltage regulators of low-power srams. VTS Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Nabil Badereddine
2013	—	`conf`	A novel method to mitigate TSV electromigration for 3D ICs. ISVLSI Yuanqing Cheng, Aida Todri-Sanial, Alberto Bosio, Luigi Dillio, Patrick Girard, Arnaud Virazel, Pascal Vivet, Marc Belleville
2013	—	`conf`	Adaptive Source Bias for Improved Resistive-Open Defect Coverage during SRAM Testing. Asian Test Symposium Elena I. Vatajelu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Aida Todri, Arnaud Virazel, Nabil Badereddine
2013	B	`conf`	Analyzing resistive-open defects in SRAM core-cell under the effect of process variability. ETS Elena I. Vatajelu, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Nabil Badereddine
2013	—	`conf`	Analyzing the effect of concurrent variability in the core cells and sense amplifiers on SRAM read access failures. DTIS Elena I. Vatajelu, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Nabil Badereddine
2013	—	`conf`	Characterization of an SRAM based particle detector for mixed-field radiation environments. IWASI Georgios Tsiligiannis, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Aida Todri-Sanial, Arnaud Virazel, Julien Mekki, Markus Brugger, J.-R. Vaillé, Frederic Wrobel, Frédéric Saigné
2013	B	`conf`	Computing detection probability of delay defects in signal line tsvs. ETS Carolina Metzler, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Pascal Vivet, Marc Belleville
2013	—	`conf`	Effect-cause intra-cell diagnosis at transistor level. ISQED Zhenzhou Sun, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Etienne Auvray
2013	—	`conf`	On the correlation between Static Noise Margin and Soft Error Rate evaluated for a 40nm SRAM cell. DFTS Elena I. Vatajelu, Georgios Tsiligiannis, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Aida Todri, Arnaud Virazel, Frederic Wrobel, Frédéric Saigné
2013	A	`conf`	On the reuse of read and write assist circuits to improve test efficiency in low-power SRAMs. ITC Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Nabil Badereddine
2013	C	`conf`	SRAM soft error rate evaluation under atmospheric neutron radiation and PVT variations. IOLTS Georgios Tsiligiannis, Elena I. Vatajelu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Aida Todri, Arnaud Virazel, Frederic Wrobel, Frédéric Saigné
2013	A	`conf`	Test solution for data retention faults in low-power SRAMs. DATE Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Nabil Badereddine
2013	J	`jnl`	Uncorrelated Power Supply Noise and Ground Bounce Consideration for Test Pattern Generation. IEEE Trans. Very Large Scale Integr. Syst. Aida Todri, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel
2013	—	`conf`	Worst-case power supply noise and temperature distribution analysis for 3D PDNs with multiple clock domains. NEWCAS Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel
2012	Misc	`conf`	A pseudo-dynamic comparator for error detection in fault tolerant architectures. VTS D. A. Tran, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Michael E. Imhof, Hans-Joachim Wunderlich
2012	Misc	`conf`	Advanced test methods for SRAMs. VTS Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel
2012	J	`jnl`	Analysis and Fault Modeling of Actual Resistive Defects in ATMEL TSTAC J. Electron. Test. Pierre-Didier Mauroux, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Benoît Godard, Gilles Festes, Laurent Vachez
2012	B	`conf`	Coupling-based resistive-open defects in TAS-MRAM architectures. ETS Joao Azevedo, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Guillaume Prenat, Jérémy Alvarez-Herault, Ken Mackay
2012	B	`conf`	Defect analysis in power mode control logic of low-power SRAMs. ETS Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Nabil Badereddine
2012	C	`conf`	Evaluation of test algorithms stress effect on SRAMs under neutron radiation. IOLTS Georgios Tsiligiannis, Luigi Dilillo, Alberto Bosio, Patrick Girard, Aida Todri, Arnaud Virazel, Antoine D. Touboul, Frederic Wrobel, Frédéric Saigné
2012	—	`conf`	Impact of Resistive-Bridge Defects in TAS-MRAM Architectures. Asian Test Symposium Joao Azevedo, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Guillaume Prenat, Jérémy Alvarez-Herault, Ken Mackay
2012	J	`jnl`	Impact of Resistive-Bridging Defects in SRAM at Different Technology Nodes. J. Electron. Test. Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine
2012	A	`conf`	Impact of resistive-open defects on the heat current of TAS-MRAM architectures. DATE Joao Azevedo, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial, Guillaume Prenat, Jérémy Alvarez-Herault, Ken Mackay
2012	A	`conf`	Low-power SRAMs power mode control logic: Failure analysis and test solutions. ITC Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Nabil Badereddine
2012	—	`conf`	Power Supply Noise Sensor Based on Timing Uncertainty Measurements. Asian Test Symposium Miroslav Valka, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, P. Debaud, S. Guilhot
2012	B	`conf`	Through-Silicon-Via resistive-open defect analysis. ETS Carolina Metzler, Aida Todri, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel
2012	—	`conf`	Why and How Controlling Power Consumption during Test: A Survey. Asian Test Symposium Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel
2011	B	`conf`	A Functional Power Evaluation Flow for Defining Test Power Limits during At-Speed Delay Testing. ETS Miroslav Valka, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Ernesto Sánchez, Mauricio de Carvalho, Matteo Sonza Reorda
2011	—	`conf`	A Hybrid Fault Tolerant Architecture for Robustness Improvement of Digital Circuits. Asian Test Symposium D. A. Tran, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Hans-Joachim Wunderlich
2011	C	`conf`	A study of path delay variations in the presence of uncorrelated power and ground supply noise. DDECS Aida Todri, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel
2011	—	`conf`	Effective Launch-to-Capture Power Reduction for LOS Scheme with Adjacent-Probability-Based X-Filling. Asian Test Symposium Kohei Miyase, Y. Uchinodan, Kazunari Enokimoto, Yuta Yamato, Xiaoqing Wen, Seiji Kajihara, Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Arnaud Virazel
2011	—	`conf`	Error Resilient Infrastructure for Data Transfer in a Distributed Neutron Detector. DFT Luigi Dilillo, Alberto Bosio, Miroslav Valka, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel
2011	—	`conf`	Failure Analysis and Test Solutions for Low-Power SRAMs. Asian Test Symposium Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Aida Todri, Arnaud Virazel, Nabil Badereddine
2011	C	`conf`	On using a SPICE-like TSTAC™ eFlash model for design and test. DDECS Pierre-Didier Mauroux, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Benoît Godard, Gilles Festes, Laurent Vachez
2011	A	`conf`	On using address scrambling to implement defect tolerance in SRAMs. ITC Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine
2011	C	`conf`	Optimized march test flow for detecting memory faults in SRAM devices under bit line coupling. DDECS Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine
2011	—	`conf`	Power-Aware Test Pattern Generation for At-Speed LOS Testing. Asian Test Symposium Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Kohei Miyase, Xiaoqing Wen
2010	J	`jnl`	A Comprehensive Analysis of Transition Fault Coverage and Test Power Dissipation for Launch-Off-Shift and Launch-Off-Capture Schemes. J. Low Power Electron. Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Mohammad Tehranipoor, Xiaoqing Wen, Nisar Ahmed
2010	J	`jnl`	A Comprehensive Framework for Logic Diagnosis of Arbitrary Defects. IEEE Trans. Computers Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel
2010	—	`conf`	A Comprehensive System-on-Chip Logic Diagnosis. Asian Test Symposium Youssef Benabboud, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Olivia Riewer
2010	—	`conf`	A Memory Fault Simulator for Radiation-Induced Effects in SRAMs. Asian Test Symposium Paolo Rech, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Luigi Dilillo
2010	A*	`conf`	A statistical simulation method for reliability analysis of SRAM core-cells. DAC Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine
2010	B	`conf`	A two-layer SPICE model of the ATMEL TSTAC ETS Pierre-Didier Mauroux, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Benoît Godard, Gilles Festes, Laurent Vachez
2010	C	`conf`	Analysis of power consumption and transition fault coverage for LOS and LOC testing schemes. DDECS Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Junxia Ma, Wei Zhao, Mohammad Tehranipoor, Xiaoqing Wen
2010	B	`conf`	Analysis of resistive-bridging defects in SRAM core-cells: A comparative study from 90nm down to 40nm technology nodes. ETS Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine
2010	Misc	`conf`	Detecting NBTI induced failures in SRAM core-cells. VTS Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine
2010	—	`conf`	Impact of Resistive-Bridging Defects in SRAM Core-Cell. DELTA Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine
2010	A	`conf`	Is test power reduction through X-filling good enough? ITC Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Mohammad Tehranipoor, Kohei Miyase, Xiaoqing Wen, Nisar Ahmed
2010	A	`conf`	Parity prediction synthesis for nano-electronic gate designs. ITC D. A. Tran, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Hans-Joachim Wunderlich
2010	B	`conf`	Setting test conditions for improving SRAM reliability. ETS Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine
2009	J	`jnl`	A SPICE-Like 2T-FLOTOX Core-Cell Model for Defect Injection and Faulty Behavior Prediction in eFlash. J. Electron. Test. Olivier Ginez, Jean Michel Daga, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
2009	—	`conf`	A case study on logic diagnosis for System-on-Chip. ISQED Youssef Benabboud, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Laroussi Bouzaida, Isabelle Izaute
2009	A	`conf`	A new design-for-test technique for SRAM core-cell stability faults. DATE Alexandre Ney, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian, Vincent Gouin
2009	J	`jnl`	Analysis of Resistive-Open Defects in SRAM Sense Amplifiers. IEEE Trans. Very Large Scale Integr. Syst. Alexandre Ney, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian
2009	C	`conf`	Comprehensive bridging fault diagnosis based on the SLAT paradigm. DDECS Youssef Benabboud, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Laroussi Bouzaida, Isabelle Izaute
2009	—	`conf`	Delay Fault Diagnosis in Sequential Circuits. Asian Test Symposium Youssef Benabboud, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Olivia Riewer
2009	J	`jnl`	Is triple modular redundancy suitable for yield improvement? IET Comput. Digit. Tech. Julien Vial, Arnaud Virazel, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch
2009	A	`conf`	NAND flash testing: A preliminary study on actual defects. ITC Pierre-Didier Mauroux, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Benoît Godard
2008	A	`conf`	A Design-for-Diagnosis Technique for SRAM Write Drivers. DATE Alexandre Ney, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian, Vincent Gouin
2008	A	`conf`	A History-Based Diagnosis Technique for Static and Dynamic Faults in SRAMs. ITC Alexandre Ney, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian
2008	J	`jnl`	A Selective Scan Slice Encoding Technique for Test Data Volume and Test Power Reduction. J. Electron. Test. Nabil Badereddine, Zhanglei Wang, Patrick Girard, Krishnendu Chakrabarty, Arnaud Virazel, Serge Pravossoudovitch, Christian Landrault
2008	Misc	`conf`	An SRAM Design-for-Diagnosis Solution Based on Write Driver Voltage Sensing. VTS Alexandre Ney, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian, Vincent Gouin
2008	—	`conf`	Improving Diagnosis Resolution without Physical Information. DELTA Alexandre Rousset, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
2008	A	`conf`	SoC Yield Improvement: Redundant Architectures to the Rescue? ITC Julien Vial, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
2008	—	`conf`	Using TMR Architectures for Yield Improvement. DFT Julien Vial, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
2008	C	`conf`	Yield Improvement, Fault-Tolerance to the Rescue?. IOLTS Julien Vial, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
2007	C	`conf`	A Mixed Approach for Unified Logic Diagnosis. DDECS Alexandre Rousset, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
2007	A	`conf`	A concurrent approach for testing address decoder faults in eFlash memories. ITC Olivier Ginez, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Jean Michel Daga
2007	J	`jnl`	Analysis and Test of Resistive-Open Defects in SRAM Pre-Charge Circuits. J. Electron. Test. Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian
2007	B	`conf`	DERRIC: A Tool for Unified Logic Diagnosis. ETS Alexandre Rousset, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
2007	B	`conf`	Dynamic Two-Cell Incorrect Read Fault Due to Resistive-Open Defects in the Sense Amplifiers of SRAMs. ETS Alexandre Ney, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian
2007	B	`conf`	Electrical Simulation Model of the 2T-FLOTOX Core-Cell for Defect Injection and Faulty Behavior Prediction in eFlash Memories. ETS Olivier Ginez, Jean Michel Daga, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
2007	—	`conf`	Fast Bridging Fault Diagnosis using Logic Information. ATS Alexandre Rousset, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
2007	—	`conf`	Influence of Threshold Voltage Deviations on 90nm SRAM Core-Cell Behavior. ATS Magali Bastian, Vincent Gouin, Patrick Girard, Christian Landrault, Alexandre Ney, Serge Pravossoudovitch, Arnaud Virazel
2007	Misc	`conf`	Retention and Reliability Problems in Embedded Flash Memories: Analysis and Test of Defective 2T-FLOTOX Tunnel Window. VTS Olivier Ginez, Jean Michel Daga, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
2007	A	`conf`	Slow write driver faults in 65nm SRAM technology: analysis and March test solution. DATE Alexandre Ney, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian
2007	Misc	`conf`	Un-Restored Destructive Write Faults Due to Resistive-Open Defects in the Write Driver of SRAMs. VTS Alexandre Ney, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian
2006	J	`jnl`	A Gated Clock Scheme for Low Power Testing of Logic Cores. J. Electron. Test. Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
2006	J	`jnl`	ADOFs and Resistive-ADOFs in SRAM Address Decoders: Test Conditions and March Solutions. J. Electron. Test. Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri, Magali Bastian Hage-Hassan
2006	Misc	`conf`	An Overview of Failure Mechanisms in Embedded Flash Memories. VTS Olivier Ginez, Jean Michel Daga, Marylene Combe, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
2006	C	`conf`	March Pre: an Efficient Test for Resistive-Open Defects in the SRAM Pre-charge Circuit. DDECS Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian
2006	C	`conf`	Structural-Based Power-Aware Assignment of Don't Cares for Peak Power Reduction during Scan Testing. VLSI-SoC Nabil Badereddine, Patrick Girard, Serge Pravossoudovitch, Christian Landrault, Arnaud Virazel, Hans-Joachim Wunderlich
2005	J	`jnl`	Analysis of Dynamic Faults in Embedded-SRAMs: Implications for Memory Test. J. Electron. Test. Simone Borri, Magali Hage-Hassan, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel
2005	—	`conf`	Controlling Peak Power Consumption During Scan Testing: Power-Aware DfT and Test Set Perspectives. PATMOS Nabil Badereddine, Patrick Girard, Arnaud Virazel, Serge Pravossoudovitch, Christian Landrault
2005	Misc	`conf`	Data Retention Fault in SRAM Memories: Analysis and Detection Procedures. VTS Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian Hage-Hassan
2005	J	`jnl`	Efficient March Test Procedure for Dynamic Read Destructive Fault Detection in SRAM Memories. J. Electron. Test. Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri, Magali Hage-Hassan
2005	B	`conf`	Resistive-open defect influence in SRAM pre-charge circuits: analysis and characterization. ETS Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian Hage-Hassan
2005	A*	`conf`	Resistive-open defect injection in SRAM core-cell: analysis and comparison between 0.13 µm and 90 nm technologies. DAC Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian
2005	C	`conf`	Scan Cell Reordering for Peak Power Reduction during Scan Test Cycles. VLSI-SoC Nabil Badereddine, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Christian Landrault
2004	A	`conf`	Design of Routing-Constrained Low Power Scan Chains. DATE Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
2004	—	`conf`	Design of Routing-Constrained Low Power Scan Chains. DELTA Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
2004	B	`conf`	Dynamic read destructive fault in embedded-SRAMs: analysis and march test solution. ETS Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri, Magali Bastian Hage-Hassan
2004	Misc	`conf`	March iC-: An Improved Version of March C- for ADOFs Detection. VTS Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri
2004	—	`conf`	Resistive-Open Defects in Embedded-SRAM Core Cells: Analysis and March Test Solution. Asian Test Symposium Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri, Magali Bastian Hage-Hassan
2003	—	`conf`	Comparison of Open and Resistive-Open Defect Test Conditions in SRAM Address Decoders. Asian Test Symposium Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri
2003	—	`conf`	Defect-oriented dynamic fault models for embedded-SRAMs. ETW Simone Borri, Magali Hage-Hassan, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel
2002	J	`jnl`	Hardware Generation of Random Single Input Change Test Sequences. J. Electron. Test. René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
2002	J	`jnl`	High Defect Coverage with Low-Power Test Sequences in a BIST Environment. IEEE Des. Test Comput. Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Hans-Joachim Wunderlich
2002	Misc	`conf`	On Using Efficient Test Sequences for BIST. VTS René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
2001	J	`jnl`	Delay Fault Testing: Choosing Between Random SIC and Random MIC Test Sequences. J. Electron. Test. Arnaud Virazel, René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch
2001	—	`conf`	On hardware generation of random single input change test sequences. ETW René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
2001	C	`conf`	Random Adjacent Sequences: An Efficient Solution for Logic BIST. VLSI-SOC René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
2000	—	`conf`	Comparison between Random and Pseudo-Random Generation for BIST of Delay, Stuck-at and Bridging Faults. IOLTW Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
2000	—	`conf`	Delay fault testing: choosing between random SIC and random MIC test sequences. ETW Arnaud Virazel, René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch
1999	J	`jnl`	A Scan-BIST Structure to Test Delay Faults in Sequential Circuits. J. Electron. Test. Patrick Girard, Christian Landrault, V. Moreda, Serge Pravossoudovitch, Arnaud Virazel
1998	—	`conf`	A BIST Structure to Test Delay Faults in a Scan Environment. Asian Test Symposium Patrick Girard, Christian Landrault, V. Moreda, Serge Pravossoudovitch, Arnaud Virazel