Armin Tajalli - RankMe

93 papers A 4C 17Journal 26Unranked 46

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	A 16nm 140-fJ/b/dB Dual-Mode ENRZ/NRZ Serial Data Transceiver with Dynamic Voltage Scaling. CICC Armin Tajalli, Cosimo Aprile, Milad Ataei, Rolf Beerwerth, Dario Carneli, Maik Fuhs, Kiarash Gharibdoust, Ali Hormati, James Hudner, Victor Perrin, Amin Shokrollahi, Richard Simpson, Andrew Stewart, David Stauffer, Giuseppe Surace, Roger Ulrich, Patrick Urban, Mark Venneborger, Anant Singh
2025	A	`conf`	A Spectral-Efficient Low-Power NRZ/PAM-4 Dual-Mode Wireline Transmitter for Multidrop Interfaces. ISLPED DongGeon Kim, Kiarash Gharibdoust, Armin Tajalli, Kyungtae Lee, Gain Kim
2024	—	`conf`	A 29 GHz Sub-Sampling PLL with 25.6-fs-rms RJ based on a Discrete-Time Integrating PD in 45nm RF SOI. CICC Rajath Bindiganavile, Asif Wahid, Armin Tajalli
2024	J	`jnl`	A Digital Background Calibration Circuit for Coarse-Fine Timing Mismatch in VCO-Based ADCs. IEEE Trans. Circuits Syst. II Express Briefs Shea Smith, Armin Tajalli, Yen-Cheng Kuan, Shiuh-Hua Wood Chiang
2024	—	`conf`	Effect of Parameter Drift on the Accuracy of Analog CNN Accelerators. MWSCAS Michael Keyser, Farzad T. Ordubadi, Armin Tajalli
2024	C	`conf`	Hadamard Multi-Tone Signaling in Multi-Wire Pulse Amplitude Modulation for Next Generation Wireline Communication. ISCAS Asif Wahid, Rajath Bindiganavile, Armin Tajalli
2024	—	`conf`	Speed-Noise-Power Trade-Offs in Design of Scaled FET Circuits Using $\mathrm{C}/\mathrm{I}_{\mathrm{D}}$ Methodology. LASCAS Armin Tajalli
2024	J	`jnl`	Trade-Offs in Design of Wide-Band Inverter-Based Amplifiers. IEEE Trans. Very Large Scale Integr. Syst. Behdad Jamadi, Shiuh-Hua Wood Chiang, Armin Tajalli
2023	—	`conf`	A 0.12-V 200-Hz-BW 10-Bit ADC Using Quad-Channel VCO and Interpolation Linearization. A-SSCC Shea Smith, Taylor Barton, Yen-Cheng Kuan, Armin Tajalli, Mau-Chung Frank Chang, Shiuh-Hua Wood Chiang
2023	—	`conf`	A VCO Linearization Technique Using Dual-VCO and Interpolation for Time-Based ADCs. MWSCAS Shea Smith, Armin Tajalli, Shiuh-Hua Wood Chiang
2023	C	`conf`	Computational Efficiency of Circuit Design and Optimization Algorithms: A Comparative Study. ISCAS Alec Adair, Armin Tajalli
2023	—	`conf`	Design Flow to Develop Wideband Inverter-Based Circuits Using C/ID Methodology. SMACD Behdad Jamadi, Fariborz T. Ordubadi, Armin Tajalli
2023	—	`conf`	Extending C/ID Methodology for Optimal Implementation of Single-Stage Discrete-Time Amplifiers. SMACD Sakthidasan Kalidasan, Armin Tajalli
2023	J	`jnl`	Noise-Aware FET Circuit Design Based on C/I IEEE Trans. Circuits Syst. II Express Briefs Asif Wahid, Jacob Atkinson, Rajath Bindiganavile, Farzan Jazaeri, Armin Tajalli
2022	—	`conf`	Balanced Circuit Topologies and Their Applications in Data Movement. MWSCAS Armin Tajalli, Amin Shokrollahi
2022	J	`jnl`	Systematic Design of Loop Circuit Topologies Using C/I IEEE Trans. Very Large Scale Integr. Syst. Jacob Atkinson, Anthony Bailey, Armin Tajalli
2021	J	`jnl`	A 32-Gb/s PAM-4 SST Transmitter With Four-Tap FFE Using High-Impedance Driver in 28-nm FDSOI. IEEE Trans. Very Large Scale Integr. Syst. Firat Celik, Ayca Akkaya, Armin Tajalli, Yusuf Leblebici
2021	—	`conf`	A Controllable KVCO Ring VCO Topology. MWSCAS Rajath Bindiganavile, Armin Tajalli
2021	C	`conf`	Optimal PAM Order for Wireline Communication. ISCAS Asif Wahid, Rajath Bindiganavile, Armin Tajalli
2021	J	`jnl`	Power-Speed Trade-Offs in Design of Scaled FET Circuits Using C/I IEEE Trans. Circuits Syst. I Regul. Pap. Armin Tajalli
2020	J	`jnl`	A 1.02-pJ/b 20.83-Gb/s/Wire USR Transceiver Using CNRZ-5 in 16-nm FinFET. IEEE J. Solid State Circuits Armin Tajalli, Mani Bastani Parizi, Dario Albino Carnelli, Chen Cao, Kiarash Gharibdoust, Davide Gorret, Amit Gupta, Christopher Hall, Ahmed Hassanin, Klaas L. Hofstra, Brian Holden, Ali Hormati, John Keay, Yohann Mogentale, Victor Perrin, John Phillips, Sumathi Raparthy, Amin Shokrollahi, David Stauffer, Richard Simpson, Andrew Stewart, Giuseppe Surace, Omid Talebi Amiri, Emanuele Truffa, Anton Tschank, Roger Ulrich, Christoph Walter, Anant Singh
2020	C	`conf`	A Low-Power 10 to 15 Gb/s Common-Gate CTLE Based on Optimized Active Inductors. VLSI-SOC Amin Aghighi, Armin Tajalli, Mohammad Taherzadeh-Sani
2020	C	`conf`	An ULP Self-Supplied Brain Interface Circuit. VLSI-SOC Amin Aghighi, Massood Tabib-Azar, Armin Tajalli
2020	—	`conf`	Digitally-Assisted Peak Detector for Periodic Signal. MWSCAS Asif Wahid, Armin Tajalli
2020	C	`conf`	Energy and Area Efficient Mixed-Mode MCMC MIMO Detector. VLSI-SOC Amin Aghighi, Behrouz Farhang-Boroujeny, Armin Tajalli
2020	—	`conf`	Mixed-Mode Signal Processing for Implementing MCMC MIMO Detector. VLSI-SoC (Selected Papers) Amin Aghighi, Behrouz Farhang-Boroujeny, Armin Tajalli
2020	C	`conf`	Power System Emulator Based on PLL Architecture. ISCAS Asif Wahid, Sayed Abdullah Sadat, Mostafa Ardakani, Armin Tajalli
2020	—	`conf`	Short-Reach and Pin-Efficient Interfaces Using Correlated NRZ. CICC Armin Tajalli, Mani Bastani Parizi, Dario Albino Carnelli, Chen Cao, Kiarash Gharibdoust, Amit Gupta, Ahmed Hassanin, Klaas L. Hofstra, Brian Holden, Ali Hormati, John Keay, Amin Shokrollahi, David Stauffer, Richard Simpson, Andrew Stewart, Giuseppe Surace, Omid Talebi Amiri, Anton Tschank, Roger Ulrich, Christoph Walter, Anant Singh
2019	—	`conf`	A 1.02pJ/b 417Gb/s/mm USR Link in 16nm FinFET. VLSI Circuits Armin Tajalli, Mani Bastani Parizi, Dario Albino Carnelli, Chen Cao, John Fox, Kiarash Gharibdoust, Davide Gorret, Amit Gupta, Christopher Hall, Ahmed Hassanin, Klaas L. Hofstra, Brian Holden, Ali Hormati, John Keay, Yohann Mogentale, G. Paul, Victor Perrin, John Phillips, Sumathi Raparthy, Amin Shokrollahi, David Stauffer, Richard Simpson, Andrew Stewart, Giuseppe Surace, Omid Talebi Amiri, Emanuele Truffa, Anton Tschank, Roger Ulrich, Christoph Walter, Anant Singh
2019	—	`conf`	A Review on Quantum Computing: From Qubits to Front-end Electronics and Cryogenic MOSFET Physics. MIXDES Farzan Jazaeri, Arnout Beckers, Armin Tajalli, Jean-Michel Sallese
2019	—	`conf`	CMOS Amplifier Design Based on Extended $g_{m}/I_{D}$ Methodology. NEWCAS Amin Aghighi, Jacob Atkinson, Nickolas Bybee, Stuart Anderson, Mitchell Crane, Anthony Bailey, Reuben Morell, Ahmed Hassanin, Armin Tajalli
2019	—	`conf`	ISI Sensitivity of PAM Signaling for Very High-Speed Short-Reach Copper Links. NEWCAS Firat Celik, Ayca Akkaya, Armin Tajalli, Yusuf Leblebici
2019	—	`conf`	JESD204B Compliant 12.5 Gb/s LVDS and SST Transmitters in 28 nm FD-SOI CMOS. PRIME Firat Celik, Ayca Akkaya, Armin Tajalli, Andreas Burg, Yusuf Leblebici
2019	—	`conf`	Multi-Stage Current-Steering Amplifier Design Based on Extended gm/ID Methodology. MWSCAS Jacob Atkinson, Amin Aghighi, Stuart Anderson, Anthony Bailey, Mitchell Crane, Armin Tajalli
2019	—	`conf`	Spectrum-Efficient Communication Over Copper Using Hybrid Amplitude and Spatial Signaling. MWSCAS Rajath Bindiganavile, Armin Tajalli
2018	—	`conf`	A 10b SAR ADC with Widely Scalable Sampling Rate and AGC Amplifier Front-End. NORCAS Ayca Akkaya, Firat Celik, Armin Tajalli, Yusuf Leblebici
2017	J	`jnl`	A Time-Division Multiplexing Signaling Scheme for Inter-Symbol/Channel Interference Reduction in Low-Power Multi-Drop Memory Links. IEEE Trans. Circuits Syst. II Express Briefs Gain Kim, Chen Cao, Kiarash Gharibdoust, Armin Tajalli, Yusuf Leblebici
2016	—	`conf`	10.1 A pin-efficient 20.83Gb/s/wire 0.94pJ/bit forwarded clock CNRZ-5-coded SerDes up to 12mm for MCM packages in 28nm CMOS. ISSCC Amin Shokrollahi, Dario Albino Carnelli, John Fox, Klaas L. Hofstra, Brian Holden, Ali Hormati, Peter Hunt, Margaret Johnston, John Keay, Sergio Pesenti, Richard Simpson, David Stauffer, Andrew Stewart, Giuseppe Surace, Armin Tajalli, Omid Talebi Amiri, Anton Tschank, Roger Ulrich, Christoph Walter, Fabio Licciardello, Yohann Mogentale, Anant Singh
2016	J	`jnl`	A 4×9 Gb/s 1pJ/b Hybrid NRZ/Multi-Tone I/O With Crosstalk and ISI Reduction for Dense Interconnects. IEEE J. Solid State Circuits Kiarash Gharibdoust, Armin Tajalli, Yusuf Leblebici
2016	J	`jnl`	A Digital Spectrum Shaping Signaling Serial-Data Transceiver With Crosstalk and ISI Reduction Property in Multidrop Interfaces. IEEE Trans. Circuits Syst. II Express Briefs Gain Kim, Kiarash Gharibdoust, Armin Tajalli, Yusuf Leblebici
2016	C	`conf`	A fully-digital spectrum shaping signaling for serial-data transceiver with crosstalk and ISI reduction property in multi-drop memory interfaces. ISCAS Kiarash Gharibdoust, Gain Kim, Armin Tajalli, Yusuf Leblebici
2016	—	`conf`	A wideband MDLL with jitter reduction scheme for forwarded clock serial links in 40 nm CMOS. NEWCAS Kiarash Gharibdoust, Armin Tajalli, Yusuf Leblebici
2015	—	`conf`	10.3 A 7.5mW 7.5Gb/s mixed NRZ/multi-tone serial-data transceiver for multi-drop memory interfaces in 40nm CMOS. ISSCC Kiarash Gharibdoust, Armin Tajalli, Yusuf Leblebici
2015	—	`conf`	A 4×9 Gb/s 1 pJ/b NRZ/multi-tone serial-data transceiver with crosstalk reduction architecture for multi-drop memory interfaces in 40nm CMOS. VLSIC Kiarash Gharibdoust, Armin Tajalli, Yusuf Leblebici
2015	J	`jnl`	A subthreshold current-sensing ΣΔ modulator for low-voltage and low-power sensor interfaces. Int. J. Circuit Theory Appl. Nikola Katic, Ibrahim Kazi, Armin Tajalli, Alexandre Schmid, Yusuf Leblebici
2015	J	`jnl`	Analysis and Characterization of Variability in Subthreshold Source-Coupled Logic Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. Mahsa Shoaran, Armin Tajalli, Massimo Alioto, Alexandre Schmid, Yusuf Leblebici
2015	J	`jnl`	Hybrid NRZ/Multi-Tone Serial Data Transceiver for Multi-Drop Memory Interfaces. IEEE J. Solid State Circuits Kiarash Gharibdoust, Armin Tajalli, Yusuf Leblebici
2015	C	`conf`	Jitter analysis and measurement in subthreshold source-coupled differential ring oscillators. ISCAS Mahsa Shoaran, Armin Tajalli, Massimo Alioto, Yusuf Leblebici
2014	—	`conf`	A 5.43-μW 0.8-V subthreshold current-sensing ΣΔ modulator for low-noise sensor interfaces. NORCHIP Nikola Katic, Ibrahim Kazi, Armin Tajalli, Alexandre Schmid, Yusuf Leblebici
2012	J	`jnl`	Wide-Range Dynamic Power Management in Low-Voltage Low-Power Subthreshold SCL. IEEE Trans. Circuits Syst. II Express Briefs Armin Tajalli, Yusuf Leblebici
2011	J	`jnl`	Design Trade-offs in Ultra-Low-Power Digital Nanoscale CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. Armin Tajalli, Yusuf Leblebici
2011	—	`conf`	Design trade-offs in ultra-low-power CMOS and STSCL digital systems. ECCTD Armin Tajalli, Yusuf Leblebici
2011	J	`jnl`	Low-Power and Widely Tunable Linearized Biquadratic Low-Pass Transconductor-C Filter. IEEE Trans. Circuits Syst. II Express Briefs Armin Tajalli, Yusuf Leblebici
2010	—	`conf`	A 9 pW/Hz adjustable clock generator with 3-decade tuning range for dynamic power management in subthreshold SCL systems. ESSCIRC Armin Tajalli, Yusuf Leblebici
2010	J	`jnl`	Nanowatt Range Folding-Interpolating Analog-to-Digital Converter Using Subthreshold Source-Coupled Circuits. J. Low Power Electron. Armin Tajalli, Yusuf Leblebici
2010	—	`conf`	Subthreshold current-mode oscillator-based quantizer with 3-decade scalable sampling rate and pico-Ampere range resolution. ESSCIRC Armin Tajalli, Yusuf Leblebici
2010	A	`conf`	Ultra-low power mixed-signal design platform using subthreshold source-coupled circuits. DATE Armin Tajalli, Yusuf Leblebici
2009	J	`jnl`	A Slew Controlled LVDS Output Driver Circuit in 0.18 µm CMOS Technology. IEEE J. Solid State Circuits Armin Tajalli, Yusuf Leblebici
2009	—	`conf`	A widely-tunable and ultra-low-power MOSFET-C filter operating in subthreshold. CICC Armin Tajalli, Yusuf Leblebici
2009	J	`jnl`	Improving Power-Delay Performance of Ultra-Low-Power Subthreshold SCL Circuits. IEEE Trans. Circuits Syst. II Express Briefs Armin Tajalli, Massimo Alioto, Yusuf Leblebici
2009	J	`jnl`	Leakage Current Reduction Using Subthreshold Source-Coupled Logic. IEEE Trans. Circuits Syst. II Express Briefs Armin Tajalli, Yusuf Leblebici
2009	C	`conf`	Subthreshold Leakage Reduction: A Comparative Study of SCL and CMOS Design. ISCAS Armin Tajalli, Yusuf Leblebici
2009	—	`conf`	Subthreshold SCL for ultra-low-power SRAM and low-activity-rate digital systems. ESSCIRC Armin Tajalli, Yusuf Leblebici
2009	J	`jnl`	Ultra-low power 32-bit pipelined adder using subthreshold source-coupled logic with 5 fJ/stage PDP. Microelectron. J. Armin Tajalli, Elizabeth J. Brauer, Yusuf Leblebici
2008	—	`conf`	A 1.8V 12-bit 230-MS/s pipeline ADC in 0.18μm CMOS technology. APCCAS Thomas Liechti, Armin Tajalli, Omer Can Akgun, Zeynep Toprak Deniz, Yusuf Leblebici
2008	—	`conf`	Improving the Power-Delay Performance in Subthreshold Source-Coupled Logic Circuits. PATMOS Armin Tajalli, Massimo Alioto, Elizabeth J. Brauer, Yusuf Leblebici
2008	C	`conf`	Improving the power-delay product in SCL circuits using source follower output stage. ISCAS Armin Tajalli, Frank K. Gürkaynak, Yusuf Leblebici, Massimo Alioto, Elizabeth J. Brauer
2008	J	`jnl`	Low-power analogue phase interpolator based clock and data recovery with high-frequency tolerance. IET Circuits Devices Syst. Pooyan Sakian, Mohsen Saffari, Seyed Mojtaba Atarodi, Armin Tajalli
2008	J	`jnl`	Subthreshold Source-Coupled Logic Circuits for Ultra-Low-Power Applications. IEEE J. Solid State Circuits Armin Tajalli, Elizabeth J. Brauer, Yusuf Leblebici, Eric A. Vittoz
2007	C	`conf`	A Power Optimized Base-Band Circuitry for the Low-IF Receivers. ISCAS Ramin Zanbaghi, Seyed Mojtaba Atarodi, Armin Tajalli
2007	J	`jnl`	A Power-Efficient Clock and Data Recovery Circuit in 0.18 µm CMOS Technology for Multi-Channel Short-Haul Optical Data Communication. IEEE J. Solid State Circuits Armin Tajalli, Paul Muller, Yusuf Leblebici
2007	J	`jnl`	Top-Down Design of a Low-Power Multi-Channel 2.5-Gbit/s/Channel Gated Oscillator Clock-Recovery Circuit CoRR Paul Muller, Armin Tajalli, Seyed Mojtaba Atarodi, Yusuf Leblebici
2007	J	`jnl`	Tradeoffs in Design of Low-Power Gated-Oscillator Clock and Data Recovery Circuits. J. Low Power Electron. Armin Tajalli, Paul Muller, Yusuf Leblebici
2007	—	`conf`	Ultra low power subthreshold MOS current mode logic circuits using a novel load device concept. ESSCIRC Armin Tajalli, Eric A. Vittoz, Yusuf Leblebici, Elizabeth J. Brauer
2006	C	`conf`	A 1/4 rate linear phase detector for PLL-based CDR circuits. ISCAS Mohsen Saffari, Seyed Mojtaba Atarodi, Armin Tajalli
2006	—	`conf`	A Q-Enhanced Biquadratic Gm-C Filter for High Frequency Applications. ICECS Mohsen Moezzi, Ramin Zanbaghi, Mojtaba Atarodi, Armin Tajalli
2006	C	`conf`	A low-power CMOS Gm-C filter for wireless receiver applications with on-chip automatic tuning system. ISCAS Habib Adrang, Reza Lotfi, Khalil Mafinejhad, Armin Tajalli, Saeed Mehrmanesh
2006	C	`conf`	A technique to suppress tail current flicker noise in CMOS LC VCOs. ISCAS Saeed Saeedi, Saeid Mehrmanesh, Armin Tajalli, Seyed Mojtaba Atarodi
2006	C	`conf`	Analysis and modeling of jitter and frequency tolerance in gated oscillator based CDRs. ISCAS Armin Tajalli, Paul Muller, Seyed Mojtaba Atarodi, Yusuf Leblebici
2005	—	`conf`	A fractional delay-locked loop for on chip clock generation applications. ASP-DAC Pooya Torkzadeh, Armin Tajalli, Seyed Mojtaba Atarodi
2005	A	`conf`	A low-power, multichannel gated oscillator-based CDR for short-haul applications. ISLPED Armin Tajalli, Paul Muller, Seyed Mojtaba Atarodi, Yusuf Leblebici
2005	—	`conf`	A multichannel 3.5mW/Gbps/channel gated oscillator based CDR in a 0.18μm digital CMOS technology. ESSCIRC Armin Tajalli, Paul Muller, Mojtaba Atarodi, Yusuf Leblebici
2005	—	`conf`	A wide tuning range, 1 GHz-2.5 GHz DLL-based fractional frequency synthesizer. ISCAS (5) Pooya Torkzadeh, Armin Tajalli, Seyed Mojtaba Atarodi
2005	—	`conf`	Analysis of jitter peaking and jitter accumulation in re-circulating delay-locked loops. ISCAS (3) Pooya Torkzadeh, Armin Tajalli, Seyed Mojtaba Atarodi
2005	A	`conf`	Top-Down Design of a Low-Power Multi-Channel 2.5-Gbit/s/Channel Gated Oscillator Clock-Recovery Circuit. DATE Paul Muller, Armin Tajalli, Seyed Mojtaba Atarodi, Yusuf Leblebici
2004	—	`conf`	A duty cycle control circuit for high speed applications. ISCAS (1) Armin Tajalli, Saeid Mehrmanesh, Seyed Mojtaba Atarodi
2004	—	`conf`	Design and optimization of a high PSRR CMOS bandgap voltage reference. ISCAS (1) Armin Tajalli, Seyed Mojtaba Atarodi, Abbas Khodaverdi, Farzad Sahandi Esfanjani
2003	—	`conf`	A compact biquadratic g ISCAS (1) Armin Tajalli, Seyed Mojtaba Atarodi
2003	—	`conf`	A compact, low power, fully integrated clock frequency doubler. ICECS Armin Tajalli, Abbas Khodaverdi, Seyed Mojtaba Atarodi
2003	—	`conf`	Design considerations for a 1.5-V, 10.7-MHz bandpass gm-C filter in a 0.6µm standard CMOS technology. ISCAS (1) Armin Tajalli, Seyed Mojtaba Atarodi
2003	—	`conf`	Structured design of an integrated subscriber line interface system and circuit. ISCAS (2) Armin Tajalli, Seyed Mojtaba Atarodi
2002	—	`conf`	A low-power subscriber line interface circuit in a high-voltage CMOS technology. ISCAS (5) Mohammad B. Vahidfar, Armin Tajalli, Seyed Mojtaba Atarodi
2000	C	`conf`	A 1.5-V supply, video range frequency, Gm-C filter. ISCAS Armin Tajalli, Mojtaba Atarodi, Akbar Adibi