Armando Astarloa

75 papers B 10C 7Misc 1Journal 28Unranked 29

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	A Proof-Of-Concept ASIC RISC-V Based SoC for Industrial Applications. DCIS Sara Alonso, Alejandro Arteaga, Leire Muguira, Carlos Cuadrado, Aitzol Zuloaga, Jaime Jiménez, Jesús Lázaro, Jose Ignacio Garate, José Ángel Araujo, Victor Martínez, Unai Bidarte, Armando Astarloa
2025	J	`jnl`	CRYSTALS-Dilithium post-quantum cyber-secure SoC for wired communications in critical systems. Internet Things Armando Astarloa, Jesús Lázaro, Jose Ignacio Garate
2025	—	`conf`	Performance Analysis of Convolution Function for IA Edge Computing Acceleration Using a 32-bit RISC-V CPU Implementation. DCIS David Cantero, Alexander Ugena, Laura Sanz, Alejandro Arteaga, Armando Astarloa
2024	J	`jnl`	AXI Lite Redundant On-Chip Bus Interconnect for High Reliability Systems. IEEE Trans. Reliab. Jesús Lázaro, Armando Astarloa, Aitzol Zuloaga, José Ángel Araujo, Jaime Jiménez
2024	—	`conf`	Smart Carrier for Scan Chain Emulation of ASIC Prototypes under Test. DCIS Juan Manuel Galán, Ainhoa Cortés, Andoni Irizar, Alejandro Arteaga, Jose Ignacio Garate, Armando Astarloa
2023	B	`conf`	SiliconBurmuin: A Horizon Europe propelled Neurocomputing Initiative in the Basque Country. SEAA Xabier Iturbe, Xabier Alberdi, Ander Aramburu, Armando Astarloa, Iñigo Barandiaran, Koldo Basterretxea, Angélica Dávila, Asier Erramuzpe, Iñigo Gabilondo, Garikoitz Lerma-Usabiaga, Lisandro Gabriel Monsalve, Libe Mori, Javier Navaridas, Jose Antonio Pascual, Joaquin Piriz, Serafim Rodrigues, Oscar Seijo, Ander Soraluze, Edgar Soria, Ignacio Torres, Nerea Uriarte, Juan Luis Valerdi
2023	—	`conf`	Time-Sensitive Networking to meet Hard-real Time Boundaries on Edge Intelligence Applications. DCIS Armando Astarloa, Pedro Fernández, Jesús Lázaro, Mikel Idirin, Sergio Salas
2022	—	`conf`	Accelerating Video Analytic Processing on Edge Intelligence. DCIS Pedro Fernández, Jaime Jiménez, Armando Astarloa, Mikel Idirin, Sergio Salas
2022	J	`jnl`	Embedded firewall for on-chip bus transactions. Comput. Electr. Eng. Jesús Lázaro, Unai Bidarte, Leire Muguira, Armando Astarloa, Jaime Jiménez
2022	J	`jnl`	High-Performance Computing Architecture for Sample Value Processing in the Smart Grid. IEEE Access Le Sun, Leire Muguira, Jaime Jiménez, Armando Astarloa, Jesús Lázaro
2022	J	`jnl`	IEEE 802.1AS Clock Synchronization Performance Evaluation of an Integrated Wired-Wireless TSN Architecture. IEEE Trans. Ind. Informatics Iñaki Val, Óscar Seijo, Raul Torrego, Armando Astarloa
2022	—	`conf`	Impact of MACsec security on TSN traffic. DCIS Roger Antonio Peña, Mikel Pascual, Armando Astarloa, Daniel Uribe, Jon Inchausti
2021	J	`jnl`	A Fixed-Latency Architecture to Secure GOOSE and Sampled Value Messages in Substation Systems. IEEE Access Mikel Rodriguez, Jesús Lázaro, Unai Bidarte, Jaime Jiménez, Armando Astarloa
2021	J	`jnl`	IEEE 802.1AS Clock Synchronization Performance Evaluation of an Integrated Wired-Wireless TSN Architecture. CoRR Inaki Val, Oscar Seijo, Raul Torrego, Armando Astarloa
2020	—	`conf`	Electronic control board for student Rocket. DCIS Jesús Lázaro, Laura Burgos, Leire Muguira, Armando Astarloa, Jaime Jiménez
2020	—	`conf`	Secure Critical Traffic of the Electric Sector over Time-Sensitive Networking. DCIS Leire Muguira, Jesús Lázaro, Sara Alonso, Armando Astarloa, Mikel Rodriguez
2020	—	`conf`	Synchronizing NTP Referenced SCADA Systems Interconnected by High-availability Networks. DCIS Armando Astarloa, Mikel Rodriguez, Francisco Durán, Jaime Jiménez, Jesús Lázaro
2019	J	`jnl`	Smart Sensor: SoC Architecture for the Industrial Internet of Things. IEEE Internet Things J. Marcelo Urbina, Tatiana Acosta, Jesús Lázaro, Armando Astarloa, Unai Bidarte
2018	—	`conf`	System-on-Programmable-Chip AES-GCM implementation for wire-speed cryptography for SAS. DCIS Mikel Rodriguez, Armando Astarloa, Jesús Lázaro, Unai Bidarte, Jaime Jimenez
2017	J	`jnl`	Cyber-Physical Production System Gateway Based on a Programmable SoC Platform. IEEE Access Marcelo Urbina, Armando Astarloa, Jesús Lázaro, Unai Bidarte, Igor Villalta, Mikel Rodriguez
2017	J	`jnl`	Estimating the SEU failure rate of designs implemented in FPGAs in presence of MCUs. Microelectron. Reliab. Igor Villalta, Unai Bidarte, Julen Gomez-Cornejo, Jesús Lázaro, Armando Astarloa
2017	J	`jnl`	On the Utilization of System-on-Chip Platforms to Achieve Nanosecond Synchronization Accuracies in Substation Automation Systems. IEEE Trans. Smart Grid Naiara Moreira, Jesús Lázaro, Unai Bidarte, Jaime Jimenez, Armando Astarloa
2016	C	`conf`	Intelligent gateway for Industry 4.0-compliant production. IECON Armando Astarloa, Unai Bidarte, Jaime Jimenez, Aitzol Zuloaga, Jesús Lázaro
2016	J	`jnl`	Performance Enhancement of High-Availability Seamless Redundancy (HSR) Networks Using OpenFlow. IEEE Commun. Lett. Elias Molina, Eduardo Jacob, Nerea Toledo, Armando Astarloa
2016	J	`jnl`	Synchronization of faulty processors in coarse-grained TMR protected partially reconfigurable FPGA designs. Reliab. Eng. Syst. Saf. Uli Kretzschmar, Julen Gomez-Cornejo, Armando Astarloa, Unai Bidarte, Javier Del Ser
2016	J	`jnl`	Using OpenFlow to control redundant paths in wireless networks. Netw. Protoc. Algorithms Elias Molina, Eduardo Jacob, Armando Astarloa
2015	—	`conf`	FPGA based nodes for sub-microsecond synchronization of cyber-physical production systems on high availability ring networks. ReConFig Armando Astarloa, Naiara Moreira, Unai Bidarte, Marcelo Urbina, David Modrono
2015	B	`conf`	Managing path diversity in layer 2 critical networks by using OpenFlow. CNSM Elias Molina, Jon Matías, Armando Astarloa, Eduardo Jacob
2015	J	`jnl`	PRP and HSR for High Availability Networks in Power Utility Automation: A Method for Redundant Frames Discarding. IEEE Trans. Smart Grid José Ángel Araujo, Jesús Lázaro, Armando Astarloa, Aitzol Zuloaga, Jose Ignacio Garate
2015	J	`jnl`	Using Software Defined Networking to manage and control IEC 61850-based systems. Comput. Electr. Eng. Elias Molina, Eduardo Jacob, Jon Matías, Naiara Moreira, Armando Astarloa
2014	J	`jnl`	Compact and Fast Fault Injection System for Robustness Measurements on SRAM-Based FPGAs. IEEE Trans. Ind. Electron. Uli Kretzschmar, Armando Astarloa, Jaime Jimenez, Mikel Garay, Javier Del Ser
2014	—	`conf`	Cost-effective redundancy for ethernet train communications using HSR. ISIE Aitzol Zuloaga, Armando Astarloa, Jaime Jimenez, Jesús Lázaro, Jose Angel Araujo
2014	J	`jnl`	FTL-CFree: A Fuzzy Real-Time Language for Runtime Verification. IEEE Trans. Ind. Informatics Joaquín Pérez, Jaime Jimenez, Asier Rabanal, Armando Astarloa, Jesús Lázaro
2014	B	`conf`	Fast and accurate SEU-tolerance characterization method for Zynq SoCs. FPL Igor Villata, Unai Bidarte, Uli Kretzschmar, Armando Astarloa, Jesús Lázaro
2014	—	`conf`	Securing IEEE 1588 messages with message authentication codes based on the KECCAK cryptographic algorithm implemented in FPGAs. ISIE Naiara Moreira, Armando Astarloa, Uli Kretzschmar, Jesús Lázaro, Elias Molina
2013	C	`conf`	Duplicate and circulating frames discard methods for PRP and HSR (IEC62439-3). IECON José Ángel Araujo, Jesús Lázaro, Armando Astarloa, Aitzol Zuloaga, Naiara Moreira
2013	—	`conf`	IEEE 1588 Transparent Clock architecture for FPGA-based network devices. ISIE Naiara Moreira, Armando Astarloa, Jesús Lázaro, Alain García, Enekoitz Ormaetxea
2013	C	`conf`	Memory requirements analysis for PRP and HSR hardware implementations on FPGAs. IECON José Ángel Araujo, Jesús Lázaro, Armando Astarloa, Naiara Moreira, Alain García
2013	C	`conf`	PRP and HSR version 1 (IEC 62439-3 Ed.2), improvements and a prototype implementation. IECON José Ángel Araujo, Jesús Lázaro, Armando Astarloa, Aitzol Zuloaga, Alain García
2013	B	`conf`	SDR control interface: An FPGA based infrastructure for control of VPX Software Defined Radio systems. FPL Stefanie Castillo, Armando Astarloa, Jesús Lázaro, Sergio Salas, Isaac Ballesteros
2013	—	`conf`	SEU Resilience of DES, AES and Twofish in SRAM-Based FPGA. ARC Uli Kretzschmar, Armando Astarloa, Jesús Lázaro
2013	C	`conf`	SHA-3 based Message Authentication Codes to secure IEEE 1588 synchronization systems. IECON Naiara Moreira, Armando Astarloa, Uli Kretzschmar
2013	C	`conf`	System-on-Chip implementation of Reliable Ethernet Networks nodes. IECON Armando Astarloa, Jesús Lázaro, Unai Bidarte, Aitzol Zuloaga, Mikel Idirin
2012	B	`conf`	Fast and accurate Single Bit Error injection into SRAM Based FPGAs. FPL Uli Kretzschmar, Armando Astarloa, Jaime Jimenez, Mikel Garay, Javier Del Ser
2012	—	`conf`	High availability automation networks: PRP and HSR ring implementations. ISIE Jose Angel Araujo, Jesús Lázaro, Armando Astarloa, Aitzol Zuloaga, Alain García
2012	—	`conf`	On the design of an heuristically optimized multiband spectrum sensing approach for cognitive radio systems. CAMAD Javier Del Ser, Asier Alonso, Sergio Gil-Lopez, Mikel Garay, Uli Kretzschmar, Armando Astarloa
2012	—	`conf`	Robustness of different TMR granularities in shared wishbone architectures on SRAM FPGA. ReConFig Uli Kretzschmar, Armando Astarloa, Jesús Lázaro, Mikel Garay, Javier Del Ser
2011	—	`conf`	An automatic experimental set-up for robustness analysis of designs implemented on SRAM FPGAS. SoC Uli Kretzschmar, Armando Astarloa, Jesús Lázaro, Jaime Jimenez, Aitzol Zuloaga
2011	J	`jnl`	I2CSec: A secure serial Chip-to-Chip communication protocol. J. Syst. Archit. Jesús Lázaro, Armando Astarloa, Aitzol Zuloaga, Unai Bidarte, Jaime Jimenez
2011	—	`conf`	NoCmodel: An extensible framework for Network-on-Chips modeling. ReCoSoC Oscar Daniel Diaz, Armando Astarloa, Aitzol Zuloaga, Jesús Lázaro, Jaime Jimenez
2011	—	`conf`	Robustness Analysis of Different AES Implementations on SRAM Based FPGAs. ReConFig Uli Kretzschmar, Armando Astarloa, Jesús Lázaro, Unai Bidarte, Jaime Jimenez
2010	—	`conf`	An Autonomous Fault Tolerant System for CAN Communications. IEA/AIE (3) Armando Astarloa, Jesús Lázaro, Unai Bidarte, Aitzol Zuloaga, José Luis Martín
2010	J	`jnl`	Neuro semantic thresholding using OCR software for high precision OCR applications. Image Vis. Comput. Jesús Lázaro, José Luis Martín, Jagoba Arias, Armando Astarloa, Carlos Cuadrado
2010	J	`jnl`	Reconfigurable Multiprocessor Systems: A Review. Int. J. Reconfigurable Comput. Taho Dorta, Jaime Jimenez, José Luis Martín, Unai Bidarte, Armando Astarloa
2009	B	`conf`	A novel SEU, MBU and SHE handling strategy for Xilinx Virtex-4 FPGAs. FPL Xabier Iturbe, Mikel Azkarate-askasua, Imanol Martinez, Jon Pérez, Armando Astarloa
2009	—	`conf`	AES-Galois Counter Mode Encryption/Decryption FPGA Core for Industrial and Residential Gigabit Ethernet Communications. ARC Jesús Lázaro, Armando Astarloa, Unai Bidarte, Jaime Jimenez, Aitzol Zuloaga
2009	—	`conf`	DNAX-BCU: An Un-clonable Cost-conscious SoPC Implementation for Bus Coupling Units of the European Installation Bus. ICDCS Workshops Armando Astarloa, Jesús Lázaro, Unai Bidarte, Aitzol Zuloaga, Jaime Jimenez
2009	—	`conf`	Overview of FPGA-Based Multiprocessor Systems. ReConFig Taho Dorta, Jaime Jimenez, José Luis Martín, Unai Bidarte, Armando Astarloa
2009	—	`conf`	PCIREX: A Fast Prototyping Platform for TMR Dynamically Reconfigurable Systems. ReConFig Armando Astarloa, Jesús Lázaro, Unai Bidarte, Aitzol Zuloaga, Jaime Jimenez
2008	—	`conf`	Configurable-System-on-Programmable-Chip for Power Electronics Control Applications. ReConFig Armando Astarloa, Unai Bidarte, Jesús Lázaro, Jon Andreu, José Luis Martín
2008	C	`conf`	Secure Ethernet Point-to-Point Links for Autonomous Electronic Ballot Boxes. ATC Armando Astarloa, Unai Bidarte, Jaime Jimenez, Jesús Lázaro, Iñigo Martínez de Alegría
2007	J	`jnl`	Design of a Master Device for the Multifunction Vehicle Bus. IEEE Trans. Veh. Technol. Jaime Jimenez, José Luis Martín, Unai Bidarte, Armando Astarloa, Aitzol Zuloaga
2007	J	`jnl`	GPS-less location algorithm for wireless sensor networks. Comput. Commun. Jagoba Arias, Jesús Lázaro, Aitzol Zuloaga, Jaime Jimenez, Armando Astarloa
2007	J	`jnl`	Hardware architecture for a general regression neural network coprocessor. Neurocomputing Jesús Lázaro, Jagoba Arias, Armando Astarloa, Unai Bidarte, Aitzol Zuloaga
2007	J	`jnl`	Tornado: A self-reconfiguration control system for core-based multiprocessor CSoPCs. J. Syst. Archit. Armando Astarloa, Aitzol Zuloaga, Unai Bidarte, José Luis Martín, Jesús Lázaro, Jaime Jimenez
2006	Misc	`conf`	Adaptation of IEEE 802.1X for Secure Session Establishment Between Ethernet Peers. ICISS Purificación Sáiz, Jon Matías, Eduardo Jacob, Javier Bustamante, Armando Astarloa
2006	—	`conf`	Modifying Slots in Test Vectors to Validate Decoders of a Train Network. ICWMC Jaime Jimenez, Iker Hoyos, Jagoba Arias, Armando Astarloa, José Luis Martín
2005	J	`jnl`	Implementation of a modified Fuzzy C-Means clustering algorithm for real-time applications. Microprocess. Microsystems Jesús Lázaro, Jagoba Arias, José Luis Martín, Carlos Cuadrado, Armando Astarloa
2005	J	`jnl`	Multiprocessor SoPC-Core for FAT volume computation. Microprocess. Microsystems Armando Astarloa, Unai Bidarte, Jesús Lázaro, Aitzol Zuloaga, Jagoba Arias
2004	B	`conf`	A Self-Reconfiguration Framework for Multiprocessor CSoPCs. FPL Armando Astarloa, Jesús Lázaro, Unai Bidarte, José Luis Martín, Aitzol Zuloaga
2004	—	`conf`	Co-simulation Virtual Platform for Reconfigurable Multiprocessor Hybrid Cores Development. MSV/AMCS Armando Astarloa, Jesús Lázaro, Jagoba Arias, Unai Bidarte, Aitzol Zuloaga
2004	B	`conf`	High Throughput Serpent Encryption Implementation. FPL Jesús Lázaro, Armando Astarloa, Jagoba Arias, Unai Bidarte, Carlos Cuadrado
2004	J	`jnl`	Malguki: an RSSI based ad hoc location algorithm. Microprocess. Microsystems Jagoba Arias, Aitzol Zuloaga, Jesús Lázaro, Jon Andreu, Armando Astarloa
2004	B	`conf`	Simulation Platform for Architectural Verification and Performance Analysis in Core-Based SoC Design. FPL Unai Bidarte, Armando Astarloa, José Luis Martín, Jon Andreu
2003	B	`conf`	Core-Based Reusable Architecture for Slave Circuits with Extensive Data Exchange Requirements. FPL Unai Bidarte, Armando Astarloa, Aitzol Zuloaga, Jaime Jimenez, Iñigo Martínez de Alegría