Arkadiy Morgenshtein

21 papers A* 1A 2C 1Journal 7Unranked 10
YearRankTypeTitle / Venue / Authors
2017 J jnl
Test Generation Methods for Utilization Improvement of Hardware-Accelerated Simulation Platforms.
IEEE Des. Test
Wisam Kadry, Dmitry Krestyashyn, Arkadiy Morgenshtein, Amir Nahir, Vitali Sokhin, Jin Sung Park, Sung-Boem Park, Wookyeong Jeong, Jae-Cheol Son
2016 A* conf
Probabilistic bug-masking analysis for post-silicon tests in microprocessor verification.
DAC
Doowon Lee, Tom Kolan, Arkadiy Morgenshtein, Vitali Sokhin, Ronny Morad, Avi Ziv, Valeria Bertacco
2015 A conf
Comparative study of test generation methods for simulation accelerators.
DATE
Wisam Kadry, Dmitry Krestyashyn, Arkadiy Morgenshtein, Amir Nahir, Vitali Sokhin, Jin Sung Park, Sung-Boem Park, Wookyeong Jeong, Jae-Cheol Son
2014 A conf
Effective post-silicon failure localization using dynamic program slicing.
DATE
Ophir Friedler, Wisam Kadry, Arkadiy Morgenshtein, Amir Nahir, Vitali Sokhin
2014 J jnl
Full-Swing Gate Diffusion Input logic - Case-study of low-power CLA adder design.
Integr.
Arkadiy Morgenshtein, Viacheslav Yuzhaninov, Alexey Kovshilovsky, Alexander Fish
2010 J jnl
Corrections to "Unified Logical Effort - A Method for Delay Evaluation and Minimization in Logic Paths With RC Interconnect" [May 10 689-696].
IEEE Trans. Very Large Scale Integr. Syst.
Arkadiy Morgenshtein, Eby G. Friedman, Ran Ginosar, Avinoam Kolodny
2010 J jnl
Unified Logical Effort - A Method for Delay Evaluation and Minimization in Logic Paths With RC Interconnect.
IEEE Trans. Very Large Scale Integr. Syst.
Arkadiy Morgenshtein, Eby G. Friedman, Ran Ginosar, Avinoam Kolodny
2008 — conf
Parallel vs. serial on-chip communication.
SLIP
Rostislav (Reuven) Dobkin, Arkadiy Morgenshtein, Avinoam Kolodny, Ran Ginosar
2008 — conf
Timing optimization in logic with interconnect.
SLIP
Arkadiy Morgenshtein, Eby G. Friedman, Ran Ginosar, Avinoam Kolodny
2006 J jnl
Logic Gates as Repeaters (LGR) for Area-Efficient Timing Optimization.
IEEE Trans. Very Large Scale Integr. Syst.
Michael Moreinis, Arkadiy Morgenshtein, Israel A. Wagner, Avinoam Kolodny
2005 — conf
Low-leakage repeaters for NoC interconnects.
ISCAS (1)
Arkadiy Morgenshtein, Israel Cidon, Ran Ginosar, Avinoam Kolodny
2004 — conf
An efficient implementation of D-Flip-Flop using the GDI technique.
ISCAS (2)
Arkadiy Morgenshtein, Alexander Fish, Israel A. Wagner
2004 J jnl
Asynchronous gate-diffusion-input (GDI) circuits.
IEEE Trans. Very Large Scale Integr. Syst.
Arkadiy Morgenshtein, Michael Moreinis, Ran Ginosar
2004 — conf
Automatic hardware-efficient SoC integration by QoS network on chip.
ICECS
Evgeny Bolotin, Arkadiy Morgenshtein, Israel Cidon, Ran Ginosar, Avinoam Kolodny
2004 — conf
Comparative analysis of serial vs parallel links in NoC.
SoC
Arkadiy Morgenshtein, Israel Cidon, Avinoam Kolodny, Ran Ginosar
2004 — conf
ISFET CMOS compatible design and encapsulation challenges.
ICECS
Liby Sudakov-Boreysha, Arkadiy Morgenshtein, Uri Dinnar, Yael Nemirovsky
2004 — conf
Micro-modem - reliability solution for NoC communications.
ICECS
Arkadiy Morgenshtein, Evgeny Bolotin, Israel Cidon, Avinoam Kolodny, Ran Ginosar
2004 — conf
Repeater insertion combined with LGR methodology for on-chip interconnect timing optimization.
ICECS
Michael Moreinis, Arkadiy Morgenshtein, Israel A. Wagner, Avinoam Kolodny
2003 C conf
Logic Gates as Repeaters (LGR) for Timing Optimization of SoC Interconnects.
VLSI-SOC
Arkadiy Morgenshtein, Michael Moreinis, Israel A. Wagner, Avinoam Kolodny
2002 — conf
Gate-diffusion input (GDI) - a technique for low power design of digital circuits: analysis and characterization.
ISCAS (1)
Arkadiy Morgenshtein, Alexander Fish, Israel A. Wagner
2002 J jnl
Gate-diffusion input (GDI): a power-efficient method for digital combinatorial circuits.
IEEE Trans. Very Large Scale Integr. Syst.
Arkadiy Morgenshtein, Alexander Fish, Israel A. Wagner