Arka Dutta

12 papers Journal 12
YearRankTypeTitle / Venue / Authors
2019 J jnl
Circuit performance analysis of graded doping of channel of DGMOS with high-k gate stack for analogue and digital application.
IET Circuits Devices Syst.
Swarnil Roy, Sagar Mukherjee, Arka Dutta, Chandan Kumar Sarkar, Chayanika Bose
2018 J jnl
Implementation of Low Power Programmable Flash ADC Using IDUDGMOSFET.
IEEE Trans. Circuits Syst. II Express Briefs
Sagar Mukherjee, Arka Dutta, Swarnil Roy, Chandan Kumar Sarkar
2016 J jnl
Impact of temperature on linearity and harmonic distortion characteristics of underlapped FinFET.
Microelectron. Reliab.
Arka Dutta, Kalyan Koley, Samar K. Saha, Chandan Kumar Sarkar
2016 J jnl
Influence of channel length and high-K oxide thickness on subthreshold analog/RF performance of graded channel and gate stack DG-MOSFETs.
Microelectron. Reliab.
Sanjit Kumar Swain, Arka Dutta, Sarosij Adak, Sudhansu Kumar Pati, Chandan Kumar Sarkar
2016 J jnl
Low-power amplitude modulator for wireless application using underlap double-gate metal-oxide-semiconductor field-effect transistor.
IET Circuits Devices Syst.
Sagar Mukherjee, Kalyan Koley, Arka Dutta, Chandan Kumar Sarkar
2016 J jnl
Study on effect of back oxide thickness variation in FDSOI MOSFET on analogue circuit performance.
IET Circuits Devices Syst.
Sagar Mukherjee, Swarnil Roy, Arka Dutta, Chandan Kumar Sarkar
2015 J jnl
Asymmetric Underlap Dual Material Gate DG-FET for Low Power Analog/RF Applications.
J. Low Power Electron.
Atanu Kundu, Arka Dutta, Chandan Kumar Sarkar
2015 J jnl
Impact of lateral straggle on analog and digital circuit performance using independently driven underlap DG-MOSFET.
Microelectron. J.
Sagar Mukherjee, Arka Dutta, Swarnil Roy, Kalyan Koley, Chandan Kumar Sarkar
2014 J jnl
Analysis of Harmonic distortion in asymmetric underlap DG-MOSFET with high-k spacer.
Microelectron. Reliab.
Arka Dutta, Kalyan Koley, Chandan Kumar Sarkar
2014 J jnl
Impact of gate metal work-function engineering for enhancement of subthreshold analog/RF performance of underlap dual material gate DG-FET.
Microelectron. Reliab.
Atanu Kundu, Kalyan Koley, Arka Dutta, Chandan Kumar Sarkar
2014 J jnl
RF parameter extraction of underlap DG MOSFETs: a look up table based approach.
IET Circuits Devices Syst.
Atanu Kundu, Arka Dutta, Kalyan Koley, S. Niyogi, Chandan Kumar Sarkar
2014 J jnl
Study of body and oxide thickness variation on analog and RF performance of underlap DG-MOSFETs.
Microelectron. Reliab.
Sudhansu Kumar Pati, Kalyan Koley, Arka Dutta, N. Mohankumar, Chandan Kumar Sarkar