Aritra Dasgupta

27 papers A 3C 1Misc 4Journal 11Unranked 8

Year	Rank	Type	Title / Venue / Authors
2026	A	`conf`	PROM: Protection against Reverse Engineering Attacks through Programmable Logic Macros. FPGA Pravin Gaikwad, Aritra Dasgupta, Sudipta Paria, Peyman Dehghanzadeh, Jonathan Cruz, Swarup Bhunia
2025	Misc	`conf`	CLIP: A Structural Approach to Cut Points Matching for Logic Equivalence Checking. VTS Dinesh Reddy Ankireddy, Sudipta Paria, Aritra Dasgupta, Sandip Ray, Swarup Bhunia
2025	J	`jnl`	Enhancing Test Efficiency through Automated ATPG-Aware Lightweight Scan Instrumentation. CoRR Sudipta Paria, Md Rezoan Ferdous, Aritra Dasgupta, Atri Chatterjee, Swarup Bhunia
2025	C	`conf`	FV-PAL: Scalable Formal Verification through Partitioning and LLM-Guided Property Generation. ICCD Sudipta Paria, Aritra Dasgupta, Dinesh Reddy Ankireddy, Prabuddha Chakraborty, Swarup Bhunia
2025	J	`jnl`	HIPR: Hardware IP Protection through Low-Overhead Fine-Grain Redaction. IACR Cryptol. ePrint Arch. Aritra Dasgupta, Sudipta Paria, Swarup Bhunia
2025	J	`jnl`	HIPR: Hardware IP Protection through Low-Overhead Fine-Grain Redaction. IACR Trans. Cryptogr. Hardw. Embed. Syst. Aritra Dasgupta, Sudipta Paria, Swarup Bhunia
2025	J	`jnl`	Intelligent Graybox Fuzzing via ATPG-Guided Seed Generation and Submodule Analysis. CoRR Raghul Saravanan, Sudipta Paria, Aritra Dasgupta, Swarup Bhunia, Sai Manoj PD
2025	J	`jnl`	LASA: Enhancing SoC Security Verification with LLM-Aided Property Generation. CoRR Dinesh Reddy Ankireddy, Sudipta Paria, Aritra Dasgupta, Sandip Ray, Swarup Bhunia
2025	—	`conf`	LASSO: LLM-Aided Security Property Generation for Assertion-based SoC Verification. MLCAD Dinesh Reddy Ankireddy, Sudipta Paria, Aritra Dasgupta, Sandip Ray, Swarup Bhunia
2025	J	`jnl`	LATTE: Library Attack for Evaluating Hardware IP Protections Against Reverse Engineering. IEEE Des. Test Aritra Dasgupta, Sudipta Paria, Christopher Sozio, Swarup Bhunia
2025	A	`conf`	LITE: ATPG-Aware Lightweight Scan Instrumentation for Enhancing Test Efficiency. ITC Sudipta Paria, Md Rezoan Ferdous, Aritra Dasgupta, Atri Chatterjee, Swarup Bhunia
2025	J	`jnl`	Library-Attack: Reverse Engineering Approach for Evaluating Hardware IP Protection. CoRR Aritra Dasgupta, Sudipta Paria, Christopher Sozio, Andrew Lukefahr, Swarup Bhunia
2025	A	`conf`	PROFUZZ: Directed Graybox Fuzzing via Module Selection and ATPG-Guided Seed Generation. ICCAD Raghul Saravanan, Sudipta Paria, Aritra Dasgupta, Swarup Bhunia, Sai Manoj P. D.
2025	J	`jnl`	SynFuzz: Leveraging Fuzzing of Netlist to Detect Synthesis Bugs. CoRR Raghul Saravanan, Sudipta Paria, Aritra Dasgupta, Venkat Nitin Patnala, Swarup Bhunia, Sai Manoj PD
2025	Misc	`conf`	Towards Automated Verification of IP and COTS: Leveraging LLMs in Pre- and Post-Silicon Stages. VTS Sudipta Paria, Aritra Dasgupta, Swarup Bhunia
2024	—	`conf`	DiSPEL: A Framework for SoC Security Policy Synthesis and Distributed Enforcement. HOST Sudipta Paria, Aritra Dasgupta, Swarup Bhunia
2024	J	`jnl`	FDPUF: Frequency-Domain PUF for Robust Authentication of Edge Devices. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Shubhra Deb Paul, Aritra Dasgupta, Swarup Bhunia
2024	—	`conf`	IP Security in Structured ASIC: Challenges and Prospects. ISVLSI Rasheed Almawzan, Sudipta Paria, Aritra Dasgupta, Kostas Amberiadis, Swarup Bhunia
2024	—	`conf`	LATENT: Leveraging Automated Test Pattern Generation for Hardware Trojan Detection. ATS Sudipta Paria, Pravin Gaikwad, Aritra Dasgupta, Swarup Bhunia
2024	—	`conf`	LISA: A Multi-Layered Iterative Framework for Hardening Obfuscation with Modular Unit Transformations. ACM Great Lakes Symposium on VLSI Rasheed Almawzan, Atri Chatterjee, Aritra Dasgupta, Swarup Bhunia
2024	—	`conf`	Navigating SoC Security Landscape on LLM-Guided Paths. ACM Great Lakes Symposium on VLSI Sudipta Paria, Aritra Dasgupta, Swarup Bhunia
2024	—	`conf`	Pasteables: A Flexible, Stick-and-Peel Smart Sensing Platform for Edge Applications. ISVLSI Reiner N. Dizon-Paradis, Aritra Dasgupta, Rohan Reddy Kalavakonda, Swarup Bhunia
2024	J	`jnl`	SPELL: An End-to-End Tool Flow for LLM-Guided Secure SoC Design for Embedded Systems. IEEE Embed. Syst. Lett. Sudipta Paria, Aritra Dasgupta, Swarup Bhunia
2024	—	`conf`	Splitting the Secrets: A Cooperative Trust Model for System-on-Chip Designs with Untrusted IPs. ISVLSI Aritra Dasgupta, Sudipta Paria, Prabuddha Chakraborty, Swarup Bhunia
2023	Misc	`conf`	An Exploration of ATPG Methods for Redacted IP and Reconfigurable Hardware. VTS Jackson Fugate, Greg Stitt, Naren Vikram Raj Masna, Aritra Dasgupta, Swarup Bhunia, Nij Dorairaj, David Kehlet
2023	J	`jnl`	DIVAS: An LLM-based End-to-End Framework for SoC Security Analysis and Policy-based Protection. CoRR Sudipta Paria, Aritra Dasgupta, Swarup Bhunia
2022	Misc	`conf`	SEVA: Structural Analysis based Security Evaluation of Sequential Locking. VLSID Abdulrahman Alaql, Aritra Dasgupta, Md. Moshiur Rahman, Swarup Bhunia