Aristides Efthymiou

23 papers A* 1A 2C 5Journal 4Unranked 11
YearRankTypeTitle / Venue / Authors
2025 — conf
Tunable Approximate Booth Multiplier.
ISVLSI
Ioannis Rizos, Georgios Papatheodorou, Aristides Efthymiou
2024 — conf
Deep Learning Based Detection of Anti-Reflective Obstacles in VLC Systems.
ICAIIC
Marina E. Plissiti, Christoforos Papaioannou, Yiorgos Sfikas, Georgios Papatheodorou, Simon-Ilias Poulis, Aristides Efthymiou, Yiorgos Tsiatouhas
2024 — conf
Exploring the Design Space of 32x32 Approximate Reduced Complexity Wallace Multipliers.
MOCAST
Ioannis Rizos, Georgios Papatheodorou, Aristides Efthymiou
2022 — conf
Signal decoding in an NLOS VLC system with the presence of anti-reflective obstacles.
BlackSeaCom
Christoforos Papaioannou, Marina E. Plissiti, Yiorgos Sfikas, Georgios Papatheodorou, Simon-Ilias Poulis, Aristides Efthymiou, Yiorgos Tsiatouhas
2021 — conf
An efficient adaptive thresholding scheme for signal decoding in NLOS VLC systems.
MeditCom
Marina E. Plissiti, Christoforos Papaioannou, Yiorgos Sfikas, Georgios Papatheodorou, Simon-Ilias Poulis, Aristides Efthymiou, Yiorgos Tsiatouhas
2013 — conf
An error tolerant CAM with nand match-line organization.
ACM Great Lakes Symposium on VLSI
Aristides Efthymiou
2010 J jnl
Initialization-Based Test Pattern Generation for Asynchronous Circuits.
IEEE Trans. Very Large Scale Integr. Syst.
Aristides Efthymiou
2010 C conf
Optimising Self-Timed FPGA Circuits.
DSD
Phillip David Ferguson, Aristides Efthymiou, Tughrul Arslan, Danny Hume
2008 C conf
A Partial Scan Based Test Generation for Asynchronous Circuits.
DDECS
Dilip P. Vasudevan, Aristides Efthymiou
2007 C conf
Redundancy and Test-Pattern Generation for Asynchronous Quasi-Delay-Insensitive Combinational Circuits.
DDECS
Aristides Efthymiou
2007 — conf
Synthetic Trace-Driven Simulation of Cache Memory.
AINA Workshops (1)
Rahman Hassan, Antony Harris, Nigel P. Topham, Aristides Efthymiou
2005 — conf
A Low-Power Processor Architecture Optimized forWireless Devices.
ASAP
Aristides Efthymiou, Jim D. Garside, Ioannis Papaefstathiou
2005 C conf
Fast, Parallel Two-Rail Code Checker with Enhanced Testability.
IOLTS
Sotirios Matakias, Y. Tsiatouhas, Themistoklis Haniotakis, Angela Arapoyanni, Aristides Efthymiou
2005 J jnl
Test pattern generation and partial-scan methodology for an asynchronous SoC interconnect.
IEEE Trans. Very Large Scale Integr. Syst.
Aristides Efthymiou, John Bainbridge, Douglas A. Edwards
2004 J jnl
A CAM with mixed serial-parallel comparison for use in low energy caches.
IEEE Trans. Very Large Scale Integr. Syst.
Aristides Efthymiou, Jim D. Garside
2004 — conf
Adding Testability to an Asynchronous Interconnect for GALS SoC.
Asian Test Symposium
Aristides Efthymiou, John Bainbridge, Douglas A. Edwards
2004 — conf
An Asynchronous, Iterative Implementation of the Original Booth Multiplication Algorithm.
ASYNC
Aristides Efthymiou, W. Suntiamorntut, Jim D. Garside, L. E. M. Brackenbury
2004 A conf
Automatic Scan Insertion and Pattern Generation for Asynchronous Circuits.
DATE
Aristides Efthymiou, Christos P. Sotiriou, Douglas A. Edwards
2003 — conf
Adaptive Pipeline Structures fo Speculation Control.
ASYNC
Aristides Efthymiou, Jim D. Garside
2002 C conf
Adaptive Pipeline Depth Control for Processor Power-Management.
ICCD
Aristides Efthymiou, Jim D. Garside
2002 A conf
An adaptive serial-parallel CAM architecture for low-power cache blocks.
ISLPED
Aristides Efthymiou, Jim D. Garside
2001 J jnl
Power Management in the Amulet Microprocessors.
IEEE Des. Test Comput.
Stephen B. Furber, Aristides Efthymiou, Jim D. Garside, David W. Lloyd, Mike J. G. Lewis, Steve Temple
1995 A* conf
Pipelined Memory Shared Buffer for VLSI Switches.
SIGCOMM
Manolis Katevenis, Panagiota Vatsolaki, Aristides Efthymiou