Arish Sateesan

18 papers B 3C 2Journal 8Unranked 5
YearRankTypeTitle / Venue / Authors
2025 — conf
FLARE: An FPGA-Based Universal Large Flow Detection Engine.
ARC
Arish Sateesan, Jo Vliegen, Nele Mentens
2025 J jnl
ITERATOR: Interruptible Remote Attestation Through Cuckoo Filters.
IEEE Internet Things J.
Nicoló Sponziello, Arish Sateesan, Md Masoom Rabbani, Nele Mentens, Nicola Dragoni, Edlira Dushku
2024 J jnl
A Genetic Programming approach for hardware-oriented hash functions for network security applications.
Appl. Soft Comput.
Mujtaba Hassan, Arish Sateesan, Jo Vliegen, Stjepan Picek, Nele Mentens
2024 J jnl
SPArch: A Hardware-oriented Sketch-based Architecture for High-speed Network Flow Measurements.
ACM Trans. Priv. Secur.
Arish Sateesan, Jo Vliegen, Simon Scherrer, Hsu-Chun Hsiao, Adrian Perrig, Nele Mentens
2023 B conf
ALBUS: a Probabilistic Monitoring Algorithm to Counter Burst-Flood Attacks.
SRDS
Simon Scherrer, Jo Vliegen, Arish Sateesan, Hsu-Chun Hsiao, Nele Mentens, Adrian Perrig
2023 J jnl
ALBUS: a Probabilistic Monitoring Algorithm to Counter Burst-Flood Attacks.
CoRR
Simon Scherrer, Jo Vliegen, Arish Sateesan, Hsu-Chun Hsiao, Nele Mentens, Adrian Perrig
2023 — conf
Evolving Non-cryptographic Hash Functions Using Genetic Programming for High-speed Lookups in Network Security Applications.
EvoApplications@EvoStar
Mujtaba Hassan, Arish Sateesan, Jo Vliegen, Stjepan Picek, Nele Mentens
2023 J jnl
Optimized algorithms and architectures for fast non-cryptographic hash functions in hardware.
Microprocess. Microsystems
Arish Sateesan, Jelle Biesmans, Thomas Claesen, Jo Vliegen, Nele Mentens
2022 — conf
An Analysis of the Hardware-Friendliness of AMQ Data Structures for Network Security.
SPACE
Arish Sateesan, Jo Vliegen, Nele Mentens
2022 J jnl
Hardware-oriented optimization of Bloom filter algorithms and architectures for ultra-high-speed lookups in network applications.
Microprocess. Microsystems
Arish Sateesan, Jo Vliegen, Joan Daemen, Nele Mentens
2021 J jnl
A Survey of Algorithmic and Hardware Optimization Techniques for Vision Convolutional Neural Networks on FPGAs.
Neural Process. Lett.
Arish Sateesan, Sharad Sinha, Smitha K. G., A. P. Vinod
2021 B conf
Low-Rate Overuse Flow Tracer (LOFT): An Efficient and Scalable Algorithm for Detecting Overuse Flows.
SRDS
Simon Scherrer, Che-Yu Wu, Yu-Hsi Chiang, Benjamin Rothenberger, Daniele Enrico Asoni, Arish Sateesan, Jo Vliegen, Nele Mentens, Hsu-Chun Hsiao, Adrian Perrig
2021 J jnl
Low-Rate Overuse Flow Tracer (LOFT): An Efficient and Scalable Algorithm for Detecting Overuse Flows.
CoRR
Simon Scherrer, Che-Yu Wu, Yu-Hsi Chiang, Benjamin Rothenberger, Daniele Enrico Asoni, Arish Sateesan, Jo Vliegen, Nele Mentens, Hsu-Chun Hsiao, Adrian Perrig
2021 C conf
Novel Non-cryptographic Hash Functions for Networking and Security Applications on FPGA.
DSD
Thomas Claesen, Arish Sateesan, Jo Vliegen, Nele Mentens
2021 — conf
SoK - Network Intrusion Detection on FPGA.
SPACE
Laurens Le Jeune, Arish Sateesan, Md Masoom Rabbani, Toon Goedemé, Jo Vliegen, Nele Mentens
2021 B conf
Speed Records in Network Flow Measurement on FPGA.
FPL
Arish Sateesan, Jo Vliegen, Simon Scherrer, Hsu-Chun Hsiao, Adrian Perrig, Nele Mentens
2020 — conf
DASH: Design Automation for Synthesis and Hardware Generation for CNN.
FPT
Arish Sateesan, Sharad Sinha, Smitha K. G.
2020 C conf
Novel Bloom filter algorithms and architectures for ultra-high-speed network security applications.
DSD
Arish Sateesan, Jo Vliegen, Joan Daemen, Nele Mentens