Arindam Banerjee

13 papers Misc 1Journal 5Unranked 7
YearRankTypeTitle / Venue / Authors
2020 J jnl
A Novel ALU Circuit based on Reversible Logic.
J. Circuits Syst. Comput.
Arindam Banerjee, Debesh Kumar Das
2019 — conf
Arithmetic Circuits Using Reversible Logic: A Survey Report.
ACSS (1)
Arindam Banerjee, Debesh Kumar Das
2016 J jnl
A New Squarer design with reduced area and delay.
IET Comput. Digit. Tech.
Arindam Banerjee, Debesh Kumar Das
2016 — conf
A new ALU architecture design using reversible logic.
ISED
Arindam Banerjee, Debesh Kumar Das
2016 Misc conf
Squaring in Reversible Logic Using Zero Garbage and Reduced Ancillary Inputs.
VLSID
Arindam Banerjee, Debesh Kumar Das
2015 — conf
Squarer design with reduced area and delay.
VDAT
Arindam Banerjee, Debesh Kumar Das
2015 J jnl
The Design of Reversible Signed Multiplier Using Ancient Indian Mathematics.
J. Low Power Electron.
Arindam Banerjee, Debesh Kumar Das
2014 J jnl
Improved matrix multiplier design for high-speed digital signal processing applications.
IET Circuits Devices Syst.
Prabir Saha, Arindam Banerjee, Partha Bhattacharyya, Anup Dandapat
2014 — conf
Squaring in reversible logic using iterative structure.
EWDTS
Arindam Banerjee, Debesh Kumar Das
2013 — conf
The Design of Reversible Multiplier Using Ancient Indian Mathematics.
ISED
Arindam Banerjee, Debesh Kumar Das
2012 — conf
Design of High Speed Vedic Multiplier for Decimal Number System.
VDAT
Prabir Saha, Arindam Banerjee, Anup Dandapat, Partha Bhattacharyya
2011 J jnl
ASIC design of a high speed low power circuit for factorial calculation using ancient Vedic mathematics.
Microelectron. J.
Prabir Saha, Arindam Banerjee, Anup Dandapat, Partha Bhattacharyya
2011 — conf
Vedic Divider: Novel Architecture (ASIC) for High Speed VLSI Applications.
ISED
Prabir Saha, Arindam Banerjee, Partha Bhattacharyya, Anup Dandapat