Arijit Raychowdhury

305 papers A* 14A 33B 5C 25Misc 5Journal 131Unranked 91

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	3DGauCIM: Accelerating Static/Dynamic 3D Gaussian Splatting via Digital CIM for High Frame Rate Real-Time Edge Rendering. ACM Trans. Design Autom. Electr. Syst. Wei-Hsing Huang, Cheng-Jhih Shih, Jian-Wei Su, Samuel Wade Wang, Vaidehi Garg, Yuyao Kong, Jen-Chun Tien, Nealson Li, Arijit Raychowdhury, Meng-Fan Chang, Yingyan (Celine) Lin, Shimeng Yu
2026	—	`conf`	Compositional AI Beyond LLMs: System Implications of Neuro-Symbolic-Probabilistic Architectures. ASPLOS (1) Zishen Wan, Hanchen Yang, Jiayi Qian, Ritik Raj, Joongun Park, Chenyu Wang, Arijit Raychowdhury, Tushar Krishna
2026	A*	`conf`	REASON: Accelerating Probabilistic Logical Reasoning for Scalable Neuro-Symbolic Intelligence. HPCA Zishen Wan, Che-Kai Liu, Jiayi Qian, Hanchen Yang, Arijit Raychowdhury, Tushar Krishna
2026	J	`jnl`	REASON: Accelerating Probabilistic Logical Reasoning for Scalable Neuro-Symbolic Intelligence. CoRR Zishen Wan, Che-Kai Liu, Jiayi Qian, Hanchen Yang, Arijit Raychowdhury, Tushar Krishna
2026	J	`jnl`	SATA: Sparsity-Aware Scheduling for Selective Token Attention. CoRR Zhenkun Fan, Zishen Wan, Che-Kai Liu, Ashwin Sanjay Lele, Win-San Khwa, Bo Zhang, Meng-Fan Chang, Arijit Raychowdhury
2025	J	`jnl`	3DGauCIM: Accelerating Static/Dynamic 3D Gaussian Splatting via Digital CIM for High Frame Rate Real-Time Edge Rendering. CoRR Wei-Hsing Huang, Cheng-Jhih Shih, Jian-Wei Su, Samuel Wade Wang, Vaidehi Garg, Yuyao Kong, Jen-Chun Tien, Nealson Li, Arijit Raychowdhury, Meng-Fan Chang, Yingyan Lin, Shimeng Yu
2025	J	`jnl`	A 28nm 1.80Mb/mm2 Digital/Analog Hybrid SRAM-CIM Macro Using 2D-Weighted Capacitor Array for Complex Number Mac Operations. CoRR Shota Konno, Che-Kai Liu, Sigang Ryu, Samuel Spetalnick, Arijit Raychowdhury
2025	C	`conf`	A 48V Input Merged Cross-Connected Double Step-Down Converter with Package-Integrated GaN Switches and Silicon Controller IC. ISCAS Hua Chen, Young-Seok Noh, Minxiang Gong, Arijit Raychowdhury
2025	J	`jnl`	A 65-nm Delta-Sigma ADC-Based VDD-Variation-Tolerant Power-Side-Channel-Attack Sensor. IEEE Solid State Circuits Lett. Shota Konno, Zachary J. Ellis, Anupam Golder, Sigang Ryu, Daniel Dinu, Avinash Varna, Sanu Mathew, Arijit Raychowdhury
2025	J	`jnl`	An Edge Accelerator With 5 MB of 0.256-pJ/bit Embedded RRAM and a Localization Solver for Bristle Robot Surveillance. IEEE J. Solid State Circuits Samuel D. Spetalnick, Ashwin Sanjay Lele, Brian Crafton, Muya Chang, Sigang Ryu, Jong-Hyeok Yoon, Zhijian Hao, Azadeh Ansari, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury
2025	C	`conf`	Characterization and Mitigation of ADC Noise by Reference Tuning in RRAM-Based Compute-In-Memory. ISCAS Ying-Hao Wei, Zishen Wan, Brian Crafton, Samuel Spetalnick, Arijit Raychowdhury
2025	J	`jnl`	Characterization and Mitigation of ADC Noise by Reference Tuning in RRAM-Based Compute-In-Memory. CoRR Ying-Hao Wei, Zishen Wan, Brian Crafton, Samuel Spetalnick, Arijit Raychowdhury
2025	A*	`conf`	CogSys: Efficient and Scalable Neurosymbolic Cognition System via Algorithm-Hardware Co-Design. HPCA Zishen Wan, Hanchen Yang, Ritik Raj, Che-Kai Liu, Ananda Samajdar, Arijit Raychowdhury, Tushar Krishna
2025	J	`jnl`	CogSys: Efficient and Scalable Neurosymbolic Cognition System via Algorithm-Hardware Co-Design. CoRR Zishen Wan, Hanchen Yang, Ritik Raj, Che-Kai Liu, Ananda Samajdar, Arijit Raychowdhury, Tushar Krishna
2025	J	`jnl`	Cross-Layer Design of Vector-Symbolic Computing: Bridging Cognition and Brain-Inspired Hardware Acceleration. CoRR Shuting Du, Mohamed Ibrahim, Zishen Wan, Luqi Zheng, Boheng Zhao, Zhenkun Fan, Che-Kai Liu, Tushar Krishna, Arijit Raychowdhury, Haitong Li
2025	—	`conf`	Efficient Processing of Neuro-Symbolic AI: A Tutorial and Cross-Layer Co-Design Case Study. NeuS Zishen Wan, Che-Kai Liu, Hanchen Yang, Ritik Raj, Arijit Raychowdhury, Tushar Krishna
2025	J	`jnl`	FAVbot: An Autonomous Target Tracking Micro-Robot with Frequency Actuation Control. CoRR Zhijian Hao, Ashwin Sanjay Lele, Yan Fang, Arijit Raychowdhury, Azadeh Ansari
2025	B	`conf`	Generative AI in Embodied Systems: System-Level Analysis of Performance, Efficiency and Scalability. ISPASS Zishen Wan, Jiayi Qian, Yuhang Du, Jason Jabbour, Yilun Du, Yang Zhao, Arijit Raychowdhury, Tushar Krishna, Vijay Janapa Reddi
2025	J	`jnl`	Generative AI in Embodied Systems: System-Level Analysis of Performance, Efficiency and Scalability. CoRR Zishen Wan, Jiayi Qian, Yuhang Du, Jason Jabbour, Yilun Du, Yang Katie Zhao, Arijit Raychowdhury, Tushar Krishna, Vijay Janapa Reddi
2025	A	`conf`	HyDra: SOT-CAM Based Vector Symbolic Macro for Hyperdimensional Computing. ICCAD Md Mizanur Rahaman Nayan, Che-Kai Liu, Zishen Wan, Arijit Raychowdhury, Azad J. Naeemi
2025	J	`jnl`	HyDra: SOT-CAM Based Vector Symbolic Macro for Hyperdimensional Computing. CoRR Md Mizanur Rahaman Nayan, Che-Kai Liu, Zishen Wan, Arijit Raychowdhury, Azad J. Naeemi
2025	J	`jnl`	MDS-DOA: Fusing Model-Based and Data-Driven Approaches for Modular, Distributed, and Scalable Direction-of-Arrival Estimation. IEEE Trans. Circuits Syst. I Regul. Pap. Adou Sangbone Assoa, Ashwin Bhat, Sigang Ryu, Arijit Raychowdhury
2025	—	`conf`	MemQuant: Towards Memory-aware Post-Training Quantization for Multimodal Transformers. AICAS Kazi Barria Nine, Foroozan Karimzadeh, Zishen Wan, Arijit Raychowdhury
2025	A*	`conf`	NSFlow: An End-to-End FPGA Framework with Scalable Dataflow Architecture for Neuro-Symbolic AI. DAC Hanchen Yang, Zishen Wan, Ritik Raj, Joongun Park, Ziwei Li, Ananda Samajdar, Arijit Raychowdhury, Tushar Krishna
2025	J	`jnl`	NSFlow: An End-to-End FPGA Framework with Scalable Dataflow Architecture for Neuro-Symbolic AI. CoRR Hanchen Yang, Zishen Wan, Ritik Raj, Joongun Park, Ziwei Li, Ananda Samajdar, Arijit Raychowdhury, Tushar Krishna
2025	C	`conf`	Optimizing Sparse/Dense VEGETA Accelerator Performance with Microscaling Quantization. ISCAS Kazi Barria Nine, Connor Talley, Ajay Sharma Mandadi, Tushar Krishna, Arijit Raychowdhury
2025	—	`conf`	ReCA: Integrated Acceleration for Real-Time and Efficient Cooperative Embodied Autonomous Agents. ASPLOS (2) Zishen Wan, Yuhang Du, Mohamed Ibrahim, Jiayi Qian, Jason Jabbour, Yang Katie Zhao, Tushar Krishna, Arijit Raychowdhury, Vijay Janapa Reddi
2024	—	`conf`	30.1 A 40nm VLIW Edge Accelerator with 5MB of 0.256pJ/b RRAM and a Localization Solver for Bristle Robot Surveillance. ISSCC Samuel D. Spetalnick, Ashwin Sanjay Lele, Brian Crafton, Muya Chang, Sigang Ryu, Jong-Hyeok Yoon, Zhijian Hao, Azadeh Ansari, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury
2024	C	`conf`	A 24/48V to 0.8V-1.2V All-Digital Synchronous Buck Converter with Package-Integrated GaN power FETs and 180nm Silicon Controller IC. ISCAS Kaushik Bhattacharyya, Minxiang Gong, Muya Chang, Xin Zhang, Arijit Raychowdhury
2024	—	`conf`	A 28nm Approximate / Binary 6T CAM for Sequence Alignment. VLSI Technology and Circuits Brian Crafton, Samuel D. Spetalnick, Muya Chang, Arijit Raychowdhury
2024	—	`conf`	A 65nm Delta-Sigma ADC Based VDD-Variation-Tolerant Power-Side-Channel-Attack Monitor with Detection Capability Down to 0.25Ω. VLSI Technology and Circuits Shota Konno, Zachary J. Ellis, Anupam Golder, Sigang Ryu, Daniel Dinu, Avinash Varna, Sanu Mathew, Arijit Raychowdhury
2024	J	`jnl`	A Heterogeneous RRAM In-Memory and SRAM Near-Memory SoC for Fused Frame and Event-Based Target Identification and Tracking. IEEE J. Solid State Circuits Ashwin Sanjay Lele, Muya Chang, Samuel D. Spetalnick, Brian Crafton, Shota Konno, Zishen Wan, Ashwin Bhat, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury
2024	—	`conf`	Accurate Low-Degree Polynomial Approximation of Non-Polynomial Operators for Fast Private Inference in Homomorphic Encryption. MLSys Jingtian Dang, Jianming Tong, Anupam Golder, Cong Hao, Arijit Raychowdhury, Tushar Krishna
2024	J	`jnl`	Accurate Low-Degree Polynomial Approximation of Non-polynomial Operators for Fast Private Inference in Homomorphic Encryption. CoRR Jianming Tong, Jingtian Dang, Anupam Golder, Callie Hao, Arijit Raychowdhury, Tushar Krishna
2024	—	`conf`	Amorphous Oxide Semiconductors for Monolithic 3D Integrated Circuits. VLSI Technology and Circuits Suman Datta, Eknath Sarkar, Khandker Akif Aabrar, Shan Deng, Jaewon Shin, Arijit Raychowdhury, Shimeng Yu, Asif Khan
2024	A	`conf`	Cooling the Chaos: Mitigating the Effect of Threshold Voltage Variation in Cryogenic CMOS Memories. ISLPED Rakshith Saligram, Amol D. Gaidhane, Yu Kevin Cao, Suman Datta, Arijit Raychowdhury
2024	A	`conf`	Cryogenic Operation of Computing-In-Memory based Spiking Neural Network. ISLPED Laith A. Shamieh, Wei-Chun Wang, Shida Zhang, Rakshith Saligram, Amol D. Gaidhane, Yu Cao, Arijit Raychowdhury, Suman Datta, Saibal Mukhopadhyay
2024	J	`jnl`	E-Gaze: Gaze Estimation With Event Camera. IEEE Trans. Pattern Anal. Mach. Intell. Nealson Li, Muya Chang, Arijit Raychowdhury
2024	J	`jnl`	Fractionally-Spaced Equalizers as Clock and Data Recovery Loops. IEEE Trans. Circuits Syst. I Regul. Pap. Sigang Ryu, Jaeha Kim, Arijit Raychowdhury
2024	A	`conf`	H3DFact: Heterogeneous 3D Integrated CIM for Factorization with Holographic Perceptual Representations. DATE Zishen Wan, Che-Kai Liu, Mohamed Ibrahim, Hanchen Yang, Samuel Spetalnick, Tushar Krishna, Arijit Raychowdhury
2024	J	`jnl`	H3DFact: Heterogeneous 3D Integrated CIM for Factorization with Holographic Perceptual Representations. CoRR Zishen Wan, Che-Kai Liu, Mohamed Ibrahim, Hanchen Yang, Samuel Spetalnick, Tushar Krishna, Arijit Raychowdhury
2024	—	`conf`	MulBERRY: Enabling Bit-Error Robustness for Energy-Efficient Multi-Agent Autonomous Systems. ASPLOS (2) Zishen Wan, Nandhini Chandramoorthy, Karthik Swaminathan, Pin-Yu Chen, Kshitij Bhardwaj, Vijay Janapa Reddi, Arijit Raychowdhury
2024	J	`jnl`	Silent Data Corruption in Robot Operating System: A Case for End-to-End System-Level Fault Analysis Using Autonomous UAVs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yu-Shun Hsiao, Zishen Wan, Tianyu Jia, Radhika Ghosal, Abdulrahman Mahmoud, Arijit Raychowdhury, David Brooks, Gu-Yeon Wei, Vijay Janapa Reddi
2024	Misc	`conf`	Special Session: Neuro-Symbolic Architecture Meets Large Language Models: A Memory-Centric Perspective. CODES+ISSS Mohamed Ibrahim, Zishen Wan, Haitong Li, Priyadarshini Panda, Tushar Krishna, Pentti Kanerva, Yiran Chen, Arijit Raychowdhury
2024	J	`jnl`	The Vulnerability-Adaptive Protection Paradigm. Commun. ACM Zishen Wan, Yiming Gan, Bo Yu, Shaoshan Liu, Arijit Raychowdhury, Yuhao Zhu
2024	A	`conf`	Thinking and Moving: An Efficient Computing Approach for Integrated Task and Motion Planning in Cooperative Embodied AI Systems. ICCAD Zishen Wan, Yuhang Du, Mohamed Ibrahim, Yang Katie Zhao, Tushar Krishna, Arijit Raychowdhury
2024	B	`conf`	Towards Cognitive AI Systems: Workload and Characterization of Neuro-Symbolic AI. ISPASS Zishen Wan, Che-Kai Liu, Hanchen Yang, Ritik Raj, Chaojian Li, Haoran You, Yonggan Fu, Cheng Wan, Ananda Samajdar, Yingyan Celine Lin, Tushar Krishna, Arijit Raychowdhury
2024	J	`jnl`	Towards Cognitive AI Systems: a Survey and Prospective on Neuro-Symbolic AI. CoRR Zishen Wan, Che-Kai Liu, Hanchen Yang, Chaojian Li, Haoran You, Yonggan Fu, Cheng Wan, Tushar Krishna, Yingyan Lin, Arijit Raychowdhury
2024	J	`jnl`	Towards Efficient Neuro-Symbolic AI: From Workload Characterization to Hardware Architecture. CoRR Zishen Wan, Che-Kai Liu, Hanchen Yang, Ritik Raj, Chaojian Li, Haoran You, Yonggan Fu, Cheng Wan, Sixu Li, Youbin Kim, Ananda Samajdar, Yingyan Celine Lin, Mohamed Ibrahim, Jan M. Rabaey, Tushar Krishna, Arijit Raychowdhury
2024	J	`jnl`	Towards Efficient Neuro-Symbolic AI: From Workload Characterization to Hardware Architecture. IEEE Trans. Circuits Syst. Artif. Intell. Zishen Wan, Che-Kai Liu, Hanchen Yang, Ritik Raj, Chaojian Li, Haoran You, Yonggan Fu, Cheng Wan, Sixu Li, Youbin Kim, Ananda Samajdar, Yingyan Lin, Mohamed Ibrahim, Jan M. Rabaey, Tushar Krishna, Arijit Raychowdhury
2024	J	`jnl`	Twofold Sparsity: Joint Bit- and Network-Level Sparsity for Energy-Efficient Deep Neural Network Using RRAM Based Compute-In-Memory. IEEE Access Foroozan Karimzadeh, Arijit Raychowdhury
2024	J	`jnl`	VAP: The Vulnerability-Adaptive Protection Paradigm Toward Reliable Autonomous Machines. CoRR Zishen Wan, Yiming Gan, Bo Yu, Shaoshan Liu, Arijit Raychowdhury, Yuhao Zhu
2023	—	`conf`	A 2.38 MCells/mm VLSI Technology and Circuits Samuel D. Spetalnick, Muya Chang, Shota Konno, Brian Crafton, Ashwin Sanjay Lele, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury
2023	—	`conf`	A 65 nm 1.4-6.7 TOPS/W Adaptive-SNR Sparsity-Aware CIM Core with Load Balancing Support for DL workloads. CICC Mustafa Fayez Ali, Indranil Chakraborty, Sakshi Choudhary, Muya Chang, Dong Eun Kim, Arijit Raychowdhury, Kaushik Roy
2023	—	`conf`	A 65nm 60mW Dual-Loop Adaptive Digital Beamformer with Optimized Sidelobe Cancellation and On-Chip DOA Estimation for mm-Wave Applications. VLSI Technology and Circuits Sigang Ryu, Adou Sangbone Assoa, Shota Konno, Arijit Raychowdhury
2023	—	`conf`	A 73.53TOPS/W 14.74TOPS Heterogeneous RRAM In-Memory and SRAM Near-Memory SoC for Hybrid Frame and Event-Based Target Tracking. ISSCC Muya Chang, Ashwin Sanjay Lele, Samuel D. Spetalnick, Brian Crafton, Shota Konno, Zishen Wan, Ashwin Bhat, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury
2023	J	`jnl`	A 90.4% Peak Efficiency 48-to-1-V GaN/Si Hybrid Converter With Three-Level Hybrid Dickson Topology and Gradient Descent Run-Time Optimizer. IEEE J. Solid State Circuits Minxiang Gong, Hua Chen, Xin Zhang, Rinkle Jain, Arijit Raychowdhury
2023	—	`conf`	A Scalable Platform for Single-Snapshot Direction Of Arrival (DOA) Estimation in Massive MIMO Systems. ACM Great Lakes Symposium on VLSI Adou Sangbone Assoa, Ashwin Bhat, Sigang Ryu, Arijit Raychowdhury
2023	A*	`conf`	BERRY: Bit Error Robustness for Energy-Efficient Reinforcement Learning-Based Autonomous Systems. DAC Zishen Wan, Nandhini Chandramoorthy, Karthik Swaminathan, Pin-Yu Chen, Vijay Janapa Reddi, Arijit Raychowdhury
2023	J	`jnl`	BERRY: Bit Error Robustness for Energy-Efficient Reinforcement Learning-Based Autonomous Systems. CoRR Zishen Wan, Nandhini Chandramoorthy, Karthik Swaminathan, Pin-Yu Chen, Vijay Janapa Reddi, Arijit Raychowdhury
2023	A	`conf`	Cryogenic CMOS as an Enabler for Low Power Dynamic Logic. ISLPED Rakshith Saligram, Suman Datta, Arijit Raychowdhury
2023	—	`conf`	E-Track: Eye Tracking with Event Camera for Extended Reality (XR) Applications. AICAS Nealson Li, Ashwin Bhat, Arijit Raychowdhury
2023	—	`conf`	Explainable ECG Beat Classification On The Edge for Smart, Trustworthy and Low-Power Wearables. BioCAS Ashwin Bhat, Arijit Raychowdhury
2023	J	`jnl`	Guest Editorial Introduction to the Special Issue on the 2022 IEEE International Solid-State Circuits Conference (ISSCC). IEEE J. Solid State Circuits Masum Hossain, Arijit Raychowdhury, Sanu K. Mathew, Yakun Sophia Shao, Yih Wang
2023	C	`conf`	Live Demonstration: Hybrid RRAM and SRAM SoC for Fused Frame and Event Target Tracking. ISCAS Ashwin Sanjay Lele, Muya Chang, Samuel Spetalnick, Yan Fang, Brian Crafton, Shota Konno, Arijit Raychowdhury
2023	A	`conf`	MAVFI: An End-to-End Fault Analysis Framework with Anomaly Detection and Recovery for Micro Aerial Vehicles. DATE Yu-Shun Hsiao, Zishen Wan, Tianyu Jia, Radhika Ghosal, Abdulrahman Mahmoud, Arijit Raychowdhury, David Brooks, Gu-Yeon Wei, Vijay Janapa Reddi
2023	A*	`conf`	Neuromorphic Swarm on RRAM Compute-in-Memory Processor for Solving QUBO Problem. DAC Ashwin Sanjay Lele, Muya Chang, Samuel D. Spetalnick, Brian Crafton, Arijit Raychowdhury, Yan Fang
2023	C	`conf`	Non-Uniform Interpolation in Integrated Gradients for Low-Latency Explainable-AI. ISCAS Ashwin Bhat, Arijit Raychowdhury
2023	J	`jnl`	Non-Uniform Interpolation in Integrated Gradients for Low-Latency Explainable-AI. CoRR Ashwin Bhat, Arijit Raychowdhury
2023	—	`conf`	PCB Identification Based on Machine Learning Utilizing Power Consumption Variability. AICAS Anupam Golder, Arijit Raychowdhury
2023	—	`conf`	RAGA: Resource-Aware Tree-Splitting for High Performance Knuth-Yao-based Discrete Gaussian Sampling on FPGAs. ACM Great Lakes Symposium on VLSI Zachary J. Ellis, Anupam Golder, Addison J. Elliott, Arijit Raychowdhury
2023	A	`conf`	Real-Time Fully Unsupervised Domain Adaptation for Lane Detection in Autonomous Driving. DATE Kshitij Bhardwaj, Zishen Wan, Arijit Raychowdhury, Ryan A. Goldhahn
2023	J	`jnl`	Real-Time Fully Unsupervised Domain Adaptation for Lane Detection in Autonomous Driving. CoRR Kshitij Bhardwaj, Zishen Wan, Arijit Raychowdhury, Ryan A. Goldhahn
2023	—	`conf`	Reducing Overhead of Feature Importance Visualization via Static GradCAM Computation. AICAS Ashwin Bhat, Arijit Raychowdhury
2022	J	`jnl`	A 40-nm 118.44-TOPS/W Voltage-Sensing Compute-in-Memory RRAM Macro With Write Verification and Multi-Bit Encoding. IEEE J. Solid State Circuits Jong-Hyeok Yoon, Muya Chang, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury
2022	J	`jnl`	A 40-nm, 64-Kb, 56.67 TOPS/W Voltage-Sensing Computing-In-Memory/Digital RRAM Macro Supporting Iterative Write With Verification and Online Read-Disturb Detection. IEEE J. Solid State Circuits Jong-Hyeok Yoon, Muya Chang, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury
2022	—	`conf`	A 40nm 60.64TOPS/W ECC-Capable Compute-in-Memory/Digital 2.25MB/768KB RRAM/SRAM System with Embedded Cortex M3 Microprocessor for Edge Recommendation Systems. ISSCC Muya Chang, Samuel D. Spetalnick, Brian Crafton, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury
2022	—	`conf`	A 40nm 64kb 26.56TOPS/W 2.37Mb/mm ISSCC Samuel D. Spetalnick, Muya Chang, Brian Crafton, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury
2022	J	`jnl`	A 65 nm Wireless Image SoC Supporting On-Chip DNN Optimization and Real-Time Computation-Communication Trade-Off via Actor-Critical Neuro-Controller. IEEE J. Solid State Circuits Ningyuan Cao, Baibhab Chatterjee, Jianbo Liu, Boyang Cheng, Minxiang Gong, Muya Chang, Shreyas Sen, Arijit Raychowdhury
2022	—	`conf`	A 90.4% Peak Efficiency 48V/1V Three-Level Hybrid Dickson Converter with Gradient Descent Run-Time Optimizer and GaN/Si Hybrid Conversion. VLSI Technology and Circuits Minxiang Gong, Xin Zhang, Arijit Raychowdhury
2022	J	`jnl`	A Practical Design-Space Analysis of Compute-in-Memory With SRAM. IEEE Trans. Circuits Syst. I Regul. Pap. Samuel Spetalnick, Arijit Raychowdhury
2022	J	`jnl`	A low power and PVT variation tolerant mux-latch for serializer interface and on-chip serial link. Integr. Mithilesh Kumar, Alak Majumder, Abir J. Mondal, Arijit Raychowdhury, Bidyut K. Bhattacharyya
2022	—	`conf`	An Analog Clock-free Compute Fabric base on Continuous-Time Dynamical System for Solving Combinatorial Optimization Problems. CICC Muya Chang, Xunzhao Yin, Zoltán Toroczkai, Xiaobo Hu, Arijit Raychowdhury
2022	J	`jnl`	An End-to-End Spiking Neural Network Platform for Edge Robotics: From Event-Cameras to Central Pattern Generation. IEEE Trans. Cogn. Dev. Syst. Ashwin Sanjay Lele, Yan Fang, Justin Ting, Arijit Raychowdhury
2022	—	`conf`	An Energy-Efficient and Runtime-Reconfigurable FPGA-Based Accelerator for Robotic Localization Systems. CICC Qiang Liu, Zishen Wan, Bo Yu, Weizhuang Liu, Shaoshan Liu, Arijit Raychowdhury
2022	J	`jnl`	An Energy-Efficient and Runtime-Reconfigurable FPGA-Based Accelerator for Robotic Localization Systems. CoRR Qiang Liu, Zishen Wan, Bo Yu, Weizhuang Liu, Shaoshan Liu, Arijit Raychowdhury
2022	A	`conf`	Analyzing and Improving Resilience and Robustness of Autonomous Systems. ICCAD Zishen Wan, Karthik Swaminathan, Pin-Yu Chen, Nandhini Chandramoorthy, Arijit Raychowdhury
2022	J	`jnl`	BitS-Net: Bit-Sparse Deep Neural Network for Energy-Efficient RRAM-Based Compute-In-Memory. IEEE Trans. Circuits Syst. I Regul. Pap. Foroozan Karimzadeh, Jong-Hyeok Yoon, Arijit Raychowdhury
2022	C	`conf`	Characterization and Mitigation of IR-Drop in RRAM-based Compute In-Memory. ISCAS Brian Crafton, Connor Talley, Samuel Spetalnick, Jong-Hyeok Yoon, Arijit Raychowdhury
2022	J	`jnl`	Circuit and System Technologies for Energy-Efficient Edge Robotics. CoRR Zishen Wan, Ashwin Sanjay Lele, Arijit Raychowdhury
2022	—	`conf`	Circuit and System Technologies for Energy-Efficient Edge Robotics: (Invited Paper). ASP-DAC Zishen Wan, Ashwin Sanjay Lele, Arijit Raychowdhury
2022	J	`jnl`	Design Space Exploration of Interconnect Materials for Cryogenic Operation: Electrical and Thermal Analyses. IEEE Trans. Circuits Syst. I Regul. Pap. Rakshith Saligram, Suman Datta, Arijit Raychowdhury
2022	J	`jnl`	EM-X-DL: Efficient Cross-device Deep Learning Side-channel Attack With Noisy EM Signatures. ACM J. Emerg. Technol. Comput. Syst. Josef Danial, Debayan Das, Anupam Golder, Santosh Ghosh, Arijit Raychowdhury, Shreyas Sen
2022	—	`conf`	Exploration into the Explainability of Neural Network Models for Power Side-Channel Analysis. ACM Great Lakes Symposium on VLSI Anupam Golder, Ashwin Bhat, Arijit Raychowdhury
2022	A	`conf`	FRL-FI: Transient Fault Analysis for Federated Reinforcement Learning-Based Navigation Systems. DATE Zishen Wan, Aqeel Anwar, Abdulrahman Mahmoud, Tianyu Jia, Yu-Shun Hsiao, Vijay Janapa Reddi, Arijit Raychowdhury
2022	J	`jnl`	FRL-FI: Transient Fault Analysis for Federated Reinforcement Learning-Based Navigation Systems. CoRR Zishen Wan, Aqeel Anwar, Abdulrahman Mahmoud, Tianyu Jia, Yu-Shun Hsiao, Vijay Janapa Reddi, Arijit Raychowdhury
2022	C	`conf`	Fusing Frame and Event Vision for High-speed Optical Flow for Edge Application. ISCAS Ashwin Sanjay Lele, Arijit Raychowdhury
2022	J	`jnl`	Fusing Frame and Event Vision for High-speed Optical Flow for Edge Application. CoRR Ashwin Sanjay Lele, Arijit Raychowdhury
2022	C	`conf`	Gradient Backpropagation based Feature Attribution to Enable Explainable-AI on the Edge. VLSI-SoC Ashwin Bhat, Adou Sangbone Assoa, Arijit Raychowdhury
2022	J	`jnl`	Gradient Backpropagation based Feature Attribution to Enable Explainable-AI on the Edge. CoRR Ashwin Bhat, Adou Sangbone Assoa, Arijit Raychowdhury
2022	A*	`conf`	Improving compute in-memory ECC reliability with successive correction. DAC Brian Crafton, Zishen Wan, Samuel Spetalnick, Jong-Hyeok Yoon, Wei Wu, Carlos Tokunaga, Vivek De, Arijit Raychowdhury
2022	—	`conf`	Multi-bit per-cell 1T SiGe Floating Body RAM for Cache Memory in Cryogenic Computing. VLSI Technology and Circuits Wriddhi Chakraborty, P. Shrestha, A. Gupta, Rakshith Saligram, Samuel Spetalnick, J. Campbell, Arijit Raychowdhury, Suman Datta
2022	A*	`conf`	RAPID-RL: A Reconfigurable Architecture with Preemptive-Exits for Efficient Deep-Reinforcement Learning. ICRA Adarsh Kumar Kosta, Malik Aqeel Anwar, Priyadarshini Panda, Arijit Raychowdhury, Kaushik Roy
2022	—	`conf`	Robotic Computing on FPGAs: Current Progress, Research Challenges, and Opportunities. AICAS Zishen Wan, Ashwin Sanjay Lele, Bo Yu, Shaoshan Liu, Yu Wang, Vijay Janapa Reddi, Cong Hao, Arijit Raychowdhury
2022	J	`jnl`	Robotic Computing on FPGAs: Current Progress, Research Challenges, and Opportunities. CoRR Zishen Wan, Ashwin Sanjay Lele, Bo Yu, Shaoshan Liu, Yu Wang, Vijay Janapa Reddi, Cong Hao, Arijit Raychowdhury
2022	C	`conf`	Towards CIM-friendly and Energy-Efficient DNN Accelerator via Bit-level Sparsity. VLSI-SoC Foroozan Karimzadeh, Arijit Raychowdhury
2022	C	`conf`	Towards Energy Efficient DNN accelerator via Sparsified Gradual Knowledge Distillation. VLSI-SoC Foroozan Karimzadeh, Arijit Raychowdhury
2021	—	`conf`	29.1 A 40nm 64Kb 56.67TOPS/W Read-Disturb-Tolerant Compute-in-Memory/Digital RRAM Macro with Active-Feedback-Based Read and In-Situ Write Verification. ISSCC Jong-Hyeok Yoon, Muya Chang, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury
2021	—	`conf`	A 40nm 100Kb 118.44TOPS/W Ternary-weight Computein-Memory RRAM Macro with Voltage-sensing Read and Write Verification for reliable multi-bit RRAM operation. CICC Jong-Hyeok Yoon, Muya Chang, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury
2021	—	`conf`	A 64-Bit Arm CPU at Cryogenic temperatures: Design Technology Co-Optimization for Power and Performance. CICC Rakshith Saligram, Divya Prasad, David Pietromonaco, Arijit Raychowdhury, Brian Cline
2021	J	`jnl`	A 65nm Thermometer-Encoded Time/Charge-Based Compute-in-Memory Neural Network Accelerator at 0.735pJ/MAC and 0.41pJ/Update. IEEE Trans. Circuits Syst. II Express Briefs Minxiang Gong, Ningyuan Cao, Muya Chang, Arijit Raychowdhury
2021	J	`jnl`	A Hardware-Friendly Approach Towards Sparse Neural Networks Based on LFSR-Generated Pseudo-Random Sequences. IEEE Trans. Circuits Syst. I Regul. Pap. Foroozan Karimzadeh, Ningyuan Cao, Brian Crafton, Justin Romberg, Arijit Raychowdhury
2021	A	`conf`	A decentralized policy gradient approach to multi-task reinforcement learning. UAI Sihan Zeng, Malik Aqeel Anwar, Thinh T. Doan, Arijit Raychowdhury, Justin Romberg
2021	—	`conf`	An Energy-Efficient Quad-Camera Visual System for Autonomous Machines on FPGA Platform. AICAS Zishen Wan, Yuyang Zhang, Arijit Raychowdhury, Bo Yu, Yanjun Zhang, Shaoshan Liu
2021	J	`jnl`	An Energy-Efficient Quad-Camera Visual System for Autonomous Machines on FPGA Platform. CoRR Zishen Wan, Yuyang Zhang, Arijit Raychowdhury, Bo Yu, Yanjun Zhang, Shaoshan Liu
2021	A*	`conf`	Analyzing and Improving Fault Tolerance of Learning-Based Navigation Systems. DAC Zishen Wan, Aqeel Anwar, Yu-Shun Hsiao, Tianyu Jia, Vijay Janapa Reddi, Arijit Raychowdhury
2021	J	`jnl`	Analyzing and Improving Fault Tolerance of Learning-Based Navigation Systems. CoRR Zishen Wan, Aqeel Anwar, Yu-Shun Hsiao, Tianyu Jia, Vijay Janapa Reddi, Arijit Raychowdhury
2021	—	`conf`	Automatic Generation of Translators for Packet-Based and Emerging Protocols. ISQED Brian Crafton, Arijit Raychowdhury, Sung Kyu Lim
2021	—	`conf`	CIM-SECDED: A 40nm 64Kb Compute In-Memory RRAM Macro with ECC Enabling Reliable Operation. A-SSCC Brian Crafton, Samuel Spetalnick, Jong-Hyeok Yoon, Wei Wu, Carlos Tokunaga, Vivek De, Arijit Raychowdhury
2021	—	`conf`	CryoMem: A 4K-300K 1.3GHz eDRAM Macro with Hybrid 2T-Gain-Cell in a 28nm Logic Process for Cryogenic Applications. CICC Rakshith Saligram, Suman Datta, Arijit Raychowdhury
2021	J	`jnl`	EM and Power SCA-Resilient AES-256 Through >350× Current-Domain Signature Attenuation and Local Lower Metal Routing. IEEE J. Solid State Circuits Debayan Das, Josef Danial, Anupam Golder, Nirmoy Modak, Shovan Maity, Baibhab Chatterjee, Dong-Hyun Seo, Muya Chang, Avinash Varna, Harish K. Krishnamurthy, Sanu Mathew, Santosh Ghosh, Arijit Raychowdhury, Shreyas Sen
2021	J	`jnl`	EM/Power Side-Channel Attack: White-Box Modeling and Signature Attenuation Countermeasures. IEEE Des. Test Debayan Das, Santosh Ghosh, Arijit Raychowdhury, Shreyas Sen
2021	—	`conf`	F3: Silicon Technologies in the Fight Against Pandemics - From Point of Care to Computational Epidemiology. ISSCC Nick Van Helleputte, Arijit Raychowdhury, Ping-Hsuan Hsieh, Jun Deguchi, Matteo Perenzoni, Esther Rodríguez-Villegas, Long Yan, Andreia Cathelin, Keith A. Bowman, Chris Van Hoof
2021	—	`conf`	F4: Electronics for a Quantum World. ISSCC Edoardo Charbon, Alicia Klinefelter, Massimo Alioto, Yao-Hong Liu, Munehiko Nagatani, Arijit Raychowdhury, Andreia Cathelin, Boris Murmann
2021	—	`conf`	Hardware-Algorithm Co-Design Enabling Efficient Event-based Object Detection. AICAS Brian Crafton, Andrew Paredes, Evan Gebhardt, Arijit Raychowdhury
2021	J	`jnl`	MAVFI: An End-to-End Fault Analysis Framework with Anomaly Detection and Recovery for Micro Aerial Vehicles. CoRR Yu-Shun Hsiao, Zishen Wan, Tianyu Jia, Radhika Ghosal, Arijit Raychowdhury, David Brooks, Gu-Yeon Wei, Vijay Janapa Reddi
2021	—	`conf`	Merged Logic and Memory Fabrics for AI Workloads. ASP-DAC Brian Crafton, Samuel Spetalnick, Arijit Raychowdhury
2021	J	`jnl`	Merged Logic and Memory Fabrics for Accelerating Machine Learning Workloads. IEEE Des. Test Brian Crafton, Samuel Spetalnick, Yan Fang, Arijit Raychowdhury
2021	J	`jnl`	Multi-Task Federated Reinforcement Learning with Adversaries. CoRR Aqeel Anwar, Arijit Raychowdhury
2021	J	`jnl`	NeuroSLAM: A 65-nm 7.25-to-8.79-TOPS/W Mixed-Signal Oscillator-Based SLAM Accelerator for Edge Robotics. IEEE J. Solid State Circuits Jong-Hyeok Yoon, Arijit Raychowdhury
2021	J	`jnl`	RAPID-RL: A Reconfigurable Architecture with Preemptive-Exits for Efficient Deep-Reinforcement Learning. CoRR Adarsh Kumar Kosta, Malik Aqeel Anwar, Priyadarshini Panda, Arijit Raychowdhury, Kaushik Roy
2021	—	`conf`	Session 35 Overview: Adaptive Digital Techniques for Variation Tolerant Systems Digital Circuits Subcommittee. ISSCC Arijit Raychowdhury, Mijung Noh, Keith A. Bowman
2021	A	`conf`	Statistical Optimization of Compute In-Memory Performance Under Device Variation. ISLPED Brian Crafton, Samuel Spetalnick, Jong-Hyeok Yoon, Arijit Raychowdhury
2021	—	`conf`	iELAS: An ELAS-Based Energy-Efficient Accelerator for Real-Time Stereo Matching on FPGA Platform. AICAS Tian Gao, Zishen Wan, Yuyang Zhang, Bo Yu, Yanjun Zhang, Shaoshan Liu, Arijit Raychowdhury
2021	J	`jnl`	iELAS: An ELAS-Based Energy-Efficient Accelerator for Real-Time Stereo Matching on FPGA Platform. CoRR Tian Gao, Zishen Wan, Yuyang Zhang, Bo Yu, Yanjun Zhang, Shaoshan Liu, Arijit Raychowdhury
2020	J	`jnl`	120.147 Efficient Electromagnetic Side Channel Analysis by Probe Positioning using Multi-Layer Perceptron. IACR Cryptol. ePrint Arch. Anupam Golder, Baogeng Ma, Debayan Das, Josef Danial, Shreyas Sen, Arijit Raychowdhury
2020	—	`conf`	27.3 EM and Power SCA-Resilient AES-256 in 65nm CMOS Through >350× Current-Domain Signature Attenuation. ISSCC Debayan Das, Josef Danial, Anupam Golder, Nirmoy Modak, Shovan Maity, Baibhab Chatterjee, Dong-Hyun Seo, Muya Chang, Avinash Varna, Harish Krishnamurthy, Sanu Mathew, Santosh Ghosh, Arijit Raychowdhury, Shreyas Sen
2020	—	`conf`	31.1 A 65nm 8.79TOPS/W 23.82mW Mixed-Signal Oscillator-Based NeuroSLAM Accelerator for Applications in Edge Robotics. ISSCC Jong-Hyeok Yoon, Arijit Raychowdhury
2020	J	`jnl`	A 65-nm 8-to-3-b 1.0-0.36-V 9.1-1.1-TOPS/W Hybrid-Digital-Mixed-Signal Computing Platform for Accelerating Swarm Robotics. IEEE J. Solid State Circuits Ningyuan Cao, Muya Chang, Arijit Raychowdhury
2020	—	`conf`	A 65nm Image Processing SoC Supporting Multiple DNN Models and Real-Time Computation-Communication Trade-Off Via Actor-Critical Neuro-Controller. VLSI Circuits Ningyuan Cao, Baibhab Chatterjee, Minxiang Gong, Muya Chang, Shreyas Sen, Arijit Raychowdhury
2020	J	`jnl`	A Decentralized Policy Gradient Approach to Multi-task Reinforcement Learning. CoRR Sihan Zeng, Aqeel Anwar, Thinh T. Doan, Justin Romberg, Arijit Raychowdhury
2020	C	`conf`	A Model Study of Multilevel Signaling for High-Speed Chiplet-to-Chiplet Communication in 2.5D Integration. VLSI-SOC Rakshith Saligram, Ankit Kaul, Muhannad S. Bakir, Arijit Raychowdhury
2020	C	`conf`	A Quad-Output Elastic Switched Capacitor Converter and Per-Core LDO with 87% Power Efficiency and 2.5× Core-Frequency Range Improvement. ISCAS Samantak Gangopadhyay, James W. Tschanz, Arijit Raychowdhury
2020	J	`jnl`	A Survey of FPGA-Based Robotic Computing. CoRR Zishen Wan, Bo Yu, Thomas Yuang Li, Jie Tang, Yuhao Zhu, Yu Wang, Arijit Raychowdhury, Shaoshan Liu
2020	J	`jnl`	Autonomous Navigation via Deep Reinforcement Learning for Resource Constraint Edge Nodes Using Transfer Learning. IEEE Access Aqeel Anwar, Arijit Raychowdhury
2020	B	`conf`	Bio-inspired Gait Imitation of Hexapod Robot Using Event-Based Vision Sensor and Spiking Neural Network. IJCNN Justin Ting, Yan Fang, Ashwin Sanjay Lele, Arijit Raychowdhury
2020	J	`jnl`	Bio-inspired Gait Imitation of Hexapod Robot Using Event-Based Vision Sensor and Spiking Neural Network. CoRR Justin Ting, Yan Fang, Ashwin Sanjay Lele, Arijit Raychowdhury
2020	J	`jnl`	Breaking Barriers: Maximizing Array Utilization for Compute In-Memory Fabrics. CoRR Brian Crafton, Samuel Spetalnick, Gauthaman Murali, Tushar Krishna, Sung Kyu Lim, Arijit Raychowdhury
2020	C	`conf`	Breaking Barriers: Maximizing Array Utilization for Compute in-Memory Fabrics. VLSI-SOC Brian Crafton, Samuel Spetalnick, Gauthaman Murali, Tushar Krishna, Sung Kyu Lim, Arijit Raychowdhury
2020	J	`jnl`	Counting Cards: Exploiting Weight and Variance Distributions for Robust Compute In-Memory. CoRR Brian Crafton, Samuel Spetalnick, Arijit Raychowdhury
2020	—	`conf`	Deep Learning Side-Channel Attack Resilient AES-256 using Current Domain Signature Attenuation in 65nm CMOS. CICC Debayan Das, Josef Danial, Anupam Golder, Santosh Ghosh, Arijit Raychowdhury, Shreyas Sen
2020	J	`jnl`	EM-X-DL: Efficient Cross-Device Deep Learning Side-Channel Attack with Noisy EM Signatures. CoRR Josef Danial, Debayan Das, Anupam Golder, Santosh Ghosh, Arijit Raychowdhury, Shreyas Sen
2020	J	`jnl`	FerroElectronics for Edge Intelligence. IEEE Micro Ali Keshavarzi, Kai Ni, Wilbert van den Hoek, Suman Datta, Arijit Raychowdhury
2020	C	`conf`	Hardware-Aware Pruning of DNNs using LFSR-Generated Pseudo-Random Indices. ISCAS Foroozan Karimzadeh, Ningyuan Cao, Brian Crafton, Justin Romberg, Arijit Raychowdhury
2020	J	`jnl`	Learning to Walk: Bio-Mimetic Hexapod Locomotion via Reinforcement-Based Spiking Central Pattern Generation. IEEE J. Emerg. Sel. Topics Circuits Syst. Ashwin Sanjay Lele, Yan Fang, Justin Ting, Arijit Raychowdhury
2020	—	`conf`	Learning to Walk: Spike Based Reinforcement Learning for Hexapod Robot Central Pattern Generation. AICAS Ashwin Sanjay Lele, Yan Fang, Justin Ting, Arijit Raychowdhury
2020	J	`jnl`	Learning to Walk: Spike Based Reinforcement Learning for Hexapod Robot Central Pattern Generation. CoRR Ashwin Sanjay Lele, Yan Fang, Justin Ting, Arijit Raychowdhury
2020	J	`jnl`	Masked Face Recognition for Secure Authentication. CoRR Aqeel Anwar, Arijit Raychowdhury
2020	C	`conf`	Memory and Energy Efficient Method Toward Sparse Neural Network Using LFSR Indexing. VLSI-SOC Foroozan Karimzadeh, Arijit Raychowdhury
2020	—	`conf`	Multilevel Signaling for High-Speed Chiplet-to-Chiplet Communication. VLSI-SoC (Selected Papers) Rakshith Saligram, Ankit Kaul, Muhannad S. Bakir, Arijit Raychowdhury
2020	—	`conf`	Non-isolated 48V-to-1V Heterogeneous Integrated Voltage Converters for High Performance Computing in Data Centers. MWSCAS Minxiang Gong, Xin Zhang, Arijit Raychowdhury
2020	J	`jnl`	OPTIMO: A 65-nm 279-GOPS/W 16-b Programmable Spatial-Array Processor with On-Chip Network for Solving Distributed Optimizations via the Alternating Direction Method of Multipliers. IEEE J. Solid State Circuits Muya Chang, Li-Hsiang Lin, Justin Romberg, Arijit Raychowdhury
2020	C	`conf`	Online Reward-Based Training of Spiking Central Pattern Generator for Hexapod Locomotion. VLSI-SOC Ashwin Sanjay Lele, Yan Fang, Justin Ting, Arijit Raychowdhury
2020	J	`jnl`	SCNIFFER: Low-Cost, Automated, Efficient Electromagnetic Side-Channel Sniffing. IEEE Access Josef Danial, Debayan Das, Santosh Ghosh, Arijit Raychowdhury, Shreyas Sen
2020	—	`conf`	Statistical Array Allocation and Partitioning for Compute In-Memory Fabrics. VLSI-SoC (Selected Papers) Brian Crafton, Samuel Spetalnick, Gauthaman Murali, Tushar Krishna, Sung Kyu Lim, Arijit Raychowdhury
2020	—	`conf`	XBAROPT - Enabling Ultra-Pipelined, Novel STT MRAM Based Processing-in-Memory DNN Accelerator. AICAS Aqeel Anwar, Arijit Raychowdhury, Ryan Hatcher, Titash Rakshit
2019	J	`jnl`	A 55-nm, 1.0-0.4V, 1.25-pJ/MAC Time-Domain Mixed-Signal Neuromorphic Accelerator With Stochastic Synapses for Reinforcement Learning in Autonomous Mobile Robots. IEEE J. Solid State Circuits Anvesha Amaravati, Saad Bin Nasir, Justin Ting, Insik Yoon, Arijit Raychowdhury
2019	—	`conf`	A 55nm 50nJ/encode 13nJ/decode Homomorphic Encryption Crypto-Engine for IoT Nodes to Enable Secure Computation on Encrypted Data. CICC Insik Yoon, Ningyuan Cao, Anvesha Amaravati, Arijit Raychowdhury
2019	—	`conf`	A 65nm 1.1-to-9.1TOPS/W Hybrid-Digital-Mixed-Signal Computing Platform for Accelerating Model-Based and Model-Free Swarm Robotics. ISSCC Ningyuan Cao, Muya Chang, Arijit Raychowdhury
2019	—	`conf`	A 7nm All-Digital Unified Voltage and Frequency Regulator Based on a High-Bandwidth 2-Phase Buck Converter with Package Inductors. ISSCC Francois Atallah, Keith A. Bowman, Hoan Nguyen, Jihoon Jeong, Daniel Yingling, Yu Sun, Brad Appel, Anthony Polomik, Mahesh Harinath, Joshua Morelli, Thomas Moore, Nathaniel Reeves, Amer Cassier, Arijit Raychowdhury
2019	—	`conf`	A 7nm Leakage-Current-Supply Circuit for LDO Dropout Voltage Reduction. VLSI Circuits Keith A. Bowman, Samantak Gangopadhyay, Francois Atallah, Hoan Nguyen, Jihoon Jeong, Daniel Yingling, Anthony Polomik, Mahesh Harinath, Nathaniel Reeves, Amer Cassier, Brad Appel, Arijit Raychowdhury
2019	J	`jnl`	Appearance-based Gesture recognition in the compressed domain. CoRR Shaojie Xu, Anvesha Amaravati, Justin Romberg, Arijit Raychowdhury
2019	J	`jnl`	Autonomous Navigation via Deep Reinforcement Learning for Resource Constraint Edge Nodes using Transfer Learning. CoRR Aqeel Anwar, Arijit Raychowdhury
2019	J	`jnl`	Computing With Networks of Oscillatory Dynamical Systems. Proc. IEEE Arijit Raychowdhury, Abhinav Parihar, Gus Henry Smith, Vijaykrishnan Narayanan, György Csaba, Matthew Jerry, Wolfgang Porod, Suman Datta
2019	J	`jnl`	Context-Aware Intelligence in Resource-Constrained IoT Nodes: Opportunities and Challenges. IEEE Des. Test Baibhab Chatterjee, Shreyas Sen, Ningyuan Cao, Arijit Raychowdhury
2019	J	`jnl`	Design space exploration of Ferroelectric FET based Processing-in-Memory DNN Accelerator. CoRR Insik Yoon, Matthew Jerry, Suman Datta, Arijit Raychowdhury
2019	J	`jnl`	Direct Feedback Alignment with Sparse Connections for Local Learning. CoRR Brian Crafton, Abhinav Parihar, Evan Gebhardt, Arijit Raychowdhury
2019	Misc	`conf`	Efficient Signal Reconstruction via Distributed Least Square Optimization on a Systolic FPGA Architecture. ICASSP Muya Chang, Samantak Gangopadhyay, Tomer Hamam, Justin Romberg, Arijit Raychowdhury
2019	J	`jnl`	Guest Editors' Introduction: Intelligent Resource-Constrained Sensor Nodes. IEEE Des. Test Shreyas Sen, Arijit Raychowdhury, Shih-Lien Lu
2019	J	`jnl`	Hardware-aware Pruning of DNNs using LFSR-Generated Pseudo-Random Indices. CoRR Foroozan Karimzadeh, Ningyuan Cao, Brian Crafton, Justin Romberg, Arijit Raychowdhury
2019	J	`jnl`	Hierarchical Memory System With STT-MRAM and SRAM to Support Transfer and Real-Time Reinforcement Learning in Autonomous Drones. IEEE J. Emerg. Sel. Topics Circuits Syst. Insik Yoon, Malik Aqeel Anwar, Rajiv V. Joshi, Titash Rakshit, Arijit Raychowdhury
2019	A	`conf`	Local Learning in RRAM Neural Networks with Sparse Direct Feedback Alignment. ISLPED Brian Crafton, Matt West, Padip Basnet, Eric Vogel, Arijit Raychowdhury
2019	—	`conf`	Optimo: A 65Nm 270Mhz 143.2Mw Programmable Spatial-Array-Processor With A Hierarchical Multi-Cast On-Chip Network For Solving Distributed Optimizations. CICC Muya Chang, Li-Hsiang Lin, Justin Romberg, Arijit Raychowdhury
2019	J	`jnl`	Practical Approaches Toward Deep-Learning-Based Cross-Device Power Side-Channel Attack. IEEE Trans. Very Large Scale Integr. Syst. Anupam Golder, Debayan Das, Josef Danial, Santosh Ghosh, Shreyas Sen, Arijit Raychowdhury
2019	A	`conf`	Rebooting Our Computing Models. DATE Patsy Cadareanu, N. Reddy C, Carmen G. Almudéver, A. Khanna, Arijit Raychowdhury, Suman Datta, Koen Bertels, Vijayakrishan Narayanan, Massimiliano Di Ventra, Pierre-Emmanuel Gaillardon
2019	J	`jnl`	SCNIFFER: Low-Cost, Automated, EfficientElectromagnetic Side-Channel Sniffing. CoRR Josef Danial, Debayan Das, Santosh Ghosh, Arijit Raychowdhury, Shreyas Sen
2019	A	`conf`	Transfer and Online Reinforcement Learning in STT-MRAM Based Embedded Systems for Autonomous Drones. DATE Insik Yoon, Malik Aqeel Anwar, Titash Rakshit, Arijit Raychowdhury
2019	J	`jnl`	Transfer and Online Reinforcement Learning in STT-MRAM Based Embedded Systems for Autonomous Drones. CoRR Insik Yoon, Malik Aqeel Anwar, Titash Rakshit, Arijit Raychowdhury
2019	A*	`conf`	X-DeepSCA: Cross-Device Deep Learning Side Channel Attack. DAC Debayan Das, Anupam Golder, Josef Danial, Santosh Ghosh, Arijit Raychowdhury, Shreyas Sen
2019	J	`jnl`	X-DeepSCA: Cross-Device Deep Learning Side Channel Attack. IACR Cryptol. ePrint Arch. Debayan Das, Anupam Golder, Josef Danial, Santosh Ghosh, Arijit Raychowdhury, Shreyas Sen
2018	J	`jnl`	A 130 nm 165 nJ/frame Compressed-Domain Smashed-Filter-Based Mixed-Signal Classifier for "In-Sensor" Analytics in Smart Cameras. IEEE Trans. Circuits Syst. II Express Briefs Anvesha Amaravati, Shaojie Xu, Justin Romberg, Arijit Raychowdhury
2018	—	`conf`	A 55nm time-domain mixed-signal neuromorphic accelerator with stochastic synapses and embedded reinforcement learning for autonomous micro-robots. ISSCC Anvesha Amaravati, Saad Bin Nasir, Sivaram Thangadurai, Insik Yoon, Arijit Raychowdhury
2018	C	`conf`	A 65nm, 1.15-0.15V, 99.99% Current-efficient Digital Low Dropout Regulator with Asynchronous Non-linear Control for Droop Mitigation. ISCAS Saad Bin Nasir, Anto Kavungal Davis, Mohamed Lamine Faycal Bellaredj, Madhavan Swaminathan, Arijit Raychowdhury, Adam Beece, Don Disney, Yong Wang, Hesam Fathi Moghadam, Eric Soenen, Jongku Kang, Yasuhiko Mano, Tomoharu Fuji
2018	—	`conf`	A FeFET Based Processing-In-Memory Architecture for Solving Distributed Least-Square Optimizations. DRC Insik Yoon, Muya Chang, Kai Ni, Matthew Jerry, Samantak Gangopadhyay, Gus Henry Smith, Tomer Hamam, Vijayakrishan Narayanan, Justin Romberg, Shih-Lien Lu, Suman Datta, Arijit Raychowdhury
2018	J	`jnl`	A Light-Powered Smart Camera With Compressed Domain Gesture Detection. IEEE Trans. Circuits Syst. Video Technol. Anvesha Amaravati, Shaojie Xu, Ningyuan Cao, Justin Romberg, Arijit Raychowdhury
2018	J	`jnl`	A Reconfigurable Hybrid Low Dropout Voltage Regulator for Wide-Range Power Supply Noise Rejection and Energy-Efficiency Trade-Off. IEEE Trans. Circuits Syst. II Express Briefs Saad Bin Nasir, Shreyas Sen, Arijit Raychowdhury
2018	J	`jnl`	ASNI: Attenuated Signature Noise Injection for Low-Overhead Power Side-Channel Attack Immunity. IEEE Trans. Circuits Syst. I Regul. Pap. Debayan Das, Shovan Maity, Saad Bin Nasir, Santosh Ghosh, Arijit Raychowdhury, Shreyas Sen
2018	C	`conf`	Computing with Coupled Oscillators: Theory, Devices, and Applications. ISCAS György Csaba, Arijit Raychowdhury, Suman Datta, Wolfgang Porod
2018	—	`conf`	Dynamics of Coupled Systems and their Computing Properties Invited Paper : Invited Paper. NEWCAS Abhinav Parihar, Anvesha Amaravati, Matthew Jerry, Suman Datta, Arijit Raychowdhury
2018	J	`jnl`	Modeling and Analysis of Magnetic Field Induced Coupling on Embedded STT-MRAM Arrays. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Insik Yoon, Arijit Raychowdhury
2018	J	`jnl`	NAVREN-RL: Learning to fly in real environment via end-to-end deep reinforcement learning using monocular images. CoRR Malik Aqeel Anwar, Arijit Raychowdhury
2018	—	`conf`	NavREn-Rl: Learning to fly in real environment via end-to-end deep reinforcement learning using monocular images. M2VIP Malik Aqeel Anwar, Arijit Raychowdhury
2018	J	`jnl`	Smart Sensing for HVAC Control: Collaborative Intelligence in Optical and IR Cameras. IEEE Trans. Ind. Electron. Ningyuan Cao, Justin Ting, Shreyas Sen, Arijit Raychowdhury
2018	J	`jnl`	Switched-Mode-Control Based Hybrid LDO for Fine-Grain Power Management of Digital Load Circuits. IEEE J. Solid State Circuits Saad Bin Nasir, Shreyas Sen, Arijit Raychowdhury
2017	—	`conf`	A 65nm 376nA 0.4V linear classifier using time-based matrix-multiplying ADC with non-linearity aware training. A-SSCC Amaravati Anvesha, Arijit Raychowdhury
2017	—	`conf`	A 65nm compressive-sensing time-based ADC with embedded classification and INL-aware training for arrhythmia detection. BioCAS Amaravati Anvesha, Shaojie Xu, Justin Romberg, Arijit Raychowdhury
2017	Misc	`conf`	Appearance-based gesture recognition in the compressed domain. ICASSP Shaojie Xu, Anvesha Amaravati, Justin Romberg, Arijit Raychowdhury
2017	—	`conf`	Collaborative intelligence in optical/IR camera based wireless sensor nodes for HVAC control. IEEE SENSORS Ningyuan Cao, Shreyas Sen, Arijit Raychowdhury
2017	B	`conf`	Computational paradigms using oscillatory networks based on state-transition devices. IJCNN Abhinav Parihar, Nikhil Shukla, Matthew Jerry, Suman Datta, Arijit Raychowdhury
2017	A	`conf`	Connecting spectral techniques for graph coloring and eigen properties of coupled dynamics: A pathway for solving combinatorial optimizations (Invited paper). ICCAD Abhinav Parihar, Nikhil Shukla, Matthew Jerry, Suman Datta, Arijit Raychowdhury
2017	—	`conf`	Digitally-assisted leakage current supply circuit for reducing the analog LDO minimum dropout voltage. CICC Samantak Gangopadhyay, Saad Bin Nasir, Hoan Nguyen, Jihoon Jeong, Francois Atallah, Keith A. Bowman, Arijit Raychowdhury
2017	J	`jnl`	High Efficiency Power Side-Channel Attack Immunity using Noise Injection in Attenuated Signature Domain. CoRR Debayan Das, Shovan Maity, Saad Bin Nasir, Santosh Ghosh, Arijit Raychowdhury, Shreyas Sen
2017	—	`conf`	High efficiency power side-channel attack immunity using noise injection in attenuated signature domain. HOST Debayan Das, Shovan Maity, Saad Bin Nasir, Santosh Ghosh, Arijit Raychowdhury, Shreyas Sen
2017	A*	`conf`	In Quest of the Next Information Processing Substrate: Extended Abstract: Invited. DAC Suman Datta, Alan C. Seabaugh, Michael T. Niemier, Arijit Raychowdhury, Darrell Schlom, Debdeep Jena, Huili Grace Xing, H.-S. Philip Wong, Eric Pop, Sayeef S. Salahuddin, Sumeet Kumar Gupta, Supratik Guha
2017	Misc	`conf`	Innovative practices session 4A variation-tolerant design of circuits/systems. VTS Arijit Raychowdhury
2017	J	`jnl`	Self-Optimizing IoT Wireless Video Sensor Node With In-Situ Data Analytics and Context-Driven Energy-Aware Real-Time Adaptation. IEEE Trans. Circuits Syst. I Regul. Pap. Ningyuan Cao, Saad Bin Nasir, Shreyas Sen, Arijit Raychowdhury
2017	J	`jnl`	Stochastic IMT (insulator-metal-transition) neurons: An interplay of thermal and threshold noise at bifurcation. CoRR Abhinav Parihar, Matthew Jerry, Suman Datta, Arijit Raychowdhury
2017	—	`conf`	Test and Reliability of Emerging Non-volatile Memories. ATS Said Hamdioui, Peyman Pouyan, Huawei Li, Ying Wang, Arijit Raychowdhury, Insik Yoon
2017	—	`conf`	Test challenges in embedded STT-MRAM arrays. ISQED Insik Yoon, Arijit Raychowdhury
2016	—	`conf`	A 130nm hybrid low dropout regulator based on switched mode control for digital load circuits. ESSCIRC Saad Bin Nasir, Shreyas Sen, Arijit Raychowdhury
2016	A	`conf`	A Light-powered, "Always-On", Smart Camera with Compressed Domain Gesture Detection. ISLPED Amaravati Anvesha, Shaojie Xu, Ningyuan Cao, Justin Romberg, Arijit Raychowdhury
2016	J	`jnl`	A Light-powered, Always-On, Smart Camera with Compressed Domain Gesture Detection. CoRR Amaravati Anvesha, Shaojie Xu, Ningyuan Cao, Justin Romberg, Arijit Raychowdhury
2016	C	`conf`	All-digital linear regulators with proactive and reactive gain-boosting for supply droop mitigation in digital load circuits. ISCAS Saad Bin Nasir, Arijit Raychowdhury
2016	J	`jnl`	Analysis of Defects and Variations in Embedded Spin Transfer Torque (STT) MRAM Arrays. IEEE J. Emerg. Sel. Topics Circuits Syst. Ashwin Chintaluri, Helia Naeimi, Suriyaprakash Natarajan, Arijit Raychowdhury
2016	J	`jnl`	Cache Design with Domain Wall Memory. IEEE Trans. Computers Rangharajan Venkatesan, Vivek Joy Kozhikkottu, Mrigank Sharad, Charles Augustine, Arijit Raychowdhury, Kaushik Roy, Anand Raghunathan
2016	J	`jnl`	Computing with Dynamical Systems Based on Insulator-Metal-Transition Oscillators. CoRR Abhinav Parihar, Nikhil Shukla, Matthew Jerry, Suman Datta, Arijit Raychowdhury
2016	A	`conf`	EMACS: Efficient MBIST architecture for test and characterization of STT-MRAM arrays. ITC Insik Yoon, Ashwin Chintaluri, Arijit Raychowdhury
2016	—	`conf`	Embedded hybrid LDO topologies for digital load circuits. APCCAS Saad Bin Nasir, Arijit Raychowdhury
2016	J	`jnl`	Enabling New Computation Paradigms with HyperFET - An Emerging Device. IEEE Trans. Multi Scale Comput. Syst. Wei-Yu Tsai, Xueqing Li, Matthew Jerry, Baihua Xie, Nikhil Shukla, Huichu Liu, Nandhini Chandramoorthy, Matthew Cotter, Arijit Raychowdhury, Donald M. Chiarulli, Steven P. Levitan, Suman Datta, John Sampson, Nagarajan Ranganathan, Vijaykrishnan Narayanan
2016	J	`jnl`	The Changing Computing Paradigm With Internet of Things: A Tutorial Introduction. IEEE Des. Test Sandip Ray, Yier Jin, Arijit Raychowdhury
2016	—	`conf`	UVFR: A Unified Voltage and Frequency Regulator with 500MHz/0.84V to 100KHz/0.27V operating range, 99.4% current efficiency and 27% supply guardband reduction. ESSCIRC Samantak Gangopadhyay, Saad Bin Nasir, A. Subramanian, Visvesh Sathe, Arijit Raychowdhury
2016	J	`jnl`	Vertex coloring of graphs via phase dynamics of coupled oscillatory networks. CoRR Abhinav Parihar, Nikhil Shukla, Matthew Jerry, Suman Datta, Arijit Raychowdhury
2015	—	`conf`	5.6 A 0.13μm fully digital low-dropout regulator with adaptive control and reduced dynamic stability for ultra-wide dynamic range. ISSCC Saad Bin Nasir, Samantak Gangopadhyay, Arijit Raychowdhury
2015	—	`conf`	A Model Study of Defects and Faults in Embedded Spin Transfer Torque (STT) MRAM Arrays. ATS Ashwin Chintaluri, Abhinav Parihar, Suriyaprakash Natarajan, Helia Naeimi, Arijit Raychowdhury
2015	J	`jnl`	A Model Study of an All-Digital, Discrete-Time and Embedded Linear Regulator. CoRR Saad Bin Nasir, Arijit Raychowdhury
2015	—	`conf`	A SAR Pipeline ADC Embedding Time Interleaved DAC Sharing for Ultra-low Power Camera Front Ends. VLSI-SoC (Selected Papers) Anvesha Amaravati, Manan Chugh, Arijit Raychowdhury
2015	C	`conf`	A time interleaved DAC sharing SAR Pipeline ADC for ultra-low power camera front ends. VLSI-SoC Anvesha Amaravati, Manan Chugh, Arijit Raychowdhury
2015	J	`jnl`	An Ultra-Low Power, "Always-On" Camera Front-End for Posture Detection in Body Worn Cameras Using Restricted Boltzman Machines. IEEE Trans. Multi Scale Comput. Syst. Soham Jayesh Desai, Mohammed Shoaib, Arijit Raychowdhury
2015	A*	`conf`	Integrated power management in IoT devices under wide dynamic ranges of operation. DAC Samantak Gangopadhyay, Saad Bin Nasir, Arijit Raychowdhury
2015	J	`jnl`	Modeling and Simulation of Vanadium Dioxide Relaxation Oscillators. IEEE Trans. Circuits Syst. I Regul. Pap. Paolo Maffezzoni, Luca Daniel, Nikhil Shukla, Suman Datta, Arijit Raychowdhury
2015	—	`conf`	Session 6 - Analog circuits using digital cells. CICC Jing Yang, Arijit Raychowdhury
2014	—	`conf`	5.7 A graphics execution core in 22nm CMOS featuring adaptive clocking, selective boosting and state-retentive sleep. ISSCC Carlos Tokunaga, Joseph F. Ryan, Charles Augustine, Jaydeep P. Kulkarni, Yi-Chun Shih, Stephen T. Kim, Rinkle Jain, Keith A. Bowman, Arijit Raychowdhury, Muhammad M. Khellah, James W. Tschanz, Vivek De
2014	J	`jnl`	A 32 nm Embedded, Fully-Digital, Phase-Locked Low Dropout Regulator for Fine Grained Power Management in Digital Circuits. IEEE J. Solid State Circuits Samantak Gangopadhyay, Dinesh Somasekhar, James W. Tschanz, Arijit Raychowdhury
2014	J	`jnl`	Exploiting Synchronization Properties of Correlated Electron Devices in a Non-Boolean Computing Fabric for Template Matching. IEEE J. Emerg. Sel. Topics Circuits Syst. Abhinav Parihar, Nikhil Shukla, Suman Datta, Arijit Raychowdhury
2014	A	`conf`	Modeling and analysis of digital linear dropout regulators with adaptive control for high efficiency under wide dynamic range digital loads. DATE Samantak Gangopadhyay, Youngtak Lee, Saad Bin Nasir, Arijit Raychowdhury
2014	—	`conf`	Modeling and analysis of system stability in a distributed power delivery network with embedded digital linear regulators. ISQED Saad Bin Nasir, Youngtak Lee, Arijit Raychowdhury
2014	A*	`conf`	Neuro Inspired Computing with Coupled Relaxation Oscillators. DAC Suman Datta, Nikhil Shukla, Matthew Cotter, Abhinav Parihar, Arijit Raychowdhury
2014	A	`conf`	The role of adaptation and resiliency in computation and power management. ICCAD Arijit Raychowdhury, Saad Bin Nasir, Samantak Gangopadhyay
2013	J	`jnl`	A 2.3 nJ/Frame Voice Activity Detector-Based Audio Front-End for Context-Aware System-On-Chip Applications in 32-nm CMOS. IEEE J. Solid State Circuits Arijit Raychowdhury, Carlos Tokunaga, Willem Marco Beltman, Michael Deisher, James W. Tschanz, Vivek De
2013	A	`conf`	Beyond charge based computation: Design space exploration of spin transfer torque based MRAMs for embedded applications. ISLPED Arijit Raychowdhury
2013	J	`jnl`	Introduction to the special issue on memory technologies. ACM J. Emerg. Technol. Comput. Syst. Bipul C. Paul, Arijit Raychowdhury
2013	—	`conf`	Pulsed READ in spin transfer torque (STT) memory bitcell for lower READ disturb. NANOARCH Arijit Raychowdhury
2013	A	`conf`	Spin torque devices in embedded memory: model studies and design space exploration. ICCAD Arijit Raychowdhury
2012	—	`conf`	A 2.3nJ/frame Voice Activity Detector based audio front-end for context-aware System-on-Chip applications in 32nm CMOS. CICC Arijit Raychowdhury, Carlos Tokunaga, Willem Marco Beltman, Michael Deisher, James W. Tschanz, Vivek De
2012	—	`conf`	A fully-digital phase-locked low dropout regulator in 32nm CMOS. VLSIC Arijit Raychowdhury, Dinesh Somasekhar, James W. Tschanz, Vivek De
2012	A	`conf`	Design for test and reliability in ultimate CMOS. DATE Michael Nicolaidis, Lorena Anghel, Nacer-Eddine Zergainoh, Yervant Zorian, Tanay Karnik, Keith A. Bowman, James W. Tschanz, Shih-Lien Lu, Carlos Tokunaga, Arijit Raychowdhury, Muhammad M. Khellah, Jaydeep P. Kulkarni, Vivek De, Dimiter Avresky
2012	A	`conf`	TapeCache: a high density, energy efficient cache based on domain wall memory. ISLPED Rangharajan Venkatesan, Vivek Joy Kozhikkottu, Charles Augustine, Arijit Raychowdhury, Kaushik Roy, Anand Raghunathan
2011	J	`jnl`	A 45 nm Resilient Microprocessor Core for Dynamic Variation Tolerance. IEEE J. Solid State Circuits Keith A. Bowman, James W. Tschanz, Shih-Lien Lu, Paolo A. Aseron, Muhammad M. Khellah, Arijit Raychowdhury, Bibiche M. Geuskens, Carlos Tokunaga, Chris Wilkerson, Tanay Karnik, Vivek K. De
2011	J	`jnl`	All-Digital Circuit-Level Dynamic Variation Monitor for Silicon Debug and Adaptive Clock Control. IEEE Trans. Circuits Syst. I Regul. Pap. Keith A. Bowman, Carlos Tokunaga, James W. Tschanz, Arijit Raychowdhury, Muhammad M. Khellah, Bibiche M. Geuskens, Shih-Lien Lu, Paolo A. Aseron, Tanay Karnik, Vivek K. De
2011	—	`ch.`	Digital Subthreshold for Ultra-Low Power Operation: Prospects and Challenges. Low-Power Variation-Tolerant Design in Nanometer Silicon Bipul C. Paul, Arijit Raychowdhury
2011	J	`jnl`	Error Detection and Correction in Microprocessor Core and Memory Due to Fast Dynamic Voltage Droops. IEEE J. Emerg. Sel. Topics Circuits Syst. Arijit Raychowdhury, Jim Tschanz, Keith A. Bowman, Shih-Lien Lu, Paolo A. Aseron, Muhammad M. Khellah, Bibiche M. Geuskens, Carlos Tokunaga, Chris Wilkerson, Tanay Karnik, Vivek De
2011	J	`jnl`	Tunable Replica Bits for Dynamic Variation Tolerance in 8T SRAM Arrays. IEEE J. Solid State Circuits Arijit Raychowdhury, Bibiche M. Geuskens, Keith A. Bowman, James W. Tschanz, Shih-Lien Lu, Tanay Karnik, Muhammad M. Khellah, Vivek K. De
2010	—	`conf`	A 45nm resilient and adaptive microprocessor core for dynamic variation tolerance. ISSCC James W. Tschanz, Keith A. Bowman, Shih-Lien Lu, Paolo A. Aseron, Muhammad M. Khellah, Arijit Raychowdhury, Bibiche M. Geuskens, Carlos Tokunaga, Chris Wilkerson, Tanay Karnik, Vivek De
2010	J	`jnl`	Digital Computation in Subthreshold Region for Ultralow-Power Operation: A Device-Circuit-Architecture Codesign Perspective. Proc. IEEE Sumeet Kumar Gupta, Arijit Raychowdhury, Kaushik Roy
2010	—	`conf`	Dynamic variation monitor for measuring the impact of voltage droops on microprocessor clock frequency. CICC Keith A. Bowman, Carlos Tokunaga, James W. Tschanz, Arijit Raychowdhury, Muhammad M. Khellah, Bibiche M. Geuskens, Shih-Lien Lu, Paolo A. Aseron, Tanay Karnik, Vivek De
2010	A	`conf`	Optimization of burn-in test for many-core processors through adaptive spatiotemporal power migration. ITC Minki Cho, Nikhil Sathe, Arijit Raychowdhury, Saibal Mukhopadhyay
2010	—	`conf`	PVT-and-aging adaptive wordline boosting for 8T SRAM power reduction. ISSCC Arijit Raychowdhury, Bibiche M. Geuskens, Jaydeep P. Kulkarni, James W. Tschanz, Keith A. Bowman, Tanay Karnik, Shih-Lien Lu, Vivek De, Muhammad M. Khellah
2010	—	`conf`	Resilient design in scaled CMOS for energy efficiency. ASP-DAC James W. Tschanz, Keith A. Bowman, Muhammad M. Khellah, Chris Wilkerson, Bibiche M. Geuskens, Dinesh Somasekhar, Arijit Raychowdhury, Jaydeep P. Kulkarni, Carlos Tokunaga, Shih-Lien Lu, Tanay Karnik, Vivek De
2010	A	`conf`	Resilient microprocessor design for high performance & energy efficiency. ISLPED Keith A. Bowman, James W. Tschanz, Shih-Lien Lu, Paolo A. Aseron, Muhammad M. Khellah, Arijit Raychowdhury, Bibiche M. Geuskens, Carlos Tokunaga, Chris Wilkerson, Tanay Karnik, Vivek De
2009	J	`jnl`	A 1.05 V 1.6 mW, 0.45°C 3σ Resolution ΣΔ Based Temperature Sensor With Parasitic Resistance Compensation in 32 nm Digital CMOS Process. IEEE J. Solid State Circuits Hasnain Lakdawala, Y. William Li, Arijit Raychowdhury, Greg Taylor, Krishnamurthy Soumyanath
2009	—	`conf`	A 1.05V 1.6mW 0.45°C 3σ-resolution ΔΣ-based temperature sensor with parasitic-resistance compensation in 32nm CMOS. ISSCC Y. William Li, Hasnain Lakdawala, Arijit Raychowdhury, Greg Taylor, Krishnamurthy Soumyanath
2009	—	`conf`	PETE: A device/circuit analysis framework for evaluation and comparison of charge based emerging devices. ISQED Charles Augustine, Arijit Raychowdhury, Yunfei Gao, Mark S. Lundstrom, Kaushik Roy
2008	J	`jnl`	Arbitrary Two-Pattern Delay Testing Using a Low-Overhead Supply Gating Technique. J. Electron. Test. Swarup Bhunia, Hamid Mahmoodi, Arijit Raychowdhury, Kaushik Roy
2007	J	`jnl`	Carbon Nanotube Electronics: Design of High-Performance and Low-Power Digital Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. Arijit Raychowdhury, Kaushik Roy
2006	J	`jnl`	A Novel Delay Fault Testing Methodology Using Low-Overhead Built-In Delay Sensor. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Swaroop Ghosh, Swarup Bhunia, Arijit Raychowdhury, Kaushik Roy
2006	A*	`conf`	A high density, carbon nanotube capacitor for decoupling applications. DAC Mark M. Budnik, Arijit Raychowdhury, Aditya Bansal, Kaushik Roy
2006	A	`conf`	Analysis of super cut-off transistors for ultralow power digital logic circuits. ISLPED Arijit Raychowdhury, Xuanyao Fong, Qikai Chen, Kaushik Roy
2006	C	`conf`	Delay Fault Localization in Test-Per-Scan BIST Using Built-In Delay Sensor. IOLTS Swaroop Ghosh, Swarup Bhunia, Arijit Raychowdhury, Kaushik Roy
2006	—	`conf`	Integrated MEMS Switches for Leakage Control of Battery Operated Systems. CICC Arijit Raychowdhury, Jeong-Il Kim, Dimitrios Peroulis, Kaushik Roy
2006	J	`jnl`	Leakage Power Analysis and Reduction for Nanoscale Circuits. IEEE Micro Amit Agarwal, Saibal Mukhopadhyay, Arijit Raychowdhury, Kaushik Roy, Chris H. Kim
2006	J	`jnl`	Modeling of metallic carbon-nanotube interconnects for circuit simulations and a comparison with Cu interconnects for scaled technologies. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Arijit Raychowdhury, Kaushik Roy
2006	J	`jnl`	Novel Low-Overhead Operand Isolation Techniques for Low-Power Datapath Synthesis. IEEE Trans. Very Large Scale Integr. Syst. Nilanjan Banerjee, Arijit Raychowdhury, Kaushik Roy, Swarup Bhunia, Hamid Mahmoodi
2006	A	`conf`	Ultralow power computing with sub-threshold leakage: a comparative study of bulk and SOI technologies. DATE Arijit Raychowdhury, Bipul Chandra Paul, Swarup Bhunia, Kaushik Roy
2005	C	`conf`	A Feasibility Study of Subthreshold SRAM Across Technology Generations. ICCD Arijit Raychowdhury, Saibal Mukhopadhyay, Kaushik Roy
2005	A	`conf`	A Novel Low-overhead Delay Testing Technique for Arbitrary Two-Pattern Test Application. DATE Swarup Bhunia, Hamid Mahmoodi-Meimand, Arijit Raychowdhury, Kaushik Roy
2005	C	`conf`	A Novel On-Chip Delay Measurement Hardware for Efficient Speed-Binning. IOLTS Arijit Raychowdhury, Swaroop Ghosh, Kaushik Roy
2005	B	`conf`	A novel delay fault testing methodology using on-chip low-overhead delay measurement hardware at strategic probe points. ETS Arijit Raychowdhury, Swaroop Ghosh, Swarup Bhunia, Debjyoti Ghosh, Kaushik Roy
2005	J	`jnl`	Accurate estimation of total leakage in nanometer-scale bulk CMOS circuits based on device geometry and doping profile. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Saibal Mukhopadhyay, Arijit Raychowdhury, Kaushik Roy
2005	J	`jnl`	Computing with subthreshold leakage: device/circuit/architecture co-design for ultralow-power subthreshold operation. IEEE Trans. Very Large Scale Integr. Syst. Arijit Raychowdhury, Bipul Chandra Paul, Swarup Bhunia, Kaushik Roy
2005	J	`jnl`	Defect Oriented Testing of Analog Circuits Using Wavelet Analysis of Dynamic Supply Current. J. Electron. Test. Swarup Bhunia, Arijit Raychowdhury, Kaushik Roy
2005	J	`jnl`	Energy-Recovery Techniques to Reduce On-Chip Power Density in Molecular Nanotechnologies. IEEE Trans. Circuits Syst. I Regul. Pap. Myeong-Eun Hwang, Arijit Raychowdhury, Kairshik Roy
2005	J	`jnl`	Frequency Specification Testing of Analog Filters Using Wavelet Transform of Dynamic Supply Current. J. Electron. Test. Swarup Bhunia, Arijit Raychowdhury, Kaushik Roy
2005	—	`conf`	Leakage Current Based Stabilization Scheme for Robust Sense-Amplifier Design for Yield Enhancement in Nano-scale SRAM. Asian Test Symposium Saibal Mukhopadhyay, Arijit Raychowdhury, Hamid Mahmoodi-Meimand, Kaushik Roy
2005	C	`conf`	Novel Low-Overhead Operand Isolation Techniques for Low-Power Datapath Synthesis. ICCD Nilanjan Banerjee, Arijit Raychowdhury, Swarup Bhunia, Hamid Mahmoodi-Meimand, Kaushik Roy
2004	—	`conf`	A Novel Multiple-Valued Logic Design Using Ballistic Carbon Nanotube FETs. ISMVL Arijit Raychowdhury, Kaushik Roy
2004	A	`conf`	A circuit model for carbon nanotube interconnects: comparative study with Cu interconnects for scaled technologies. ICCAD Arijit Raychowdhury, Kaushik Roy
2004	J	`jnl`	A circuit-compatible model of ballistic carbon nanotube field-effect transistors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Arijit Raychowdhury, Saibal Mukhopadhyay, Kaushik Roy
2004	A	`conf`	Device optimization for ultra-low power digital sub-threshold operation. ISLPED Bipul Chandra Paul, Arijit Raychowdhury, Kaushik Roy
2004	—	`conf`	Effectiveness of energy recovery techniques in reducing on-chip power density in molecular nano-technologies. ISCAS (3) Myeong-Eun Hwang, Arijit Raychowdhury, Kaushik Roy
2004	—	`conf`	First Level Hold: A Novel Low-Overhead Delay Fault Testing Technique. DFT Swarup Bhunia, Hamid Mahmoodi-Meimand, Arijit Raychowdhury, Kaushik Roy
2004	—	`conf`	Frequency Specification Testing of Analog Filters Using Wavelet Transform of Dynamic Supply Current. ISQED Swarup Bhunia, Arijit Raychowdhury, Kaushik Roy
2004	Misc	`conf`	Modeling and Estimation of Leakage in Sub-90nm Devices. VLSI Design Arijit Raychowdhury, Saibal Mukhopadhyay, Kaushik Roy
2004	A	`conf`	Trim Bit Setting of Analog Filters Using Wavelet-Based Supply Current Analysis. DATE Swarup Bhunia, Arijit Raychowdhury, Kaushik Roy
2003	A*	`conf`	Accurate estimation of total leakage current in scaled CMOS logic circuits based on compact current modeling. DAC Saibal Mukhopadhyay, Arijit Raychowdhury, Kaushik Roy
2003	A	`conf`	Modeling of Ballistic Carbon Nanotube Field Effect Transistors for Efficient Circuit Simulation. ICCAD Arijit Raychowdhury, Saibal Mukhopadhyay, Kaushik Roy