Arighna Deb

30 papers A 4C 2Misc 1Journal 10Unranked 13
YearRankTypeTitle / Venue / Authors
2025 — conf
Unlocking the Benefits of Dynamic Quantum Circuits in Resource Constraint Architecture.
ISVLSI
Abhoy Kole, Mohammed E. Djeridane, Arighna Deb, Kamalika Datta, Indranil Sengupta, Rolf Drechsler
2024 C conf
Design Objectives for Synthesis of Graphene PN Junction Circuits Based on Two-Level Representation.
DSD
Subrata Das, Arighna Deb, Petr Fiser, Debesh Kumar Das
2024 A conf
Dynamic Realization of Multiple Control Toffoli Gate.
DATE
Abhoy Kole, Arighna Deb, Kamalika Datta, Rolf Drechsler
2024 Misc conf
In-Memory SAT-Solver for Self-Verification of Programmable Memristive Architectures.
VLSID
Fatemeh Shirinzadeh, Arighna Deb, Saeideh Shirinzadeh, Abhoy Kole, Kamalika Datta, Rolf Drechsler
2024 — conf
Leveraging ReRAM Sequence Graphs for Efficient Mapping of Binary Adders in ReRAM Crossbars.
VDAT
Pragnya Dhal, Arighna Deb, Subrata Das, Debesh Kumar Das
2024 J jnl
ReSG: A Data Structure for Verification of Majority-based In-memory Computing on ReRAM Crossbars.
ACM Trans. Embed. Comput. Syst.
Kousik Bhunia, Arighna Deb, Kamalika Datta, Muhammad Hassan, Saeideh Shirinzadeh, Rolf Drechsler
2023 — conf
Automated Equivalence Checking Method for Majority Based In-Memory Computing on ReRAM Crossbars.
ASP-DAC
Arighna Deb, Kamalika Datta, Muhammad Hassan, Saeideh Shirinzadeh, Rolf Drechsler
2023 A conf
Extending the Design Space of Dynamic Quantum Circuits for Toffoli based Network.
DATE
Abhoy Kole, Arighna Deb, Kamalika Datta, Rolf Drechsler
2023 J jnl
Impact of sneak paths on in-memory logic design in memristive crossbars.
it Inf. Technol.
Kamalika Datta, Arighna Deb, Abhoy Kole, Rolf Drechsler
2023 — conf
Switching Activity Reduction in Graphene PN Junction Circuits using Circuit Re-structuring.
ISDCS
Subrata Das, Arighna Deb, Petr Fiser
2023 — conf
Verification of In-Memory Logic Design using ReRAM Crossbars.
NEWCAS
Kamalika Datta, Arighna Deb, Fatemeh Shirinzadeh, Abhoy Kole, Saeideh Shirinzadeh, Rolf Drechsler
2021 J jnl
An Efficient Design for Testability Approach of Reversible Logic Circuits.
J. Circuits Syst. Comput.
Joyati Mondal, Arighna Deb, Debesh K. Das
2021 J jnl
Design Space Exploration of Matrix-Matrix Convolution Operation.
J. Circuits Syst. Comput.
Piyalee Behera, Arighna Deb
2021 J jnl
Exploring the Potential Benefits of Alternative Quantum Computing Architectures.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Arighna Deb, Gerhard W. Dueck, Robert Wille
2020 A conf
Towards Exploring the Potential of Alternative Quantum Computing Architectures.
DATE
Arighna Deb, Gerhard W. Dueck, Robert Wille
2019 — conf
Delay Efficient All Optical Carry Lookahead Adder.
VDAT
Sayantani Roy, Arighna Deb, Debesh K. Das
2019 — conf
Detailed Fault Model for Physical Quantum Circuits.
ATS
Arighna Deb, Debesh K. Das
2017 J jnl
An iterative structure for synthesizing symmetric functions using quantum-dot cellular automata.
Microprocess. Microsystems
Arighna Deb, Debesh K. Das
2017 A conf
Dedicated synthesis for MZI-based optical circuits based on AND-inverter graphs.
ICCAD
Arighna Deb, Robert Wille, Rolf Drechsler
2017 — conf
OR-Inverter Graphs for the Synthesis of Optical Circuits.
ISMVL
Arighna Deb, Robert Wille, Rolf Drechsler
2017 J jnl
Synthesis of optical circuits using binary decision diagrams.
Integr.
Arighna Deb, Robert Wille, Oliver Keszöcze, Saeideh Shirinzadeh, Rolf Drechsler
2016 J jnl
Gates vs. Splitters: Contradictory Optimization Objectives in the Synthesis of Optical Circuits.
ACM J. Emerg. Technol. Comput. Syst.
Arighna Deb, Robert Wille, Oliver Keszöcze, Stefan Hillmich, Rolf Drechsler
2016 J jnl
Reversible Synthesis of Symmetric Functions with a Simple Regular Structure and Easy Testability.
ACM J. Emerg. Technol. Comput. Syst.
Arighna Deb, Debesh K. Das, Hafizur Rahaman, Robert Wille, Rolf Drechsler, Bhargab B. Bhattacharya
2015 — conf
An Efficient Reduction of Common Control Lines for Reversible Circuit Optimization.
ISMVL
Arighna Deb, Robert Wille, Rolf Drechsler, Debesh K. Das
2014 J jnl
A Modular Design to Synthesize Symmetric Functions Using Quantum Quaternary Logic.
J. Low Power Electron.
Arighna Deb, Debesh Kumar Das, Susmita Sur-Kolay
2014 — conf
A regular network of symmetric functions in quantum-dot cellular automata.
VDAT
Arighna Deb, Debesh Kumar Das
2014 — conf
Synthesis of Symmetric Boolean Functions Using a Three-Stage Network.
ISED
Arighna Deb, Debesh K. Das, Bhargab B. Bhattacharya
2013 — conf
Modular Design for Symmetric Functions Using Quantum Quaternary Logic.
ISED
Arighna Deb, Debesh K. Das, Susmita Sur-Kolay
2013 C conf
Reversible Circuit Synthesis of Symmetric Functions Using a Simple Regular Structure.
RC
Arighna Deb, Debesh K. Das, Hafizur Rahaman, Bhargab B. Bhattacharya, Robert Wille, Rolf Drechsler
2013 — conf
Reversible synthesis of symmetric boolean functions based on unate decomposition.
ACM Great Lakes Symposium on VLSI
Arighna Deb, Debesh K. Das, Hafizur Rahaman, Bhargab B. Bhattacharya