Aria Eshraghi

11 papers C 2Journal 6Unranked 3
YearRankTypeTitle / Venue / Authors
2019 — conf
A 192-Virtual-Receiver 77/79GHz GMSK Code-Domain MIMO Radar System-on-Chip.
ISSCC
Vito Giannini, Marius Goldenberg, Aria Eshraghi, James Maligeorgos, Lysander Lim, Ryan Lobo, Dave Welland, Chung-Kai Chow, Andrew Dornbusch, Tim Dupuis, Struan Vaz, Fred Rush, Paul Bassett, Hong Kim, Monier Maher, Otto Schmid, Curtis Davis, Manju V. Hegde
2004 J jnl
A comparative analysis of parallel delta-sigma ADC architectures.
IEEE Trans. Circuits Syst. I Regul. Pap.
Aria Eshraghi, Terri S. Fiez
2003 J jnl
A time-interleaved parallel /ΔΣ A/D converter.
IEEE Trans. Circuits Syst. II Express Briefs
Aria Eshraghi, Terri S. Fiez
2002 J jnl
A CMOS transconductor with 80-dB SFDR up to 10 MHz.
IEEE J. Solid State Circuits
Uma Chilakapati, Terri S. Fiez, Aria Eshraghi
2001 — conf
A 3.3 V transconductor in 0.35 μm CMOS with 80 dB SFDR up to 10 MHz.
CICC
Uma Chilakapati, Terri S. Fiez, Aria Eshraghi
2000 J jnl
A 14-bit current-mode ΣΔ DAC based upon rotated data weighted averaging.
IEEE J. Solid State Circuits
Russell E. Radke, Aria Eshraghi, Terri S. Fiez
1999 — conf
A spurious-free delta-sigma DAC using rotated data weighted averaging.
CICC
Russell E. Radke, Aria Eshraghi, Terri S. Fiez
1998 J jnl
A Nyquist-rate delta-sigma A/D converter.
IEEE J. Solid State Circuits
Eric T. King, Aria Eshraghi, Ian Galton, Terri S. Fiez
1994 C conf
Asynchronus Implementation for the Add Compare Select Processor for Communication Systems.
ISCAS
Aria Eshraghi, Terri S. Fiez, Thomas R. Fischer
1994 C conf
Compact and Accurate MOST Model for Analog Circuit Hand Calculations.
ISCAS
Farbod Aram, Aria Eshraghi, Terri S. Fiez
1994 J jnl
Design of a new squaring function for the Viterbi algorithm.
IEEE J. Solid State Circuits
Aria Eshraghi, Terri S. Fiez, Kel D. Winters, Thomas R. Fischer